JPH03160495A - Image display device - Google Patents

Abstract

PURPOSE:To allow high-speed image formation by providing plural sets of graphic modules including image processors, frame buffers, etc., and simultaneously operating these sets. CONSTITUTION:The graphic modules 2, 3, 4 contg. the image processors 8, the frame buffers 7, etc., are connected in parallel to a host computer 1 and the plural image commands from the computer 1 are respectively supplied to the image processors 8 of the respective graphic modules 2, 3, 4. The respective plotting processing is executed simultaneously in the respective image processors 8. The time required for image formation is, therefore, the same as the time for one picture element and the images are eventually formed at a high speed even if the number of the images to be plotted increases. The plural images formed in such a manner are synthesized by a video signal synthesizer 5 and are displayed on a CRT display 6. The images are thus formed at a high speed even when the number of the images to be displayed increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image display device that displays characters, figures, images, etc.

[Conventional technology]

Generally, an image display device is provided with a frame buffer for storing image data, and an image is displayed on the frame buffer by an image processor based on an image command sent from a host computer. An image is displayed by reading out the contents of this frame buffer at an appropriate timing and supplying it to a CRT display.

FIG. 2 shows an example of the structure of a conventional image display device, and here, an image display device capable of displaying a plurality of independent color images will be exemplified and explained.

The image display device shown in FIG. 2 includes a plurality of frame buffers 31 to 34 for storing image data, etc., and images are displayed in response to image commands SI sent from a host computer 35 to the frame buffers 7y31 to 34. an image processor 36 for image processing and the frame buffer 31;
The image data stored in ~34 is converted into the actual color signal S,
a D/A converter 38 that converts the digital color signal S2 outputted from the color palette 37 into an analog video signal S,
a CRT display 39 for displaying a video signal S,
the image processor 36, the color palette 37, D/
A timing controller 40 is configured to provide the A converter 38 with a mask timing signal S, which is an appropriate timing signal for display, and an image display timing signal S.

In the image display device described above, in order to display a desired image on the CRT display 39, a predetermined image command S is sent from the host computer 35 to the image processor 36.
1 and sends a plurality of predetermined frame buffers 31 by a frame buffer control signal 56 and a frame buffer data/address signal St from the image processor 36.
A pit pattern corresponding to the target image is written into one of the frame buffers 34 to 34. Then, after converting this bit pattern into a target color signal S2 based on the color conversion table written in the color palette 37 while synchronizing with the image display timing signal Ss from the timing controller 40, the D/A The converter 38 converts it into an analog video signal S, and sends it to the CRT.
The signal is supplied to the display 39.

[Problem to be solved by the invention]

However, in the conventional system, once the image command S1 is sent from the host combiner 35 to the image processor 36 and processing is started, the next image command is sent while the image processor 36 is performing the drawing process. Unable to accept S1. Therefore, when drawing is performed using a plurality of frame buffers, there is a drawback that the image generation time becomes longer in proportion to the number of frame buffers.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image display device that enables high-speed image display by providing a plurality of graphic module sets including image processors, frame puffers, etc., and operating these modules simultaneously.

[Means to solve the problem]

In order to achieve the above object, the image display device of the present invention includes a frame buffer, an image processor that generates an image in the frame buffer based on an image command, and a digital signal read out from the frame buffer that converts the digital signal into an analog signal. a plurality of graphic modules including a D/A converter that converts the video signals into video signals; a host computer that commonly outputs image commands to the plurality of graphic modules; and a plurality of videos output by the plurality of graphic modules. The present invention is characterized by comprising a video signal combiner for combining signals, and a CRT display for displaying the combined video signal output from the video signal combiner.

[Effect]

In the image display device of the present invention, an image processor is connected to the host computer. Graphic modules including frame buffers etc. are connected in parallel, and multiple image commands from the host computer are supplied to the image processors of each graphic module, and each image processor simultaneously performs each drawing. Processing takes place.

Therefore, even if the number of images to be drawn increases, the time required for image formation is the same as one screen, and images are generated at high speed. The plurality of images thus formed are combined by a video signal synthesizer and displayed on a CRT display.

〔Example〕

DETAILED DESCRIPTION OF THE INVENTION Hereinafter, features of the present invention will be specifically described based on examples with reference to the drawings.

As shown in FIG. 1, the image display device of this embodiment includes a host computer 1 that outputs an image command S1, and a host computer 1 that receives this image command S+ and outputs different analog video signals S31*S32. +S
．． A plurality of graphic modules 2, to 4 generating 3
and a video signal synthesizer 5 which synthesizes the outputs of each of the graphic modules 2 to 4 and supplies the synthesized signal to a CRT display 6.

Each of the graphic modules 2 to 4 includes a frame buffer 7 for storing image data, an image processor 8 for generating an image in the frame buffer 7 based on the image command S1, and an image data stored in the frame buffer 7. a timing controller 9 that generates appropriate timing for displaying image data; a color palette 10 that converts the image data read from the frame buffer 7 into color signals; and a color palette 10 that converts the digital color signals into analog video signals. It is composed of a D/A converter 1l that converts into.

The host computer 1 commonly supplies an image command St to the image processor 8 and timing controller 9 of each graphic module 2 to 4, and also supplies a display synchronization signal S● to each timing controller 9 in common.

One graphics module executes only the commands to be executed among the image commands S1 issued by the host computer l. Among the image commands S, those related to image data such as drawing are executed by the image processor 8, and those related to display control, such as image size, display color range, and position displayed on the CRT display 6, are executed by timing. It is executed by the controller 9.

Among the image commands SI, those related to image data such as drawing are realized by the image processor 8 performing appropriate operations on the frame buffer 7.

For example, if the image command Sl is a command such as "draw a red line from point P1 to point P2",
A red color code preset in the color palette IO is written to appropriate quantized pixels from the address corresponding to point P1 to the address corresponding to point P2 on the frame buffer 7.

Also, among the image commands S1, those related to display control are sent to the frame buffer 7 by the timing controller 9.
, the color palette 10, and the D/A converter 1l.

For example, in a command such as "Set the display position on the rCRT display between point P1 and point P2", the timing is measured from the display synchronization signal S6 given from the host computer 1, and the display position is set between point P1 and point P2. The state variable is changed to a value such that the frame buffer 7 is read for display only between the address corresponding to the power point P1 and the address corresponding to P2. In addition to this, the timing controller 9 also has state variables for readout that matches the resolution, readout that displays only appropriate colors, etc., and operates according to each set value based on these state variables.

In the case of this embodiment, the video signal combiner 5 combines analog signals into one combined video signal S,
Make it. The output impedance and voltage amplitude of the composite video signal Ss are calculated and adjusted from the maximum value that can be added with current. The CRT display 6 displays all the graphics modules 2 to 4 by the given composite video signal S.
Display the contents of.

In the above embodiment, an image display device using a CRT display 6 was explained, but even if a printer or the like is used instead of a CRT display, the interface of the D/A converter l1 of the graphic modules 2 to 4 can be used. The present invention can be applied in the same manner by simply making a change.

〔Effect of the invention〕

As described above, according to the present invention, a plurality of graphic modules each having an image processor, a frame buffer, etc. are provided in parallel and are operated simultaneously. As a result, even when the number of images to be displayed increases, images can be quickly displayed.

Furthermore, since it is easy to add graphic modules later, the functionality of the image display device can be easily enhanced as needed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an image display device of the present invention, and FIG. 2 is a block diagram showing an example of the structure of a conventional image display device. 1, 35: Host computer 2-4: Graphics module 5: Video signal synthesizer 6, 39: CRT display 7. 31-34: Frame buffer 8. 36: Image processor 9, 40: Timing controller 10. 37: Color palette 11, 38: D/A converter S1: Image command S2: Color signal Ss* S311 S31 S33: Video signal S4
: Master timing signal S, : Image display timing signal S6: Frame buffer control fi number

Claims (1)

[Claims] 1. A frame buffer, an image processor that generates an image in the frame buffer based on an image command, and a digital signal converter that converts a digital signal read from the frame buffer into an analog video signal. a host computer that outputs image commands in common to the plurality of graphic modules; and a video signal synthesizer that synthesizes the plurality of video signals output by the plurality of graphic modules. An image display device comprising: and a CRT display that displays a composite video signal output from the video signal synthesizer.