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JPH03152638A - Log data collection system for information processor - Google Patents

Log data collection system for information processor

Info

Publication number
JPH03152638A
JPH03152638A JP1292769A JP29276989A JPH03152638A JP H03152638 A JPH03152638 A JP H03152638A JP 1292769 A JP1292769 A JP 1292769A JP 29276989 A JP29276989 A JP 29276989A JP H03152638 A JPH03152638 A JP H03152638A
Authority
JP
Japan
Prior art keywords
processor
log data
circuit
failure
data collection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1292769A
Other languages
Japanese (ja)
Inventor
Hiroaki Nakada
浩章 中田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Ibaraki Ltd
Original Assignee
NEC Ibaraki Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Ibaraki Ltd filed Critical NEC Ibaraki Ltd
Priority to JP1292769A priority Critical patent/JPH03152638A/en
Publication of JPH03152638A publication Critical patent/JPH03152638A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To inhibit a faulty processor to have an access to a system bus at collection of the log data and to make another processor carry on a due operation by separating the faulty processor from the system bus when any processors have some faults. CONSTITUTION:When a certain processor 2-i has a fault, this processor 2-i informs a bus switch circuit 3-i of occurrence of the fault. The circuit 3-i cut the connection between the processor 2-i and a system bus 5 and informs a log data store circuit 4 of the fault of the processor 2-i via a connection line 6-i. Then the circuit 4 informs a diagnostic processor 1 of the fault via a connection line 7. The circuit 3-i receives the data from the faulty processor 2-i and sends the log data to the circuit 4 via the line 6-i. Then the circuit 4 reports the end of collection of the log data to the processor 1 via the line 7.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は情報処理装置のログデータ採取方式に関し、特
にプロセッサの何れかに何らかの障害が発生した場合に
、障害が発生したプロセッサがらのログデータを採取す
る情報処理装置のログデータ採取方式に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a log data collection method for an information processing device, and in particular, when a failure occurs in any of the processors, log data from the failed processor is collected. This invention relates to a log data collection method for an information processing device that collects log data.

〔従来の技術〕[Conventional technology]

従来の情報処理装置のログデータ採取方式は、プロセッ
サの何れかに何らがの障害が発生した場合に、障害が発
生したプロセッサがシステムバス上にログデータを送出
して、メモリにログデータを格納した後に、診断プロセ
ッサがそのログデータを採取する方式となっていた。
In the conventional log data collection method for information processing equipment, when a failure occurs in one of the processors, the failed processor sends log data onto the system bus and stores the log data in memory. After that, the diagnostic processor collects the log data.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の情報処理装置のログデータ採取方式は、
プロセッサの何れかに何らがの障害が発生した場合に、
障害が発生したプロセッサがシステムバス上にログデー
タを送出して、メモリにログデータを格納した後に、診
断プロセッサがログデータを採取する方式となっている
ので、障害が発生したプロセッサがシステムバスをアク
セスするために、ログデータをメモリに書き込む動作を
他のプロセッサの動作に影響を与えないで正しく行える
かどうかわからないという欠点を有している。
The log data collection method of the conventional information processing device described above is
In the event of a failure of any of the processors,
The diagnostic processor collects log data after the faulty processor sends log data onto the system bus and stores the log data in memory. The drawback is that it is not known whether the operation of writing log data into memory for access can be performed correctly without affecting the operations of other processors.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の情報処理装置のログデータ採取方式は、診断プ
ロセッサと複数台のプロセッサとを持つ情報処理装置の
ログデータ採取方式において、前記プロセッサの何れか
に何らかの障害が発生した場合に、障害が発生した前記
プロセッサからの障害発生通知を受けて、障害が発生し
た前記プロセッサに対するシステムバスの接続を切り離
すバス切り換え回路と、障害が発生した前記プロセッサ
からのログデータを格納するログデータ格納回路とを有
して構成されている。
In the log data collection method for an information processing device according to the present invention, in the log data collection method for an information processing device having a diagnostic processor and a plurality of processors, if a failure occurs in any of the processors, a failure occurs. a bus switching circuit that disconnects a system bus from the failed processor upon receiving a failure occurrence notification from the failed processor; and a log data storage circuit that stores log data from the failed processor. It is configured as follows.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の情報処理装置のログデータ採取回路の
一実施例を示すブロック図である。
FIG. 1 is a block diagram showing an embodiment of a log data collection circuit of an information processing apparatus according to the present invention.

第1図の情報処理装置は、1台の診断プロセッサ1と、
N台のプロセッサ2−1.・・・2−1.・・・2−N
と、バス切り換え回路3−1.・・・3−1゜・・・3
−Nと、ログデータ格納回路4と、システムバス5とに
より構成されている。
The information processing device in FIG. 1 includes one diagnostic processor 1,
N processors 2-1. ...2-1. ...2-N
and bus switching circuit 3-1. ...3-1゜...3
-N, a log data storage circuit 4, and a system bus 5.

何れかのプロセッサ2−iに何らがの障害が発生した場
合に、プロセッサ2−iは、バス切り換え回路3−iに
障害が発生したことを通知する。
If any fault occurs in any of the processors 2-i, the processor 2-i notifies the bus switching circuit 3-i that the fault has occurred.

プロセッサ2−iから障害通知を受けたバス切り換え回
路3−iは、障害が発生したプロセッサ2−1とシステ
ムバス5との接続を切り離し、接続線6−iを通じて、
ログデータ格納回路4ヘプロセツサ2−iの障害発生通
知を送る。プロセッサ2−iの障害発生通知を受けたロ
グデータ格納回路4は、診断プロセッサ1に対して、接
続線7を通じて障害発生通知を行う、プロセッサ2−i
の障害発生通知を行ったバス切り換え回路3−iは、障
害が発生したプロセッサ2−iからのログデータを引き
取り、接続線6−iを通じてログデータ格納回路4ヘロ
グデータを送出する。バス切り換え回路3−iからログ
データを受信したログデータ格納回路4は、障害が発生
したプロセッサ2−iからのログデータを格納する。障
害が発生したプロセッサ2−iからのログデータの格納
が終了した場合に、ログデータ格納回路4は、診断プロ
セッサ1に対して、接続線7を通じてログデータ採取の
終了を報告し、ログデータの採取を終了する。
The bus switching circuit 3-i, which has received the fault notification from the processor 2-i, disconnects the faulty processor 2-1 from the system bus 5, and connects the faulty processor 2-1 to the system bus 5 through the connection line 6-i.
A notification of the occurrence of a failure in the processor 2-i is sent to the log data storage circuit 4. The log data storage circuit 4 that has received the failure occurrence notification of the processor 2-i notifies the diagnostic processor 1 of the failure occurrence through the connection line 7.
The bus switching circuit 3-i that has notified the processor 2-i of the failure takes over the log data from the processor 2-i where the failure has occurred, and sends the log data to the log data storage circuit 4 through the connection line 6-i. The log data storage circuit 4 that has received the log data from the bus switching circuit 3-i stores the log data from the processor 2-i in which the failure has occurred. When the storage of log data from the failed processor 2-i is completed, the log data storage circuit 4 reports the completion of log data collection to the diagnostic processor 1 through the connection line 7, and stores the log data. Finish collecting.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明の情報処理装置のログデー
タ採取方式は、プロセッサの何れかに何らかの障害が発
生した時に、障害が発生したプロセッサとシステムバス
との接続を切り離すことにより、障害が発生したプロセ
ッサのログデータの採取時に、障害が発生したプロセッ
サがシステムバスへのアクセスを行わないので、他のプ
ロセッサの動作が安心して継続できるという効果を有し
ている。
As explained above, in the log data collection method of the information processing device of the present invention, when a fault occurs in any of the processors, the connection between the faulty processor and the system bus is disconnected. When collecting log data of a faulty processor, the faulty processor does not access the system bus, which has the effect that other processors can continue operating with peace of mind.

取方式の一実施例を示すブロック図である。FIG. 2 is a block diagram showing an example of a method of taking the data.

1・・・診断プロセッサ、2−1.〜2−1.〜2−N
・・・プロセッサ、3−1.〜3−1.〜3−N・・・
バス切り換え回路、4・・・ログデータ格納回路、5・
・・システムバス、6−1.〜6−i、6−N、7・・
・接続線。
1... Diagnostic processor, 2-1. ~2-1. ~2-N
...Processor, 3-1. ~3-1. ~3-N...
Bus switching circuit, 4... Log data storage circuit, 5.
...System bus, 6-1. ~6-i, 6-N, 7...
・Connection line.

Claims (1)

【特許請求の範囲】[Claims] 診断プロセッサと複数台のプロセッサとを持つ情報処理
装置のログデータ採取方式において、前記プロセッサの
何れかに何らかの障害が発生した場合に、障害が発生し
た前記プロセッサからの障害発生通知を受けて、障害が
発生した前記プロセッサに対するシステムバスの接続を
切り離すバス切り換え回路と、障害が発生した前記プロ
セッサからのログデータを格納するログデータ格納回路
とを有することを特徴とする情報処理装置のログデータ
採取方式。
In a log data collection method for an information processing device having a diagnostic processor and a plurality of processors, when a failure occurs in any of the processors, a failure notification is received from the processor in which the failure has occurred, and the failure is detected. A log data collection method for an information processing device, comprising: a bus switching circuit that disconnects a system bus from the processor in which a failure has occurred; and a log data storage circuit that stores log data from the processor in which a failure has occurred. .
JP1292769A 1989-11-09 1989-11-09 Log data collection system for information processor Pending JPH03152638A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1292769A JPH03152638A (en) 1989-11-09 1989-11-09 Log data collection system for information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1292769A JPH03152638A (en) 1989-11-09 1989-11-09 Log data collection system for information processor

Publications (1)

Publication Number Publication Date
JPH03152638A true JPH03152638A (en) 1991-06-28

Family

ID=17786104

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1292769A Pending JPH03152638A (en) 1989-11-09 1989-11-09 Log data collection system for information processor

Country Status (1)

Country Link
JP (1) JPH03152638A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05165657A (en) * 1991-12-16 1993-07-02 Matsushita Electron Corp Semiconductor integrated circuit
US6782492B1 (en) 1998-05-11 2004-08-24 Nec Corporation Memory error recovery method in a cluster computer and a cluster computer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05165657A (en) * 1991-12-16 1993-07-02 Matsushita Electron Corp Semiconductor integrated circuit
US6782492B1 (en) 1998-05-11 2004-08-24 Nec Corporation Memory error recovery method in a cluster computer and a cluster computer

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