JPH03159174A - Liquid crystal display device - Google Patents
Liquid crystal display deviceInfo
- Publication number
- JPH03159174A JPH03159174A JP1298327A JP29832789A JPH03159174A JP H03159174 A JPH03159174 A JP H03159174A JP 1298327 A JP1298327 A JP 1298327A JP 29832789 A JP29832789 A JP 29832789A JP H03159174 A JPH03159174 A JP H03159174A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- insulating film
- groove
- gate
- liquid crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 15
- 239000011521 glass Substances 0.000 claims abstract description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 8
- 239000004020 conductor Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 2
- 238000000206 photolithography Methods 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 24
- 239000011651 chromium Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は、絶縁ゲート型薄膜トランジスタ（以下ＴＰＴ
という）を用いたアクティブマトリクス型の液晶表示装
置に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Industrial application field The present invention relates to an insulated gate thin film transistor
The present invention relates to an active matrix type liquid crystal display device using an active matrix type liquid crystal display device.
（ロ） １；１：米の技術
近年、ＴＰＴを用いた高密度のＴＶ用液晶表示装置が開
発され、表示画面の大型化と共に画素数の増大が図られ
ている。(B) 1;1: American technology In recent years, high-density liquid crystal display devices for TVs using TPT have been developed, and efforts are being made to increase the size of the display screen and the number of pixels.
第２図は従来のＴＰＴを用いた液晶表示装置の断面図で
ある。図において、ガラス基板（１）上の全面にはシリ
コン酸化物の絶縁膜（２）が形成され、絶縁膜（２）上
にクロム等の導電体からなるゲートを極（３）及びゲー
ト電極（３）と連続する選択電極（図示せず）が一体に
形成される。更に、デート電極（３）を覆って全面にゲ
ート絶縁膜（４）が形成され、この上にアモルファスシ
リコン（５）、保護絶縁膜（６）、及び、Ｎ＋型不純物
がドープされたアモルファスシリコンからなるドレイン
（７）及びソース（８）が設けられ、更に、ドレイン（
７）に接続されたアルミニウムの表示電圧供給線（９）
とソース（８）を画素ＴＬ極（１０）に接続するアルミ
ニウムの接続電極（１１）が形成される。FIG. 2 is a sectional view of a conventional liquid crystal display device using TPT. In the figure, an insulating film (2) of silicon oxide is formed on the entire surface of a glass substrate (1), and a gate made of a conductive material such as chromium is formed on the insulating film (2) with a pole (3) and a gate electrode ( 3) and a continuous selection electrode (not shown) are integrally formed. Further, a gate insulating film (4) is formed on the entire surface covering the date electrode (3), and on this, amorphous silicon (5), a protective insulating film (6), and a gate insulating film (4) made of amorphous silicon doped with N+ type impurities are formed. A drain (7) and a source (8) are provided, and a drain (7) and a source (8) are provided.
7) Aluminum display voltage supply line (9) connected to
An aluminum connection electrode (11) is formed to connect the source (8) and the pixel TL pole (10).
このように、Ｔ Ｐ Ｔの設けられたガラス基板（１）
上にポリイミド配向膜の塗布、ラビングによる配向処理
、ガラス基板（１）の周辺のシール及び液晶の注入によ
って液晶表示装置が完成する。In this way, the glass substrate (1) provided with TPT
A liquid crystal display device is completed by applying a polyimide alignment film thereon, alignment treatment by rubbing, sealing around the glass substrate (1), and injecting liquid crystal.
第２図の液晶表示装置において、選択電極に選択電圧を
印加するとＴＰＴがオンして表示電圧供給線（９）に印
加された表示電圧が画業電極（１０）に充電され、表示
がなされる。In the liquid crystal display device shown in FIG. 2, when a selection voltage is applied to the selection electrode, the TPT is turned on, and the display voltage applied to the display voltage supply line (9) is charged to the image electrode (10), thereby producing a display.
このような液晶表示装置は、特開平１−１３６１．２３
号公報に記載されている。Such a liquid crystal display device is disclosed in Japanese Patent Application Laid-Open No. 1-1361.23.
It is stated in the No.
（ハ）発明が解決しようとする課題
第２図に示された液晶表示装置においては、絶縁膜（２
）上にゲート電極（３）、ゲート絶縁膜（４）、アモル
ファスシリコン（５）、ドレイン（７）及びソース（８
）、表示電圧供給線（９）及び接続電極（１１）が積層
されるため、段差部のステンブカパレッジが悪化し、各
層間のショートが発生する危惧がある。(c) Problems to be Solved by the Invention In the liquid crystal display device shown in FIG.
) on which a gate electrode (3), gate insulating film (4), amorphous silicon (5), drain (7) and source (8) are formed.
), the display voltage supply line (9), and the connection electrode (11) are stacked, so there is a risk that the stent coverage at the stepped portion will deteriorate and a short circuit will occur between each layer.
そこで、ゲート電極（３）及び選択電極にタンタルを使
用し、その表面に陽極酸化によって緻密な絶縁膜を形成
してゲート電極（３）とドレイン（７）及びソース（８
）のショートを防止する技術が提案されている。しかし
ながら、大画面高密度になると選択電極の幅が狭くなる
と共に配線長が長くなるために、その電気抵抗が大きく
なり、特に、ゲート電極（３）及び選択電極を電気抵抗
の大きいタンタルで形成した場合には、抵抗の増大は顕
著になる。Therefore, tantalum is used for the gate electrode (3) and the selection electrode, and a dense insulating film is formed on the surface by anodic oxidation.
) has been proposed to prevent short circuits. However, as the screen becomes larger and denser, the width of the selection electrode becomes narrower and the length of the wiring becomes longer, which increases the electrical resistance. In some cases, the increase in resistance becomes significant.
また、第２図の液晶表示装置のＴＰＴは、その高さが高
くなり、ガラス基板をシールする際にその間隙を一定に
保持するためにいれるピラーがＴＦ Ｔ ｌに存在する
と間隙がバラついてしまう欠点があった。In addition, the height of the TPT of the liquid crystal display device shown in Figure 2 is high, and the gap will vary if there is a pillar in the TF T l that is inserted to maintain a constant gap when sealing the glass substrate. There were drawbacks.
（ニ）課題を解決するための手段
本発明は、上述した点に鑑みて創作されたものであり、
ガラス基板上に設けられた絶縁膜と、ゲート電極及び該
ゲート電極に連続する選択電極が形成される部分の前記
絶縁膜に形成された溝と、該溝に埋め込まれ前記ゲート
電極及び選択電極を形成する導電体と、前記ゲート電極
上に形成されたゲート絶縁膜と、該ゲート絶縁膜上に形
成されたアモルファスシリコン層とを具備することによ
り、選択電極の配線抵抗を低下させ、ＴＰＴの高さを低
く形成することのできる液晶表示装置を提供するもので
ある。(d) Means for solving the problems The present invention was created in view of the above points,
An insulating film provided on a glass substrate, a groove formed in the insulating film in a portion where a gate electrode and a selection electrode continuous to the gate electrode are formed, and a groove embedded in the groove to form the gate electrode and selection electrode. By providing a conductor to be formed, a gate insulating film formed on the gate electrode, and an amorphous silicon layer formed on the gate insulating film, the wiring resistance of the selection electrode can be reduced and the TPT can be increased. The present invention provides a liquid crystal display device that can be formed with a low height.
（ホ）作用
上述の手段によれば、ガラス基板上の絶縁膜に設けられ
た溝は、選択電極及びゲート＠Ｉｉｉを埋め込み、選択
を極の厚さを厚く形成することを可能にし、その結果、
配線抵抗を減少するよう作用し、更に、ゲート電極の厚
さが厚くなっても、ＴＰＴの高さを低くするように作用
する。(E) Effect According to the above-mentioned means, the groove provided in the insulating film on the glass substrate embeds the selection electrode and the gate @Iiii, making it possible to form the selection electrode thickly, and as a result, ,
It acts to reduce the wiring resistance, and further acts to reduce the height of the TPT even if the gate electrode becomes thicker.
（へン実施例
第１図（ａ）（ｂ）は、本発明の実施例を示す断面図で
あり、第１図（ａ）は選択電極部のｌｌＩｒ面図、第１
図（ｂ）はＴＦＴ部の断面図である。(Embodiment FIGS. 1(a) and 1(b) are cross-sectional views showing an embodiment of the present invention, and FIG. 1(a) is an llIr side view of the selection electrode section, and
Figure (b) is a cross-sectional view of the TFT section.
第１図（ａ）（ｂ）において、ガラス基板（１２）の−
主面上にＣＶＤ法等によって３０００人程度０厚さにＳ
ｉｎ、の絶縁膜（１３）が設けられ、更に、この絶縁膜
（１３）にはフォトリソによって形成された溝（１４）
が設けられる。この溝（１４）内には選択電極（１５）
及びゲート電極（１６）が埋め込まれ設けられる。こで
、選択電極（１５）及びゲート電極（１６）は、溝（１
４）を形成したフォトレジストを残した状態で、Ｃｒを
スッパタリング法によって絶縁膜（１３）と略同じ厚さ
に付着し、７オトレジストを除去するり７トオフ法によ
り形成さ・れる。従って、選択電極（１５）とゲート電
極（１６）の上面は、絶縁膜（１３）の表面と略一致し
、平坦面を形成している。また、選択電極（１５）は並
行に複数配置され、各選択型［ｉ （１５）から突出し
てゲート電ｐｉ（１６）が一体化されている。In FIGS. 1(a) and 1(b), - of the glass substrate (12)
S on the main surface to about 3,000 thickness by CVD method etc.
An insulating film (13) is provided, and a groove (14) formed by photolithography is further provided in this insulating film (13).
will be provided. In this groove (14) there is a selection electrode (15).
and a gate electrode (16) are buried and provided. Here, the selection electrode (15) and the gate electrode (16) are arranged in the groove (1
With the photoresist formed in 4) remaining, Cr is deposited to approximately the same thickness as the insulating film (13) by sputtering, and the photoresist 7 is removed or formed by a 7-off method. Therefore, the upper surfaces of the selection electrode (15) and the gate electrode (16) substantially coincide with the surface of the insulating film (13), forming a flat surface. Further, a plurality of selection electrodes (15) are arranged in parallel, and a gate electrode pi (16) is integrated with each selection electrode [i (15)] protruding from the selection electrodes (15).
そして、第１図（ｂ）に示すごとく、ゲート電極（１６
）Ｉニは、３０００人の厚さのシリコン窒化ｍｔＳｉＮ
ｘ）からなるゲート絶縁膜（１７）と、チャンネル領域
となる２０００人の厚さのアモルファスシリコン（ａ−
５ｉ）層（１８）と、Ｎ９不純物のドープされた５００
人の厚さのアモルファスシリコン（Ｎ”ａ−３ｉ）から
なるドレイン（２ｏ）及びソース（２１）が設けられる
。これらゲート絶縁膜（１７）と、アモルファスシリコ
ン（ａ−５ｉ）層（１８）と、Ｎ４ａ−８ｉは、プラズ
マＣＶＤ法によって連続して積層され、ゲート電極（１
６）上のＴＰＴが形成される部分のみを残しその池をエ
ツチング除去することによって形成される。Then, as shown in FIG. 1(b), the gate electrode (16
)I 3000 mtSiN thick silicon nitride
a gate insulating film (17) consisting of a
5i) layer (18) with N9 impurity doped 500
A drain (2o) and source (21) made of amorphous silicon (N"a-3i) with a human thickness are provided. These gate insulating films (17) and amorphous silicon (a-5i) layers (18) , N4a-8i are successively laminated by plasma CVD method, and the gate electrode (1
6) It is formed by etching away the pond leaving only the part where the upper TPT will be formed.
更に、選択電極（１５）と直交してＡ１で形成された表
示電圧供給線（２２）がドレイン（２０）に重畳して設
けられ、ソース（２１）と重畳してＡＩで形成された接
続電極（２３）が設けられる。ドレイン（２０）とソー
ス（２１）は、表示電圧供給線（２２）と接続電極（２
３）をマスクとしてＮ”ａ −Ｓ ｉをエツチング除去
することによって形成される。ＩＴＯからなる画素電極
（２４）はその一部が接続電極（２３）に重畳されて設
けられ、ＴＰＴのソース（２１）に接続される。更に、
シリコン窒化膜のパッシベーション膜（２５）がＴ Ｐ
Ｔを覆って設けられる。Further, a display voltage supply line (22) made of A1 is provided to be perpendicular to the selection electrode (15) and overlapped with the drain (20), and a connection electrode made of AI is provided to overlap with the source (21). (23) is provided. The drain (20) and source (21) are connected to the display voltage supply line (22) and the connection electrode (2
The pixel electrode (24) made of ITO is formed by etching away the N''a-S i using 3) as a mask. 21).Furthermore,
The silicon nitride passivation film (25) is T P
It is provided to cover the T.
第１図（ａ ）（ｂ ）の構造によると、選択電極（１
５）は、比較的厚く形成されるため、その線幅が狭くな
−）ても配線抵抗は十分低くなる。また、選択電極（１
５）と一体向の構成されたゲート電極（１６）と絶縁膜
（１３）の段差がなくなるために、ゲート電極（１６）
とドレイン（２０）及びソース（２１）とのショートが
なくなり、更に、表示電圧供給線（２２）や接続電極（
２３）の断線が防止できる。According to the structure shown in FIGS. 1(a) and 1(b), the selection electrode (1
5) is formed relatively thick, so even if its line width is narrow -), the wiring resistance is sufficiently low. In addition, the selection electrode (1
5) Since there is no difference in level between the gate electrode (16) and the insulating film (13), which are configured in one direction, the gate electrode (16)
This eliminates short-circuiting between the drain (20) and source (21), and furthermore, the display voltage supply line (22) and the connection electrode (
23) can be prevented from breaking.
尚、第１図（ａ ）（ｂ ）の実施例では、選択電極（
１５）及びゲート４極（１６）は、Ｃｒで形成したが、
Ｔａを使用しその表面を陽極酸化した構造にしてもよい
。In the embodiment shown in FIGS. 1(a) and 1(b), the selection electrode (
15) and the gate quadrupole (16) were made of Cr, but
It may also have a structure in which Ta is used and the surface is anodized.
（ト）発明の効果
本発明によれば、選択電極の配線抵抗を小さくできるの
で、動作速度が早く、高密度の液晶表示装置が実現でき
る。また、ＴＰＴ全体の高さを低くできるので、ピラー
による間隙の制胛が正確に行え、表示品質の向上となる
利点がある。(G) Effects of the Invention According to the present invention, since the wiring resistance of the selection electrode can be reduced, a liquid crystal display device with high operating speed and high density can be realized. Furthermore, since the height of the entire TPT can be reduced, the gap can be accurately controlled by the pillars, which has the advantage of improving display quality.
第１図（ａ ）（ｂ ）は、本発明の実施例を示す断面
図、第２図は従来例を示す断面図である。
（１２）・・・ガラス基板、（１３）・・・絶縁膜、（
１４）・・・溝、（１５）・・・選択電極、（１６）・
・・ゲート電極、（１７）・・・ゲート絶縁膜、（１８
）・・・ａ−５ｉ層、（２０）・・・ドレイン、（２１
）・・・ソース、（２２）・・・表示電圧供給線、（２
３）・・・接続電極、（２４）・・・画素電極、（２５
）・；・パッシベーション膜。
第１図
出頭人 三洋電機株式会社FIGS. 1(a) and 1(b) are sectional views showing an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional example. (12)...Glass substrate, (13)...Insulating film, (
14)...Groove, (15)...Selection electrode, (16)...
...Gate electrode, (17)...Gate insulating film, (18
)...a-5i layer, (20)...drain, (21
)...Source, (22)...Display voltage supply line, (2
3)... Connection electrode, (24)... Pixel electrode, (25
)・;・Passivation film. Figure 1 Appearance Sanyo Electric Co., Ltd.
Claims (2)
及び該ゲート電極に連続する選択電極が形成される部分
の前記絶縁膜に形成された溝と、 該溝に埋め込まれ前記ゲート電極及び選択電極を形成す
る導電体と、 前記ゲート電極上に形成されたゲート絶縁膜該ゲート絶
縁膜上に形成されたアモルファスシリコン層と、 を具備した液晶表示装置。(1) An insulating film provided on a glass substrate, a groove formed in the insulating film in a portion where a gate electrode and a selection electrode continuous to the gate electrode are formed, and the gate electrode and the groove embedded in the groove. A liquid crystal display device comprising: a conductor forming a selection electrode; a gate insulating film formed on the gate electrode; and an amorphous silicon layer formed on the gate insulating film.
じ厚さであることを特徴とする請求項第１項記載の液晶
表示装置。(2) The liquid crystal display device according to claim 1, wherein the conductor embedded in the groove has approximately the same thickness as the insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1298327A JPH03159174A (en) | 1989-11-16 | 1989-11-16 | Liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1298327A JPH03159174A (en) | 1989-11-16 | 1989-11-16 | Liquid crystal display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03159174A true JPH03159174A (en) | 1991-07-09 |
Family
ID=17858225
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1298327A Pending JPH03159174A (en) | 1989-11-16 | 1989-11-16 | Liquid crystal display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03159174A (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100305877B1 (en) * | 1993-08-19 | 2001-12-15 | 김영환 | Method for fabricating tft |
| KR100358162B1 (en) * | 1995-02-24 | 2003-01-24 | 주식회사 하이닉스반도체 | Method for manufacturing thin film transistor |
| WO2005055309A1 (en) * | 2003-12-02 | 2005-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor, display device and liquid crystal display device and method for manufacturing the same |
| WO2005059990A1 (en) * | 2003-12-02 | 2005-06-30 | Semiconductor Energy Laboratory Co., Ltd. | Electronic device and semiconductor device and method for manufacturing the same |
| JP2005210081A (en) * | 2003-12-02 | 2005-08-04 | Semiconductor Energy Lab Co Ltd | Electronic appliance, and semiconductor apparatus and formation method therefor |
| JP2005210083A (en) * | 2003-12-02 | 2005-08-04 | Semiconductor Energy Lab Co Ltd | Thin film transistor, display, liquid crystal display, and method of manufacturing them |
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1989
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