JPH03141666A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH03141666A JPH03141666A JP27915789A JP27915789A JPH03141666A JP H03141666 A JPH03141666 A JP H03141666A JP 27915789 A JP27915789 A JP 27915789A JP 27915789 A JP27915789 A JP 27915789A JP H03141666 A JPH03141666 A JP H03141666A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- substrate
- insulating substrate
- holes
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 239000004020 conductor Substances 0.000 claims description 29
- 230000002093 peripheral effect Effects 0.000 claims description 11
- 239000011347 resin Substances 0.000 claims description 7
- 229920005989 resin Polymers 0.000 claims description 7
- 238000007789 sealing Methods 0.000 claims description 6
- 238000012856 packing Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要］
絶縁基板に形成された集積回路と外部接続用リード端子
とをワイヤで接続した混成集積回路の構成に関し、
回路素子の実装密度を高めるため、絶縁基板の表面と裏
面との双方に集積回路を形成可能ならしめることを目的
とし、
表面に第１の集積回路を形成し裏面に第２の集積回路が
形成される角形絶縁基板の周縁部には、その周縁端に平
行し該基板を貫通する多数のスルーホールが形成され、
該基板の表面の周縁部には少なく七も該スルーホールの
それぞれに対応する多数の導体パッドが形成され、
該基板の外側には該導体パッドのそれぞれに対応する多
数のリード端子が配設され、
該第２の集積回路が所要の該スルーホールを介してその
スルーホールに対応する導体パッドに接続され、
該第１．第２の集積回路の少なくとも一方に接続された
該導体パッドとその導体パッドに対向するリード端子と
がワイヤにて接続されたのち、少なくとも該絶縁基板お
よび該接続ワイヤを封止する封止樹脂が形成されたこと
を特徴とし構成する。[Detailed Description of the Invention] [Summary] Regarding the configuration of a hybrid integrated circuit in which an integrated circuit formed on an insulating substrate and lead terminals for external connection are connected with wires, in order to increase the mounting density of circuit elements, the surface of the insulating substrate is The periphery of the rectangular insulating substrate, on which the first integrated circuit is formed on the front surface and the second integrated circuit is formed on the back surface, is A large number of through holes are formed parallel to the edges and pass through the substrate, and a large number of conductor pads are formed at the peripheral edge of the surface of the substrate, corresponding to at least seven through holes, and on the outside of the substrate. is provided with a large number of lead terminals corresponding to each of the conductive pads, the second integrated circuit is connected to the conductive pad corresponding to the through hole through the required through hole, and the first integrated circuit is connected to the conductive pad corresponding to the through hole. After the conductive pad connected to at least one side of the second integrated circuit and the lead terminal facing the conductive pad are connected by a wire, a sealing resin is applied to seal at least the insulating substrate and the connecting wire. It is characterized by being formed.
〔産業上の利用分野］
本発明は、絶縁基板に形成された集積回路と外部接続用
リード端子とがワイヤで接続された混成集積回路、特に
絶縁基板の表裏に回路形成させたことで高密度実装とし
た混成集積回路の構成に関する。[Industrial Application Field] The present invention relates to a hybrid integrated circuit in which an integrated circuit formed on an insulating substrate and lead terminals for external connection are connected by wires, and in particular, a hybrid integrated circuit formed on the front and back sides of the insulating substrate. This paper relates to the configuration of a hybrid integrated circuit as an implementation.
絶縁基板に集積回路を形成し、その集積回路と外部接続
用リード端子とがワイヤで接続されたのち、モールドに
よる封止樹脂の外装が形成された従来の混成集積回路は
、絶縁基板の表面と裏面との双方でワイヤ接続させるこ
とが困難であるとの理由から、表面のみに回路形成され
たものであった。Conventional hybrid integrated circuits, in which an integrated circuit is formed on an insulating substrate, the integrated circuit and lead terminals for external connection are connected with wires, and then a sealing resin sheath is formed by molding are formed on the surface of the insulating substrate. Circuits were formed only on the front surface because it was difficult to make wire connections on both sides.
（発明が解決しようとする課８）
以上説明したように、ワイヤを使用して集積回路とリー
ド端子とを接続した従来の混成集積回路は、絶縁基板の
裏面が利用されない構成であり、従来と同じ回路素子を
使用する限り回路内の実装密度が高められないという問
題点があった。(Issue 8 to be solved by the invention) As explained above, the conventional hybrid integrated circuit in which the integrated circuit and the lead terminal are connected using wires has a configuration in which the back side of the insulating substrate is not used. There is a problem in that as long as the same circuit elements are used, the packaging density within the circuit cannot be increased.
本発明の目的は、集積回路とリード端子とがワイヤによ
って接続される混成集積回路において、絶縁基板の裏面
に集積回路が形成できるようにすることである。An object of the present invention is to enable the integrated circuit to be formed on the back surface of an insulating substrate in a hybrid integrated circuit in which the integrated circuit and lead terminals are connected by wires.
〔課題を解決するための手段］
第１図は本発明による混成集積回路の基本構成の概略を
示す側断面図（イ）、その混成集積回路に使用した絶縁
基板とリード端子との接続関係の概略を示す平面図（０
）である。[Means for Solving the Problems] Figure 1 is a side sectional view (A) showing the outline of the basic configuration of a hybrid integrated circuit according to the present invention, and a diagram showing the connection relationship between the insulating substrate and lead terminals used in the hybrid integrated circuit. Plan view showing the outline (0
).
第１図において、本発明による混成集積回路１は、表面
には回路素子３，４等を搭載しそれらの接続パターンを
含む第１の集積回路を形成し、裏面には回路素子５，６
等を搭載しそれらの接続パターンを含む第２の集積回路
が形成される角形絶縁基板２の周縁部には、その周縁端
に平行し絶縁基板２を貫通する多数のスルーホール７が
形成され、絶縁基板２の表面の周縁部には少なくともス
ルーホール７のそれぞれに対応する多数の導体パッド８
が形成される。In FIG. 1, a hybrid integrated circuit 1 according to the present invention has circuit elements 3, 4, etc. mounted on the front side to form a first integrated circuit including connection patterns thereof, and circuit elements 5, 6 on the back side.
A large number of through holes 7 are formed at the peripheral edge of the rectangular insulating substrate 2 on which a second integrated circuit including connection patterns and the like is formed, parallel to the peripheral edge and penetrating the insulating substrate 2. A large number of conductive pads 8 are provided on the peripheral edge of the surface of the insulating substrate 2, corresponding to at least each of the through holes 7.
is formed.
絶縁基板２の外側には各導体パッド８に対応する多数の
リード端子９が配設される。A large number of lead terminals 9 corresponding to each conductor pad 8 are arranged on the outside of the insulating substrate 2 .
絶縁基板２の裏面に形成された第２の集積回路と、絶縁
基板２の表面に形成された導体パッド８とは所要のスル
ーホール（第１図（ロ）の塗り潰しスルーホール）７を
介して接続される。The second integrated circuit formed on the back surface of the insulating substrate 2 and the conductor pad 8 formed on the surface of the insulating substrate 2 are connected through the required through holes (filled through holes in FIG. 1 (b)) 7. Connected.
第１の集積回路において第２の集積回路に接続されない
接続パターンは、第２の集積回路が接続されないスルー
ホール７に連通する導体パッド８に接続する。A connection pattern in the first integrated circuit that is not connected to the second integrated circuit is connected to a conductive pad 8 that communicates with a through hole 7 to which the second integrated circuit is not connected.
そして、使用された導体パッド８とその導体バンド８に
対向するリード端子９とはワイヤ１０で接続され、しか
るのち絶縁基板２および接続ワイヤｌＯを封止する封止
樹脂１１を形成して完成する。Then, the used conductor pad 8 and the lead terminal 9 facing the conductor band 8 are connected with a wire 10, and then a sealing resin 11 is formed to seal the insulating substrate 2 and the connecting wire 10, thereby completing the process. .
上記手段によれば、絶縁基板の周縁部にスルーホールを
設け、該基板の周縁部表面には少な（とも該スルーホー
ルに対応する導体バンドを設け、該基板の表面には第１
の集積回路を形成し、該基板の裏面には第２の集積回路
を形成し、第１の集積回路は該導体パッドを介して外部
接続用リー１端子とワイヤにて接続し、第２の集積回路
は所要の該スルーホールとそのスルーホールが対応する
導体パッドを介して外部接続用リード端子とワイヤにて
接続する構成としたことによって、該基板の裏面に第２
の集積回路が形成可能となり、かつ、第１の集積回路と
第２の集積回路とを所要部で接続または相互独立に形成
可能となり、混成集積回路の高密度実装が実現される。According to the above means, a through hole is provided at the peripheral edge of the insulating substrate, a conductor band (corresponding to the through hole) is provided at the peripheral edge surface of the substrate, and a first conductor band is provided on the surface of the substrate.
A second integrated circuit is formed on the back surface of the substrate, the first integrated circuit is connected to the external connection lead 1 terminal by a wire through the conductor pad, and the second The integrated circuit has a structure in which the required through holes and the through holes are connected to external connection lead terminals by wires via the corresponding conductor pads, so that a second
integrated circuits can be formed, and the first integrated circuit and the second integrated circuit can be connected at required parts or formed independently of each other, and high-density packaging of hybrid integrated circuits can be realized.
［実施例］
以下に、図面を用いて本発明の実施例による混成集積回
路を説明する。[Embodiment] A hybrid integrated circuit according to an embodiment of the present invention will be described below with reference to the drawings.
第２図は本発明の一実施例による混成集積回路の要部を
示す平面図、第３図は本発明の他の実施例による混成集
積回路の要部を示す平面図である。FIG. 2 is a plan view showing a main part of a hybrid integrated circuit according to an embodiment of the present invention, and FIG. 3 is a plan view showing a main part of a hybrid integrated circuit according to another embodiment of the invention.
第１図と共通部分に同一符号を使用した第２図において
、混成集積回路１２の絶縁基板２は、表面にＩＣｌ３と
ダイオード１４と抵抗１５．１６等を搭載しそれらの接
続パターン１７を含む第１の集積回路を形成し、裏面に
は第１の集積回路と同様な第２の集積回路を形成する。In FIG. 2, in which the same reference numerals are used for parts common to those in FIG. 1 integrated circuit is formed, and a second integrated circuit similar to the first integrated circuit is formed on the back side.
セラミンクにてなる絶縁基板２の周縁部には、周縁端に
平行し絶縁基板２を貫通する多数のスルーホール７と、
各スルーホール７に対応する導体パッド８−、が形成さ
れると共に、絶縁基板２の周縁端面を絶縁基板２の厚さ
方向に除去した内面に導体層１８を被着した多数の凹部
１７に対応する導体パッド８−２が形成されるようにな
る。At the periphery of the insulating substrate 2 made of ceramic, there are a number of through holes 7 that run parallel to the periphery and pass through the insulating substrate 2.
Conductor pads 8 - corresponding to each through hole 7 are formed, and correspond to a large number of recesses 17 on which a conductor layer 18 is coated on the inner surface of the insulating substrate 2 by removing the peripheral end face in the thickness direction of the insulating substrate 2. A conductive pad 8-2 is now formed.
絶縁基板２の外側には各導体パッド８−１８に対応する
リード端子９が配設され、利用された導体パッド８−１
．８−２とそのパッド８−＋、 ８−ｄこ対応するリー
ド端子９とがワイヤＩＯにて接続されたのち、絶縁基板
２およびワイヤ１０を；Ｗう封止に１脂（１１）を形成
し、混成集積回路１２が完成する。Lead terminals 9 corresponding to each conductive pad 8-18 are arranged on the outside of the insulating substrate 2, and the used conductive pad 8-1
．． After 8-2 and its pads 8-+ and 8-d are connected to the corresponding lead terminals 9 using wires IO, a layer of resin (11) is formed on the insulating substrate 2 and the wires 10; Then, the hybrid integrated circuit 12 is completed.
利用されたスルーホール７は、第２の集積回路をパッド
８−８に接続するおよび、第１の集積回路と第２の集積
回路とを接続しさらに８−１に接続する。The utilized through holes 7 connect the second integrated circuit to pad 8-8, and connect the first and second integrated circuits to pad 8-1.
絶縁基板２０周縁端に設けられた凹部Ｉ７と導体層１８
は、リード端子９に相当する従来のり一ト喘子を半田接
続する従来技術による混成集積回路の構成を利用したも
のであり、混成集積回路１２においてその用途はスルー
ホール７と同一である。The recess I7 provided at the peripheral edge of the insulating substrate 20 and the conductor layer 18
This utilizes the configuration of a conventional hybrid integrated circuit in which a conventional glue plate corresponding to the lead terminal 9 is connected by soldering, and its use in the hybrid integrated circuit 12 is the same as that of the through hole 7.
このようにスルーホール７と導体層１８とをｐＨ用し、
第１の集積回路と第２の集積回路との接続を可能とした
混成集積回路１２の絶縁基板２は、導体層１８に替えて
スルーホール７を形成せしめた絶縁基板より、周縁部の
機械的強度に優れ集積回路形成領域を広（すると共に、
リード端子９の微細ピッチ配設を可能にする。In this way, the through hole 7 and the conductor layer 18 are used for pH control,
The insulating substrate 2 of the hybrid integrated circuit 12 that enables the connection between the first integrated circuit and the second integrated circuit has a mechanically It has excellent strength and expands the area for forming integrated circuits (as well as
This allows fine pitch arrangement of lead terminals 9.
なお第２図において、対応する導体バット８が連通する
導体層１８は第２の集積回路に接続されたもの、対応す
る導体パッド８−２が連通しない導体層１８は第２の集
積回路に接続されないもの、川塗りしたスルーホール７
は第１．第２の集積回路に接続されたもの、男塗りしな
いスルーホール７１よ第２の集積回路に接続されないも
のを示す。In FIG. 2, the conductor layer 18 with which the corresponding conductor pad 8 communicates is connected to the second integrated circuit, and the conductor layer 18 with which the corresponding conductor pad 8-2 does not communicate is connected to the second integrated circuit. What is not possible, river-painted through hole 7
is the first. What is connected to the second integrated circuit is shown, and what is not connected to the second integrated circuit, such as a through hole 71 that is not colored by men, is shown.
第１図と共通部分に同一符号を使用した第３図において
、混成集積回路２１の絶縁基板２は、表面にＩＣ２２と
ダイオード２３，２４．２５と抵抗２６等を搭赦しそれ
らの接続パターン２７を含む第１の集積回路を形成し、
裏面にニブ第１の集積回路と同様な第２の集積回路を形
成する。In FIG. 3, in which the same reference numerals are used for parts common to those in FIG. forming a first integrated circuit comprising;
A second integrated circuit similar to the first integrated circuit is formed on the back side of the nib.
絶縁基板２の周縁部に形成し利用された導体パッド８．
、．１１．とそのパット８−、．８−ｚに対応するリー
ド端子９とをワイヤ１０にて接続されたのら、絶縁基Ｆ
ｉ、２およびワイヤＩＯを覆う封止樹脂（１１）を形成
し、混成集積回路２１が完成する。Conductor pads 8 formed on the periphery of the insulating substrate 2.
,． 11. And that putt 8-,. After connecting the lead terminal 9 corresponding to 8-z with the wire 10, the insulating base F
A sealing resin (11) is formed to cover i, 2 and the wire IO, and the hybrid integrated circuit 21 is completed.
ＩＩＩ用されたスルーホール７は、第１の集積回路と第
２の集積回路との接続および、第２の集積回路をリード
端子９に接続する媒体となるパッド８に接続ためのもの
である。The through hole 7 used in III is for connecting the first integrated circuit to the second integrated circuit and to the pad 8 which is a medium for connecting the second integrated circuit to the lead terminal 9.
なお図中において、対応する導体パッド８ □が連通す
る導体層１８は第２の集積回路に接続されたもの、対応
する導体パッド８−２が連通しない導体層１８は第２の
集積回路に接続されないもの、黒塗りしたスルーホール
７は第２の集積回路に接続され第１の集積回路に接続さ
れないもの、川塗りしないスルーホール７は利用されな
いまたは第２の集積回路に接続され第１の集積回路に接
続さねｔ・ものであり、スルーホール７また二よ導体層
１１０て連通せずワイヤＩＯの接続されないパ、・１・
）３４．パッド８゜２は利用されなかっかことを示す。In the figure, the conductor layer 18 with which the corresponding conductor pad 8 □ communicates is connected to the second integrated circuit, and the conductor layer 18 with which the corresponding conductor pad 8-2 does not communicate is connected to the second integrated circuit. Through-holes 7 that are blacked out are connected to the second integrated circuit and not connected to the first integrated circuit, and through-holes 7 that are not blacked out are not used or are connected to the second integrated circuit and connected to the first integrated circuit. It is connected to the circuit, and the through hole 7 or the second conductor layer 110 does not communicate and the wire IO is not connected.
)34. Pad 8°2 indicates that it is not used.
上記手段によれば、絶縁基板に形成された集積回路と外
部接続用リード端子とをワイヤにて接続する混成集積回
路において、絶縁基板の裏面にはその表面に形成された
第１の集積回路に対し独立または所要部接続自在な構成
を提供し、高密度実装が実現された効果を有する。According to the above means, in a hybrid integrated circuit in which an integrated circuit formed on an insulating substrate and a lead terminal for external connection are connected by a wire, the back side of the insulating substrate has a first integrated circuit formed on the front side. On the other hand, it provides a configuration that can be independent or freely connected to required parts, and has the effect of realizing high-density packaging.
９はリード端子、 １０はワイヤ、 １１は封止樹脂、 １２．２１は混成集積回路、 を示す。9 is a lead terminal, 10 is a wire, 11 is a sealing resin; 12.21 is a hybrid integrated circuit, shows.
第１図は本発明による混成集積回路の基本構成図、
第２図は本発明の一実施例による混成集積回路の要部の
平面図、
第３図は本発明の他の実施例による混成集積回路の要部
の平面図、
である。
図中において、
２は絶縁基板、
７はスルーホール、
８、８．．８−２は導体パッド、
Ｉ２５晃成算項口路
（ロ）
本発明による浸滅系移て廖夕肩（険算戒図嶌 １ 図
親明の一大方七一によるシ毘戊鳥積回路の要部の平面９
夷 ２ 図FIG. 1 is a basic configuration diagram of a hybrid integrated circuit according to the present invention, FIG. 2 is a plan view of essential parts of a hybrid integrated circuit according to an embodiment of the present invention, and FIG. 3 is a diagram of a hybrid integrated circuit according to another embodiment of the present invention. This is a plan view of the main parts of the circuit. In the figure, 2 is an insulating substrate, 7 is a through hole, 8, 8. ．． 8-2 is a conductor pad. plane 9 of the main part of
Figure 2
Claims (1)
が形成される角形絶縁基板（２）の周縁部には、その周
縁端に平行し該基板（２）を貫通する多数のスルーホー
ル（７）が形成され、 該基板（２）の表面の周縁部には少なくとも該スルーホ
ール（７）のそれぞれに対応する多数の導体パッド（８
）が形成され、 該基板（２）の外側には該導体パッド（８）のそれぞれ
に対応する多数のリード端子（９）が配設され、該第２
の集積回路が所要の該スルーホール（７）を介してその
スルーホール（７）に対応する導体パッド（８）に接続
され、 該第１、第２の集積回路の少なくとも一方に接続された
該導体パッド（８）とその導体パッド（８）に対向する
リード端子（９）とがワイヤ（１０）にて接続されたの
ち、 少なくとも該絶縁基板（２）および該接続ワイヤ（１０
）を封止する封止樹脂（１１）が形成されたことを特徴
とする混成集積回路。[Claims] At the peripheral edge of the rectangular insulating substrate (2), on which a first integrated circuit is formed on the front surface and a second integrated circuit is formed on the back surface, there is a rectangular insulating substrate (2) parallel to the peripheral edge of the substrate (2). A large number of through holes (7) are formed passing through the substrate (2), and a large number of conductor pads (8) corresponding to at least each of the through holes (7) are formed at the peripheral edge of the surface of the substrate (2).
) is formed, and a large number of lead terminals (9) corresponding to each of the conductor pads (8) are arranged on the outside of the substrate (2), and
an integrated circuit connected to the conductor pad (8) corresponding to the through hole (7) through the required through hole (7), and an integrated circuit connected to at least one of the first and second integrated circuits. After the conductor pad (8) and the lead terminal (9) facing the conductor pad (8) are connected by the wire (10), at least the insulating substrate (2) and the connection wire (10) are connected.
) A hybrid integrated circuit characterized in that a sealing resin (11) is formed to seal the circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27915789A JPH03141666A (en) | 1989-10-26 | 1989-10-26 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27915789A JPH03141666A (en) | 1989-10-26 | 1989-10-26 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03141666A true JPH03141666A (en) | 1991-06-17 |
Family
ID=17607247
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27915789A Pending JPH03141666A (en) | 1989-10-26 | 1989-10-26 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03141666A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6040983A (en) * | 1997-04-16 | 2000-03-21 | Texas Instruments Incorporated | Vertical passive components for surface mount assembly |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63136657A (en) * | 1986-11-28 | 1988-06-08 | Toshiba Corp | Both-side mounting electronic circuit device |
| JPH01199497A (en) * | 1987-11-10 | 1989-08-10 | Ibiden Co Ltd | Electronic component mounting substrate |
-
1989
- 1989-10-26 JP JP27915789A patent/JPH03141666A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63136657A (en) * | 1986-11-28 | 1988-06-08 | Toshiba Corp | Both-side mounting electronic circuit device |
| JPH01199497A (en) * | 1987-11-10 | 1989-08-10 | Ibiden Co Ltd | Electronic component mounting substrate |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6040983A (en) * | 1997-04-16 | 2000-03-21 | Texas Instruments Incorporated | Vertical passive components for surface mount assembly |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS63211663A (en) | Circuit board | |
| JP3138539B2 (en) | Semiconductor device and COB substrate | |
| JPH0529537A (en) | Semiconductor module structure | |
| JPS59136963A (en) | Multilayer mounting structure of memory storage | |
| JPH03141666A (en) | Hybrid integrated circuit | |
| JP3615672B2 (en) | Semiconductor device and wiring board used therefor | |
| JPS6352461A (en) | Semiconductor device | |
| JPH05211256A (en) | Semiconductor device | |
| JP2706699B2 (en) | Semiconductor module | |
| JP3136274B2 (en) | Semiconductor device | |
| JP2766361B2 (en) | Semiconductor device | |
| JPS62155546A (en) | Memory module | |
| JPH05326833A (en) | Semiconductor mounting substrate | |
| JPH03190188A (en) | Multilayer circuit device and manufacture thereof | |
| JPS58120662U (en) | Chippukiyariya | |
| JPH03195091A (en) | Multilayered circuit device and its manufacture | |
| JPS62188249A (en) | Pin grid array package | |
| JPS63224346A (en) | Mounting structure for electronic component | |
| JP2841459B2 (en) | Hybrid integrated circuit | |
| JP3405718B2 (en) | Semiconductor device | |
| JP2826518B2 (en) | Semiconductor device | |
| JPS5879741A (en) | Connecting method for integrated circuit device | |
| KR970053665A (en) | Method of forming an electrode pattern on a substrate and a module package using the same | |
| JPH04133341A (en) | Semiconductor chip carrier | |
| JPS6286744A (en) | Lsi chip |