JPH031252A - Page fault processing system - Google Patents

Abstract

PURPOSE:To shorten the execution time of a program by executing the next and following instructions without awaiting the completion of data transfer from an external storage even when a page fault occurs in a write instruction. CONSTITUTION:The system is comprised in such a way that the program is restarted from the next instruction before the data transfer from the external storage 3 holding the data of a virtual page 1a(1b) is completed when the page fault occurs in the write operation for the virtual page 1a(1b) in the program, and the write instruction that is the cause of the page fault is executed when the data transfer is completed. In other words, a page fault interruption processing program is continued without making the program in which the page fault occurs in the write instruction await for long time, and also, a data transfer interruption processing affects the result of the write instruction issued from the program on the virtual page correctly. In such a way, the execution time of the program can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a page fault processing method for virtual memory of an electronic computer.

[Prior Art] FIG. 4 is a conceptual diagram showing the storage area configuration of an electronic Illumination system. In FIG. 4, (1) is a virtual memory in which program data is stored. However, the virtual memory (1) is virtual, and physically the data in the virtual memory (1) is placed on the real memory (2) or external memory (3). The virtual memory (1) is composed of a plurality of pages (1a) and (lb). In addition, the real memory (2) contains a plurality of real frames (2a
) and (2b).

The virtual pages (1a) and (1b) have real frames (2a
)(2b) Some have it and some don't. In the case of a virtual page (1a) with a real frame (2a), its data is physically placed in the real frame (2a). In the case of a virtual page (lb) that does not have a real frame, its data is physically located in external storage (3). When a command to refer to or write to a virtual page (1a) having a real frame (2a) is executed, it becomes physically the same as referring to or writing to a real frame (2a) due to the conversion mechanism of the 8-Dware. When a reference or write instruction is executed to a virtual page (1b) that does not have a real frame, a page fault interrupt occurs. (4) is the channel, written+l! ! This is a processor that transfers data between (2) and external storage (3).

Channel (4) generates a pig transfer completion side input when the data transfer is completed.

FIG. 5 is a diagram showing the software configuration within the computer. In the figure, (5) is a 10-gram program that executes the main operations of one applicable electronic meter (hereinafter simply referred to as a program).
0 Normally, it consists of multiple steps, and each step has one instruction.

Program (5) is executed one instruction at a time in the order of step numbers. However, when 8 interrupts occur, execution shifts to a processing program according to the type of interrupt. (6) is a page fault interrupt processing program, which is executed when program (5) causes a page fault interrupt. (7) is a pig transfer completion side import processing program, which is executed when channel (4) completes data transfer.

Figure 6 shows the page fault interrupt processing program (6)
FIG. 7 is a flowchart of the pig transfer completion side input processing program (7). In FIG. This section describes processing when a page fault interrupt occurs as a result of referencing or writing to a virtual page (1b) that does not exist. The page fault interrupt processing program (6) first instructs the channel (4) to transfer the contents of the virtual vegetable (1b) from the external storage (3) to the 5 unused real frames (2b) (step S5); After that, enter the waiting state (step S
7). The data transfer completion interrupt processing program (7) first allocates the real frame (2b) to the virtual page (1b) (step S9), and then restarts step J of the program (5) (step 13).

FIG. 8 is a diagram showing a series of operations after one program (5) causes a page fault.

The conventional page fault processing method is configured as described above, and in FIG. 8, instruction J in step J is a reference or write instruction to a virtual page (1b) that does not have a real frame (step 514). When this instruction is executed, a page fault interrupt occurs, and execution moves to the page fault interrupt processing program (6) (step 515).
) commands channel (4) to transfer data (step 55), then enters a waiting state (step S7), and while the waiting state continues, the data transfer by channel (4) is completed (step 516), A transfer completion interrupt occurs (step 517), and execution moves to the data transfer completion interrupt processing program (7) (step 518).
, the data transfer completion interrupt processing program (7) allocates the real frame (2b) containing the transferred data to the virtual page (1b) (step S9), and the program (
Step J of 5) is restarted. Program (5) executes instruction J again. However, the virtual page (1b) that is referenced and written by instruction J has a real frame (2b).

No page fault interrupt occurs and the instruction is executable (step 514). From now on, program (5) will execute steps after step (J + 1) in order (steps S18 to 520). .

[Problem to be Solved by the Invention 1] In the conventional page fault processing method as described above, when the program (5) writes to the virtual page (1b) in step J, the operation is similar to that of the virtual page (lb). Even though it is logically possible to execute steps (Jl-1> and beyond), the instruction execution of step (J + 1) is delayed until the data transfer is completed. There was a problem.

This invention was made to solve this problem. Even if a page fault occurs in a write instruction to a virtual page that does not have a real frame, processing of the next instruction and subsequent instructions is immediately executed without waiting for the data transfer to be completed. The purpose is to obtain a page fault processing method that can be continued.

[Means for Solving the Problems] One method of page fault processing according to the present invention is that in a virtual memory electronic computer system, when a program causes a page fault due to a write command to a virtual page, one method is to store the data of the corresponding virtual page. When the transfer from the retained external memory to the real memory is completed, the program is easily restarted from the next instruction, and when the transfer of the corresponding data is completed, the write instruction that caused the page fault is executed. This is what I did.

[A1 [5] In this invention, the page fault I/interrupt processing program uses a write command to continue the program that caused the page fault without keeping it open for a long time, and the data transfer interrupt processing is performed.

To correctly reflect the result of a write command issued by a program on a virtual page.

Embodiment] FIG. 1 is a diagram showing a flowchart of page fault processing according to an embodiment of the present invention.

FIG. 2 is a flowchart of a page fault interrupt processing program according to an embodiment of the present invention.

FIG. 3 shows the completion of data transfer according to an embodiment of the present invention.
FIG. 3 is a diagram showing a flowchart of an immersion processing program.

In the page fault processing method configured as described above, in step J of program (5).

A case will be described in which a store (STORE) instruction, which is a write instruction, is executed. The store instruction has two operands, and writes the contents of the register indicated by operand 1 to the virtual page indicated by operand 2. FIG. 2 is a flowchart of page fault interrupt processing 10 grams (6) that is executed when a base fault interrupt occurs as a result of specifying and executing a virtual page (1b) that does not have a real frame with operand 2. In FIG. 2, it is first determined whether or not the occurrence occurred when an instruction was fetched (step S1). If it was an instruction fetch, conventional processing is performed (steps S5 and S7).
If it is not the time to fetch an instruction, proceed to step S2.Next, it is determined whether the instruction that caused the page fault is a store instruction (step S2).If it is a store instruction, proceed to step S3.If it is not a store instruction, proceed to step S2. Conventional processing (steps S5 and 57) 6. Next, it is determined whether data has already been entered into variables R and A (step S3). If it is, the conventional processing is performed (steps S5 and S7). If not, proceed to step S4.First, store the contents of the register indicated by operand 1 of the store instruction in R, and save the address of the virtual page (Ib) indicated by operand 2 in 8. (Step S4). Next, the unused real frame (
2b) to channel (4) (step 85). Next, program (5) is executed by step (J
+1) to restart the process (step S6). FIG. 3 is a flowchart of a data transfer completion interrupt processing program (7) that is executed when a data transfer completion interrupt by channel (4) occurs at the time when instruction K in step of program (5) is completed. In FIG. 3, first, the real frame (2b) is allocated to the virtual page (1b) (step 59). Next, it is determined whether or not values are stored in R and A (step StO). For example, the process advances to step Sit, and if the data has not been saved, the zeroth order program (5), which is the conventional process (step 813), is restarted from step (K+1) (step 512).

Next is 1. A series of operations after the program (5) causes a page fault will be explained with reference to FIG. Here, step J of program (5) is a store instruction having virtual page (1b) as operand 2. program(
5) executes instruction J (step 514), and since the virtual page (1b) does not have a real frame, a page fault interrupt occurs.

The page fault interrupt handling program (6) is executed (step 315). Here, after executing several determinations (steps 81 to S3) in FIG. 2, values are saved in R and A, and the data Open the transfer (step 55) Next, the program (5) executes the instructions from step (J+1>) (step 918), and when it executes up to step K (step 519), the data transfer is completed and the program (step 516) ), an interrupt is generated and the data transfer completion interrupt processing program (7) is executed (step 517).

Here, after allocating the real frame (2b) to the virtual page (lb) (step S9), the store instruction, which is the instruction in step J, is executed using the values of R and A (step S5).
14), at this time, the virtual page (1b) is a real frame (
2b), a page fault does not occur.Subsequently, program (5) executes the instruction after step (K+1). However, if a page fault occurs when the instruction in step J is fetched, if instruction J is other than a store instruction, or if the same virtual page ( When a second page fault occurs for 1b), conventional processing is performed.

In the above embodiment, only store commands are received, but other write commands may also be read.

In addition, in the above embodiment, only one data storage variable R1A was provided, so only the first page fault could be handled. However, by providing multiple variables, multiple write commands can be processed. Become.

[Effect of the invention 1] As explained above, in this invention, even if a page fault occurs in a write instruction, the next instruction and subsequent instructions can be executed without waiting for the completion of data transfer from external storage, so the program execution time is shortened. There is an effect that can be done.

[Brief explanation of drawings]

FIG. 1 is a flow chart of a page fault l-processing method according to an embodiment of the present invention, FIG. 2 is a flow chart of a page 7 ortho interrupt processing program according to an embodiment of the present invention, and FIG. 3 is a flow chart of a page fault l-processing method according to an embodiment of the present invention. FIG. 4 is a conceptual diagram of the storage structure; FIG. 5 is a software configuration diagram; FIG. 6 is a flowchart of a conventional page fault interrupt processing program; FIG. FIG. 8 is a flowchart of a conventional pig transfer completion side input processing program, and FIG. 8 is a flowchart of a conventional page fault processing method. In addition, the same reference numerals in each figure indicate the same or corresponding parts. 2 figures, 5 figures, 3 figures, horses, 6 figures, and 7 figures for children.

Claims (1)

[Claims] In a virtual memory computer system, if a program causes a page fault with a write command to a virtual page, the above error occurs before the data transfer from the external memory holding the data of the virtual page to the real memory is completed. A page fault processing method characterized in that the program is restarted from the next instruction, and when the transfer of the relevant data is completed, the write instruction that caused the page fault is executed.