JPH03114333A - Clock synchronizing system in packet transmission and packet transmitter and packet receiver - Google Patents

Abstract

PURPOSE:To simply constitute the circuit and to stably establish clock synchronization between the transmitter and the receiver by controlling the frequency of a clock of the receiver so that each relative frequency of the transmitter and receiver clocks with respect to a clock (ATM clock) of a packet transmission network is coincident. CONSTITUTION:In order to make a sender oscillating frequency omega1 and a receiver oscillating frequency omega3 coincident, relative frequencies omegai, omegao with respect to a reference oscillating frequency omega2 available for the both (equivalent to ATM clock) are obtained. Then the frequencies are compared to control the receiver oscillating frequency omega3. Thus, in the case of packet transmission for a television signal or an audio signal, the clock synchronization between the transmitter and the receiver is established without use of an expensive equipment but having a problem in the quality of the information signal or use of a phase locked loop difficult of realization in the performance and without being affected by fluctuation of the packet arrival time.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention is a method for packetizing and transmitting continuous information signals without interruption in time, such as television signals and audio signals. The present invention relates to a clock synchronization method for synchronizing a transmitting side clock and a receiving side clock in a system, and a packet transmitting device and a packet receiving device to which this clock synchronizing method is applied.

(Conventional technology) For transmission of television signals (video signals) and audio signals,
Traditionally, fixed speed transmission lines have been used. However, in recent years, broadband ISDN (Integrated 5
As seen in the proposal of an asynchronous transfer mode (packet transmission mode using fixed-length cells, hereinafter referred to as ATM) of the erv1ces dlgltal network, television signals, audio signals, etc. are generated continuously in order to make effective use of transmission channels. ↑There is also an opportunity to transmit h-reports in packet form.

Television signals and audio signals are simply sampled and quantized (P
CM encoding alone provides fixed-rate information, but high-efficiency encoding that removes the inherent redundancy and audiovisual redundancy of the signal generally results in variable-rate information. For such variable-speed information, it is more efficient to use a variable-speed transmission system such as ATM than to use a fixed-speed transmission line, and the advantage is that the encoding quality is maintained high. be.

By the way, in packet transmission, it is important that clock synchronization between transmitting and receiving is established. This is because if clock synchronization is not established, the amount of encoded data and the amount of decoded data will differ, and normal decoding will not be possible. When transmitting television signals and the like using ATM, it is also necessary to consider the synchronization (bit synchronization) between the clock of the ATM network and the clock of the information source. That is,
Since the ATM transmission system does not take into account the bit rate etc. of individual information sources to ensure bit synchronization, the individual terminals (television signal encoding equipment, decoding equipment, etc.) connected to the ATM network Each must be dealt with accordingly. FIG. 4 shows the synchronization relationship between the transmitting side and the receiving side in television signal transmission via an ATM network.

In FIG. 4, a television video signal input from a signal source to a terminal 41 is digitized by, for example, studio equipment 42 using a clock (frequency fs) from a clock generation source 43 as a sampling frequency. This digital video signal (in the following explanation, it is all digitalized, so it is simply referred to as a video signal) is input to the encoding system, and the encoding clock (frequency fc) from the clock generation source 45 is input to the encoding system. After being highly efficiently encoded by a video encoding circuit 44 operating in The interface section 46 is for connecting the encoding system and the ATM transmission (packet transmission) system, and is composed of a packetization buffer memory, a packet header addition circuit, and the like.

The video signal packetized by the second interface unit 46 receives a clock (frequency f
The second interface section 4 performs the processing of the ATM network 4 wire 7 and the interface section 46 running in the ATM).
It is human-powered. The video signal decomposed into packets by the second interface unit 49 is decoded by a video decoding circuit 50 that operates with a decoding clock (frequency fd) from a clock generation source 51 and output from a terminal 52.

In the system shown in FIG. 4, the signal source, encoding, ATM transmission, and decoding are each independent clock generation sources 43, 45, and 48.
．． 51, it is necessary to synchronize the clocks in some way. In other words, in a synchronous transmission system such as a line mode, the clocks of each part are all phase-synchronized in advance, whereas in a packet transmission system such as an ATM transmission system, the connection method with a specific signal source and terminal equipment is generally used. Since this is not taken into account, it operates at a unique clock frequency (f ATM in FIG. 4). Therefore, when the signal source clock (fs) is supplied externally, generally fS/fAt is the difference between the encoding clock and the ATM clock.
A phase synchronization relationship cannot be maintained at a frequency ratio of M=n/m (n and m are integers).

Furthermore, although the encoding clock frequency fc and the decoding clock frequency fd must be the same frequency, there is an ATM transmission system between the encoding circuit 44 and the decoding circuit 50 that uses a unique clock frequency f ATM. Therefore, it is impossible to phase-synchronize the encoding clock and the decoding clock.

Conventionally, the following two countermeasures have been considered for the above problem.

(1) Phase-synchronize the encoding clock, ATM clock, and decoding clock (specifically, synchronize the encoding clock and decoding clock with the ATM clock as a reference). The signal source clocks are independent. Leave as is. At this time, the signal source and the decoding circuit are asynchronous, so a frame synchronizer is used to interface between them.

(2) First, the signal source clock and the encoding clock are phase-synchronized, and then output as is to the asynchronous ATM clock transmission system. The interface at this time is performed by the interface unit 6 shown in FIG. In this case, since the ATM transmission system output and the decoding clock are naturally asynchronous, the decoding circuit controls the decoding clock by some method to make it coincide with the encoding clock.

FIG. 5 and FIG. 6 show block diagrams when the above methods (1) and (2) are used, respectively.

In FIG. 5, similarly to the line mode synchronous transmission system, the encoding circuit 44, ATM network 47, and decoding circuit 50 are
Phase synchronization is performed using LL circuits 55 and 56. but,
As mentioned above, the clock frequency f used in the ATM network
Since ATM is determined without considering the relationship of integer ratios between fC and fd, it is generally determined that the signal source clock and A
The frequency ratio of n/m with the TM clock becomes complicated, and the comparison frequency in the phase-locked loop becomes extremely small, which has the disadvantage that it is difficult to operate the PLL circuit 55, 56 stably.

Furthermore, since the signal source clock externally input to the terminal 53 is generated independently of other clocks, the frame synchronizer 54 must be used to convert the clock frequency.

The frame synchronizer 54 has a video frame memory, and since it can write to this memory with an arbitrary clock and read with an arbitrary clock, it is possible to connect an asynchronous video processing system, but it is not only expensive but also However, since video frames are skipped (interlaced, iterative processing), problems may occur in image quality, and the relative delay time between video and audio changes significantly.

FIG. 6 shows an example in which a signal source clock inputted from a terminal 53 and an encoding clock are phase-synchronized in advance by a PLL circuit 61, and the decoding circuit 50 independently maintains clock frequency synchronization.

The decoding circuit 50 detects the video horizontal and vertical synchronization signals multiplexed in the packet in advance, and performs decoding output from the clock generation circuit 65 so that the synchronization signals appear periodically during the decoding process. control the frequency of the clock. That is, the packet disassembly/synchronization word detection circuit 62 (
When the synchronization word output from the ATV clock (operated with the ATV clock) is separated from video encoded data and written to the buffer 7 memory 63 using the ATM clock, and read out using the decoding clock, the synchronization word existing in the buffer memory 63 The number is detected by the synchronization word number detection circuit 64 and the decoding clock frequency is controlled. The number of synchronization words in the buffer memory 63 means the amount of synchronization words passed at each point in time,
If this is constant, it means that the clock frequencies on the encoding side and the decoding side match.

Using method (2) above overcomes the difficulty in synchronizing the encoding/decoding clock and ATM clock, which was a problem in (1), and also eliminates the need for a frame synchronizer, but it has the following drawbacks: exists. That is, since the ATM network is a packet transmission system, video encoded data is not transmitted at a constant speed, and there is temporal fluctuation in packets arriving at the receiving side depending on the availability of the network.

Although this fluctuation is naturally canceled during long-time integration, it is thought that it has a considerably low frequency component, and this affects the stability of frequency control of the decoding clock.

Therefore, the decoding clock contains a lot of low-frequency jitter due to the influence of the ATM network condition. This requires a phase-locked loop with an extremely low comparison frequency and a frame synchronizer, or requires frequency control of the decoding clock, which is susceptible to the ATM network conditions, making it difficult to implement in terms of circuitry and having problems with performance. There was a problem.

The present invention provides a clock synchronization method that can stably establish clock synchronization between transmission and reception with a simple circuit configuration in packet transmission of video signals, etc., and a packet transmitter and a packet receiver using this clock synchronization method. The purpose is to

C. Configuration of the Invention (Means for Solving the Problems) In order to achieve the above object, the clock synchronization method of the present invention provides a clock synchronization method from the transmitting side that indicates the relative frequency of the transmitting side clock to the tarock of the packet transmission network. Frequency data is transmitted as a packet along with an information signal, and the receiving side clock frequency data indicating the relative frequency of the receiving side clock with respect to the clock of the packet transmission network is compared with the received sending side clock frequency data, and the comparison result is The transmitting side clock and the receiving side clock are synchronized by controlling the frequency of the receiving side clock based on .

Further, the packet transmitting device according to the present invention includes means for detecting the relative frequency of the transmitting side clock with respect to the clock supplied from the packet transmission network and generating transmitting side clock frequency data indicating the relative frequency; and means for packetizing and transmitting the information signal data together with the information signal data.

Further, the packet transmitting device according to the present invention includes means for decomposing information signal data and transmitting side clock frequency data in a packet transmitted from the packet transmission network, and temporarily storing the decomposed information signal data and transmitting side clock frequency data. storage means for detecting the relative frequency of the receiving side clock with respect to the clock supplied from the packet transmission network and generating receiving side clock frequency data indicating the relative frequency; It has a comparison means for comparing the frequency data of the receiving side clock, and a means for controlling the frequency of the receiving side clock based on the comparison result of the comparing means.

(Function) Generally, it is difficult to accurately detect the frequency of the clock output from an oscillator, and it is difficult to detect the frequency of the clock output from two independent oscillators to completely eliminate the frequency difference between the two. It is also extremely difficult to control.

In the present invention, absolute accuracy is not required in detecting the clock frequency of the transmitting side and the receiving side, but detection is performed in the form of a relative frequency based on the clock supplied from the packet transmission network, and data at the transmitting side clock frequency is received. By informing the sender and the receiver, clock synchronization is established between the sender and the receiver. That is, the transmitting side clock frequency data informed to the receiving side is compared with the receiving side clock frequency data indicating a similar relative frequency at the receiving side, and the comparison result determines the transmitting side and receiving side clocks relative to the clock of the Paquesoto transmission network. The frequency of the receiving side clock is controlled so that the relative frequencies of the two coincide with each other.

As described above, the clock synchronization method of the present invention is basically frequency control and does not achieve phase synchronization, but generally a packet transmission system always includes a buffer memory as a temporary storage means, and this buffer The memory absorbs the phase error between the transmitting and receiving clocks. Furthermore, frequency errors during transient response of the control loop are also absorbed by the buffer memory.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of main parts on the transmitting side and receiving side of a video packet transmission system to which the clock synchronization method of the present invention is applied.

First, on the transmitting side, a video signal input manually to the signal input terminal 11 is processed together with a receiving clock (hereinafter referred to as an encoding clock) externally supplied to the clock input terminal 12 in synchronization with the video signal. The signal is input to a circuit, for example, a video encoding circuit 13, and is encoded. The output of this encoding circuit 13 is input to an interface circuit 14 . The interface circuit 14 includes a packetization circuit for packet transmission, a buffer memory circuit for clock frequency conversion, and the like. Also, terminal 1
The encoding clock input to the counter 2 is also applied to the clock input of the counter 15.

The clock (hereinafter referred to as ATM clock) supplied from the ATM network 20, which is a packet transmission network, to the sending side is as follows:
At the same time as it is input to the interface circuit 14, it is also input to the frequency divider circuit 16, and the frequency divider circuit 16 generates a pulse having a frequency of 1/N (N is a positive integer) of the ATM clock frequency. This pulse is applied to the count/clear input of the counter circuit 15. This counter circuit 15 is A
The number of encoding clocks is counted within a certain period based on the TM clock, and the count result is output. This count result is data ωj indicating the relative frequency of the encoding clock frequency with respect to the ATM clock frequency (this is referred to as transmitting side clock frequency data).
is transmitted together with the encoded video signal via the interface circuit 14 (multiplexed within the client,
It is sent to the TM network 20.

On the other hand, on the receiving side, the received packets are decomposed by a packet-soto decomposition circuit 21 and sequentially written into a buffer memory circuit 22 in synchronization with the ATM clock.

In this case, the video signal and the transmitting side clock frequency data ω1 that are multiplexed within the buffer memory circuit 22 are written.

In addition, the ATM clock supplied from the ATM network 20 to the receiving side is frequency-divided to 1/N by the frequency dividing circuit 23, just like the transmitting side, and is then applied to the count/clear input of the counter circuit 24. . This counter circuit 24 is an ATM
The number of clocks on the receiving side (hereinafter referred to as decoding clocks) is counted within a certain period based on the clock, and the count result is output. This count result is AT
This is data ω0 (hereinafter referred to as receiving side clock frequency data) indicating the relative frequency of the decoding clock based on the frequency of the M clock. The receiving side clock frequency data ω0, which is the count result of the counter circuit 24, is input to the subtraction input terminal of the subtraction circuit 25. The transmission side clock frequency data ωi read from the buffer memory 22 using the decoding clock is input to the addition input terminal of the subtraction circuit 25 . Therefore, the subtraction circuit 25 outputs a signal representing the difference between the two relative frequencies, ωI - ω0 - Δω.

The output of the subtraction circuit 25 is integrated by a loop filter 26 and then input to a control input terminal of a variable frequency clock generation circuit 27 for obtaining a decoding clock. As the loop filter 26, a completely integral type filter without leakage is suitable. Here, for example, Δω〉0(ωi〉
When ω0), the frequency of the decoding clock becomes high,
If a feedback control loop is configured so that the frequency of the decoding clock is low when Δω is 0, the decoding clock will also be synchronized with the ATV clock, and eventually the encoding clock (transmission clock) will be synchronized with the ATV clock. Synchronization with the decoding clock (receiving side clock) can be established. In this case, due to the integral action of the loop filter 26, no steady frequency error occurs.

Furthermore, even if fluctuations occur in the arrival time of packets in the ATM network 20, the buffer memory circuit 22 absorbs the fluctuations, so that the control loop for the receiving side clock is not affected.
It remains extremely stable. However, in the ATM network 20, so-called packet loss occurs, in which packets are stochastically dropped depending on the usage conditions. In that case, if the transmitting side clock frequency data ωl is not transmitted to the receiving side, the receiving side clock will not be controlled as a result, a frequency error will occur, and an overflow or underflow will occur in the buffer memory circuit 22. It could happen. However, the amount of data of this transmitter clock frequency data is extremely small compared to the video signal, so even if sufficient error correction (for example, by multiple transmissions) is performed to cope with packet loss, the transmission efficiency will decrease. can be ignored, and there is no practical problem at all.

FIG. 2 is a diagram illustrating the operating principle of an embodiment of the present invention.

In order to match the transmitting side oscillation frequency ω1 and the receiving side oscillation frequency ω, a reference oscillation frequency ω2 (
This corresponds to the ATM clock mentioned above. ) and compare them to determine the receiving side oscillation frequency ω.

control.

If FIG. 2 is expressed more simply, it will be as shown in FIG. 3, resulting in a negative feedback control loop. ωi, ω
0. The meaning of Δω is the same as in FIG. Kd is a parameter related to the loop gain, P(s) is the loop filter, and Kv is the frequency control sensitivity of the receiving side oscillator. ωB
t), ωo(L).

The Laplace transform of Δω([) is ωI(s
), ωo(s'), Δω(S), then Δω(s)−
ω1(s)−ωo(s) ...(1)Δω(
S)・Kd−F(s)・Kv＋Δω(s)=ωo(s)
...(2) From (1) and (2), it becomes when Kd-Kv·P(s)>1. Let F(s) be a completely integral type loop filter, for example, F(s)- + (a, b, O are constants), and Δω(s) zconst, then 1 i
m ωo(s)−ωI(s)S+0, and no steady frequency error occurs as described above.

Note that the above assumption of Δω(s) zconst can be achieved without any problems if a crystal-accurate oscillator is used for each clock generation source, and even if this is not the case, the transmitting side clock frequency data ωi can be set to a shorter period. This problem can be easily solved by transmitting at 100 kHz and widening the band of F(s) to speed up the control loop for the receiving side clock frequency.

In the above embodiments, the case where the present invention is applied to packet transmission of video signals has been described, but the present invention can be similarly applied to packet transmission of audio signals and other information signals as long as they are continuous information signals. The applicability is clear.

[Effects of the Invention] According to the present invention, when transmitting packets of television signals, audio signals, etc., there is no need to use expensive devices such as frame synchronizers, which have problems with purchasing information signals, or to use devices that are difficult to realize in terms of performance. Without using difficult phase-locked loops, which inevitably occur in packet transmission systems! The effect is that clock synchronization between transmission and reception can be established without being affected by fluctuations in arrival time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a packet transmission system to which the clock synchronization method of the present invention is applied, and FIG.
The figure is a diagram for explaining the operating principle of the present invention, Figure 3 is a block diagram showing the frequency control loop of Figure 2, and Figure 4 is a block diagram showing an overview of clock synchronization in the transmission system. , FIG. 5, and FIG. 6 are block diagrams for explaining the clock synchronization method in conventional packet transmission, respectively. 13... Video encoding circuit, 14... Interface circuit, 15... Sending side Counter circuit for detecting relative frequency of clock, 16... Frequency dividing circuit for detecting relative frequency of transmitting side clock, 20... ATM network (packet transmission network) 21... Packet disassembly circuit, 22.・・・
Buffer memory circuit (storage means) 23... Frequency divider circuit for detecting the relative frequency of the receiving side clock, 24... Counter circuit for detecting the relative frequency of the receiving side clock, 25...
Subtraction circuit (comparison means) 26... Loop filter (frequency control means) 27... Variable frequency clock generation circuit, 28... Video decoding circuit.

Claims (3)

[Claims] (1) In a system that transmits information signals via a packet transmission network that operates with a clock of a predetermined frequency, a transmission side sends transmission side clock frequency data indicating the relative frequency of the transmission side clock to the clock of the packet transmission network from the transmission side to the information signal. Packetized and transmitted with data,
On the receiving side, receiving side clock frequency data indicating the relative frequency of the receiving side clock with respect to the clock of the packet transmission network is compared with the received sending side clock frequency data, and based on the comparison result, the receiving side clock frequency data is compared. A clock synchronization method for packet transmission characterized by synchronizing a transmitter clock and a receiver clock by controlling the frequency. (2) means for detecting the relative frequency of a transmitter clock with respect to the clock of a packet transmission network and generating transmitter clock frequency data indicating the relative frequency; and packetizing the transmitter clock frequency data together with information signal data and transmitting the packet. A packet transmitting device comprising: means for transmitting a packet. (3) means for decomposing information signal data and transmitting side clock frequency data in a packet transmitted from a packet transmission network; storage means for temporarily storing the decomposed information signal data and transmitting side clock frequency data; and packet transmission. means for detecting a relative frequency of a receiving side clock with respect to a network clock and generating receiving side clock frequency data indicating the relative frequency; and transmitting side clock frequency data and said receiving side clock frequency data stored in said storage means. What is claimed is: 1. A packet receiving device comprising: comparing means for comparing the signals; and means for controlling the frequency of the receiving clock based on the comparison result of the comparing means.