JPH0296337A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0296337A JPH0296337A JP63249264A JP24926488A JPH0296337A JP H0296337 A JPH0296337 A JP H0296337A JP 63249264 A JP63249264 A JP 63249264A JP 24926488 A JP24926488 A JP 24926488A JP H0296337 A JPH0296337 A JP H0296337A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- insulating film
- probe
- contact
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 239000000523 sample Substances 0.000 abstract description 20
- 230000006866 deterioration Effects 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 238000003825 pressing Methods 0.000 description 3
- 241000270295 Serpentes Species 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 241000234435 Lilium Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本光明は、半導体８ｉ積回路を解析するにあたり、配線
上にプローブを接触させるようにした半導体装置に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device in which a probe is brought into contact with wiring when analyzing a semiconductor 8i integrated circuit.
従来の技術
半導体装置の解析を目的とし、配線面にプローブを接触
させることが可能なテスト・ポイントと称される部分を
もつ従来の半導体装置は、第２図（ａ）、 （ｂ）また
は第３図（ａ）、（ｂ）に示すような構成であった。BACKGROUND ART A conventional semiconductor device that has a portion called a test point that allows a probe to touch the wiring surface for the purpose of analyzing a semiconductor device is shown in FIGS. 2(a), (b) or The configuration was as shown in FIGS. 3(a) and 3(b).
第２図（ａ）、 （ｂ）において、１１はシリコン基板
、１２はシリコン基板１１の上に形成された絶縁膜・、
１３は絶縁膜１２上に形成された配線、１４はこれらの
上を覆う絶縁膜、１５は絶縁膜１４に設けられたコンタ
クト孔、１６はプローブである。この場合、絶縁膜１４
のコンタクト孔１５内の配線面は外部に露出した状態で
構成されたものであった。In FIGS. 2(a) and (b), 11 is a silicon substrate, and 12 is an insulating film formed on the silicon substrate 11.
13 is a wiring formed on the insulating film 12, 14 is an insulating film covering these, 15 is a contact hole provided in the insulating film 14, and 16 is a probe. In this case, the insulating film 14
The wiring surface within the contact hole 15 was configured to be exposed to the outside.
第３図（ａ）、 （ｂ）においては、２１はシリコン基
板、２２は絶縁膜、２３は配線、２４は絶縁膜、２５は
プローブである。この場合、配線面上は絶縁膜２４で覆
われ、配線面は外部に露出しない状態で構成されたもの
であった。In FIGS. 3(a) and 3(b), 21 is a silicon substrate, 22 is an insulating film, 23 is a wiring, 24 is an insulating film, and 25 is a probe. In this case, the wiring surface was covered with an insulating film 24 so that the wiring surface was not exposed to the outside.
発明が解決しようとする課題
しかしながら、このような従来の構成では、第２図（ａ
）、（ｂ）に示す半導体装置においては、コンタクト孔
１５から水分が浸透し、配線１３の劣化にともない、信
頼性の低下をまねくという問題があり、また、第３図（
ａ）、 （ｂ）に示す半導体装置においては、プローブ
２５に圧力を加えて配線面上の絶縁膜２４を破壊し、プ
ローブ２５と配線面を接触させる際に、プローブ２５が
絶縁膜２４の上をす外り、他の隣接する配線上の絶縁膜
が破壊したり、両配線而間が短絡するという問題があっ
た。Problems to be Solved by the Invention However, in such a conventional configuration, the problem as shown in FIG.
In the semiconductor device shown in FIG.
In the semiconductor devices shown in a) and (b), the insulating film 24 on the wiring surface is destroyed by applying pressure to the probe 25, and when the probe 25 and the wiring surface are brought into contact, the probe 25 is placed on the insulating film 24. In addition, there was a problem that the insulating film on other adjacent wirings would be destroyed or the two wirings would be short-circuited.
本発明は上記問題を解決するもので、配線の劣化や隣接
配線の短絡を招くことなくプローブを目的の配線に確実
に接触させることができる半導体装置の提供を目的とす
るものである。The present invention solves the above problem, and aims to provide a semiconductor device that allows a probe to reliably contact a target wiring without causing deterioration of the wiring or short-circuiting of adjacent wiring.
課題を解決するための手段
上記問題を解決するために本発明は、配線の一部に穴部
が形成され、この穴部を含めて前記配線上に絶縁膜が形
成されているものである。Means for Solving the Problems In order to solve the above problems, in the present invention, a hole is formed in a part of the wiring, and an insulating film is formed on the wiring including the hole.
作用
上記構成により、配線面上の穴部によって絶縁膜にも段
差が生じ、その結果、プローブに圧力を加える際に、プ
ローブを絶縁膜の段差部に接触させることにより、プロ
ーブのすべりがおさえられ、それと同時に段差部で圧力
を加えることにより、段差部のうすい絶縁膜が容易に破
壊されて穴部周囲の配線部分にプローブの先端が確実に
接触する。Effect With the above configuration, a step is created in the insulating film due to the hole on the wiring surface, and as a result, when applying pressure to the probe, by bringing the probe into contact with the step in the insulating film, slipping of the probe can be suppressed. At the same time, by applying pressure at the stepped portion, the thin insulating film at the stepped portion is easily destroyed, and the tip of the probe reliably contacts the wiring portion around the hole.
また、配線面全面は絶縁膜で覆われて外部に露出してい
ないので、この配線が劣化することはない。Further, since the entire wiring surface is covered with an insulating film and is not exposed to the outside, the wiring does not deteriorate.
実施例 以下、本発明の一実施例を図面に基づいて説明する。Example Hereinafter, one embodiment of the present invention will be described based on the drawings.
第１図（ａ）、 （ｂ）は本発明の一実施例による半導
体装置を示すものであって、第１図（ａ）は断面図、第
１図（ｂ）は平面図である。第１図（ａ）、 （ｂ）に
おいて、半導体集積回路が形成されたシリコン基板１の
上に第１の絶縁膜２が形成され、その上に配線層３が形
成される。配線層３はたとえばアルミニウムからなり、
その厚みはたとえば２μｍ程度に形成される。配線層３
の一部には解析などの目的に用いられる穴部５が設けら
れている。穴部５を含めた配線層３の上は保護膜となる
第２の絶縁膜４で覆われ、穴部５の上の絶縁膜４には段
差部７が形成される。第２の絶縁膜４はたとえば窒化シ
リコン膜あるいは酸化シリコン膜からなり、その厚みは
たとえば１μｍ程度に形成され、配線層３より簿く形成
される。第２の絶縁ｒＩＡ４は通常ＣＶＤ法によって形
成されるが、平面上に対して側面の膜厚が薄くなる。し
たがって、解析などの目的でプローブ６を第２の絶縁膜
４の段差部７に接触させると、穴部５９Ｊ而の絶縁膜４
は簿いため、わずかの圧力で容易に破壊することができ
、さらに、第２の絶縁膜４より配線層３の方が厚いため
、段差部７において、プローブ６は配線Ｍ３に接触する
とともに、すべることがない。また、配線層３の穴部５
は第２の絶縁膜４で覆われて外部に露出していないので
水分の浸透による劣化はなく、良好な信頼性が保たれる
。なお、穴部５が配線層３を貴通して段差部を構成して
もよい。FIGS. 1(a) and 1(b) show a semiconductor device according to an embodiment of the present invention, with FIG. 1(a) being a sectional view and FIG. 1(b) being a plan view. In FIGS. 1A and 1B, a first insulating film 2 is formed on a silicon substrate 1 on which a semiconductor integrated circuit is formed, and a wiring layer 3 is formed thereon. The wiring layer 3 is made of aluminum, for example,
The thickness thereof is, for example, approximately 2 μm. Wiring layer 3
A hole portion 5 is provided in a part of the hole portion 5 to be used for purposes such as analysis. The wiring layer 3 including the hole 5 is covered with a second insulating film 4 serving as a protective film, and a stepped portion 7 is formed in the insulating film 4 above the hole 5. The second insulating film 4 is made of, for example, a silicon nitride film or a silicon oxide film, has a thickness of about 1 μm, and is formed thinner than the wiring layer 3 . The second insulator rIA4 is usually formed by CVD, but the film thickness on the side surface is thinner than that on the plane surface. Therefore, when the probe 6 is brought into contact with the stepped portion 7 of the second insulating film 4 for the purpose of analysis, etc., the hole 59J is exposed to the insulating film 4.
Since the wiring layer M3 is thin, it can be easily destroyed with a slight pressure.Furthermore, since the wiring layer 3 is thicker than the second insulating film 4, the probe 6 comes into contact with the wiring M3 at the stepped portion 7 and slips. Never. In addition, the hole 5 of the wiring layer 3
Since it is covered with the second insulating film 4 and is not exposed to the outside, there is no deterioration due to penetration of moisture, and good reliability is maintained. Note that the hole portion 5 may pass through the wiring layer 3 to form a stepped portion.
発明の効宋
以上のように本発明によれば、配線面上は穴部を含めて
絶縁膜で覆われているので、従来の半導体装置にみられ
た水分の浸透による信頼性の低下を防止することができ
るとともに、配線の一部に穴部を設けたので、プローブ
を配線の解析の必要性のある箇所に確実に接触でき、隣
接配線の短絡を生じることはない。Effects of the Invention According to the present invention, as described above, the wiring surface, including the holes, is covered with an insulating film, which prevents the deterioration in reliability due to moisture penetration that occurs in conventional semiconductor devices. In addition, since a hole is provided in a part of the wiring, the probe can be reliably brought into contact with a portion of the wiring that requires analysis, and short circuits between adjacent wirings will not occur.
４、図面のｌ！ＪＩＩＩな説明
第１図（ａ）、 （ｂ）は本発明の一実施例を示す半導
体装置の断面図および平面図、第２図（ａ）、 （ｂ）
と第３図（ａ）、 （ｂ）はそれぞれ従来の半導体装置
の断面図および平面図である。4.L of the drawing! 1 (a) and (b) are a cross-sectional view and a plan view of a semiconductor device showing one embodiment of the present invention, and Fig. 2 (a) and (b) are
3(a) and 3(b) are a sectional view and a plan view, respectively, of a conventional semiconductor device.
１・・・シリコン基板、２・・・第１の絶縁膜、３・・
・配線層、４・・・第２の絶縁膜、５・・・穴部、７・
・・段差部。DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... First insulating film, 3...
・Wiring layer, 4... second insulating film, 5... hole, 7.
・Step part.
代理人 森 本 ｉ 弘 第 図 （θン （ｉ） ！・−シッフ〉基淳及 ２−・屈ｌの蛇、橡履 ３−配、線層 ４−躬２へ蛇、縁腰 ５−穴部 ７−・放羞弊 第２図 （ｔｌ） （ｂ） 第３ （ａ） （ｂンAgent Hiroshi Mori No. figure (θn (i) !・-Schiff〉Atsushi Kiyoshi 2- Crooked snake, lily 3- Wiring, line layer 4 - Snake to Tsumu 2, Enkoshi 5-Hole 7-・Disgrace Figure 2 (tl) (b) Third (a) (b-n
Claims (1)
記配線上に絶縁膜が形成されている半導体装置。1. A semiconductor device in which a hole is formed in a part of the wiring, and an insulating film is formed on the wiring including the hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63249264A JPH0296337A (en) | 1988-10-03 | 1988-10-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63249264A JPH0296337A (en) | 1988-10-03 | 1988-10-03 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0296337A true JPH0296337A (en) | 1990-04-09 |
Family
ID=17190377
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63249264A Pending JPH0296337A (en) | 1988-10-03 | 1988-10-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0296337A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005209964A (en) * | 2004-01-23 | 2005-08-04 | Shin Etsu Handotai Co Ltd | Method for evaluating semiconductor wafer and wafer for evaluation |
-
1988
- 1988-10-03 JP JP63249264A patent/JPH0296337A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005209964A (en) * | 2004-01-23 | 2005-08-04 | Shin Etsu Handotai Co Ltd | Method for evaluating semiconductor wafer and wafer for evaluation |
| JP4506181B2 (en) * | 2004-01-23 | 2010-07-21 | 信越半導体株式会社 | Semiconductor wafer evaluation method |
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