JPH028946A - Cache memory control system - Google Patents

Abstract

PURPOSE:To perform a processing without nullifying the content of a cache memory by broadcasting write data to all the central processing units, and writing the write data on the cache memory corresponding to a recognized central processing unit. CONSTITUTION:The write data is broadcasted to all the CPUs (2a-2d) at the time of performing a write operation, and broadcasted write data is written actually on the cache memory corresponding to the CPU recognized by a recognition means (parallel processing mode flags 9a-9d) via a transfer means (data bus 11). Assuming that arrangements (A1-A8) exist in the same block in a main memory device 1, the block is read out to all of four CPUs (2a-2d), and all the CPUs (2a-2d) perform write on the block. In such a case, the CPU2a writes the data in the arrangement A1 and the CPU2b writes the data in the arrangements A2 on the same block, respectively.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention describes a cache memory control method in a multiprocessor system that shares a main memory. [Prior Art] FIG.
Written by Glen G., Langdon, Jr. (CO
M P UTEACH PRESS INC, 1982
) is a block diagram showing the configuration of the cache memory control method shown in FIG. In the figure, 1 is a main memory that stores data necessary for data processing, 2 is a central processing unit (CPU) that shares this main memory 1 and performs calculations and controls related to data processing, and 3 is a central processing unit 2. and a cache memory for speeding up data transfer between the main storage device 1 and the main storage device 1;
5 is a read data bus, 5 is a main memory read path, 6 is a write data bus, 7 is a load through path, and 8 is a store through path.

Next, the operation will be explained. The cache memory 3 stores data when the central processing unit 2 accesses the data from the main storage device 1.

It is said that data that has been used -i times has a high possibility of being used again, and data can often be accessed from this cache memory 3 during subsequent data access. Furthermore, the cache memory 3 can normally be accessed much faster than the main storage device 1, so if the data to be accessed is in the cache memory 3, the data can be accessed quite quickly. When the data is not in the cache memory 3, it is necessary to access the data to the main storage device 1, which slows down the process.

When the central processing unit 2 accesses data, first,
A request for necessary data is issued, and it is tested whether or not the requested access data exists in the cache memory 3. If there is, the data in the cache memory 3 is read out and taken out from the data bus 4 as is. If there is no necessary data in the cache memory 3, the main +! 1MfF, data is once read from the main storage device 1 into the cache memory 3 via the spill bus 5, and then the data is read from the cache memory 3. Alternatively, a similar test can be carried out during a write operation in which data is read from the main memory 'II + iJL output path 5 to the cache memory 3 and simultaneously read from the central processing unit 2/\\ via the rotary through bus 1. Written to storage device 1.

Therefore, it is desirable to store frequently used data in the cache memory 3, which has a considerably smaller capacity than the main storage device 1. Normal cache memory 3
Replacement of the data in the cache memory 3 is performed in such a way that the most recently used data (accepted data remains in the cache memory 3 for a long time) and the oldest used data is returned to the main device 1. .

Furthermore, as shown in FIG. 5, in a multiprocessor system in which a plurality of central processing units each having such a cache memory are combined to share the main storage device 1,
There are further complications. In a multiprocessor system, the same main storage device 1 is shared, so the cache memories 3a to 3d, which are copies of the main storage device 1, have the same main storage device 1 corresponding to the plurality of central processing units 2a to 2d. A copy of the data may exist. If any central processing unit rewrites the contents of its cache memory, the copies of the data before the update in the cache memories 3a to 3d in all central processing units 2a to 2d are no longer correct and may be used incorrectly. It is necessary to make it invalid so that it does not occur. This is called cache memory invalidation. This invalidation of the cache memory normally occurs every time the central processing unit writes.

FIG. 6 shows a data store operation (write operation) in one central processing unit 2 in a multiprocessor system. In this flowchart 1,
At times 1 to 1A, the description is made assuming that the write to the main memory device 1 is performed after the cache hit and the store is one-sided ≠.

In FIG. 6, in step S1 it is determined whether or not there is data in a certain cache memory. If there is data, the process moves to step S3 and the data is stored in the cache memory 3. If there is no data, the process moves to step S2 and the main memory Store data in 1.

In step S4, it is determined whether or not the target data exists in the cache memory of another central processing unit. If the target data exists, the process moves to step S6 and invalidates the contents of the cache memory of the other central processing unit. If there is no target data, the process moves to step S5 and no processing is performed.

As shown here, when storing data, in the case of a cache hit or a cache miss, the content of the cache memory of the central processing unit is tested to determine if the target data is the old thread. If the cache memory is also present in the central processing unit, it is necessary to invalidate that cache memory.

In recent multiprocessor systems, unlike the conventional parallel processing that aims to improve system throughput by allocating multiple jobs to multiple central processing units, When a device executes one job, parallel processing may be performed for the purpose of improving the response of that job. In this case, data in the same block of the main memory may be divided among multiple central processing units, and data in the same block is frequently accessed by different central processing units.

For example, as shown in Figure 2, if you want to have a loop in a certain program processed in parallel by multiple central processing units, you can take advantage of so-called spatial parallelism and divide the loop into parts for each repetition. It is often done to treat In the example in Figure 2, the statements D OA, LL represent parallel processing, and assuming there are four central processing units, each of the four expressions in this loop executes one central processing unit. indicates that it is assigned to In other words,
The loop repetition is divided into four parts, and the central processing unit 2a processes the first expression for the first, fifth, ninth, and so on, and the central processing unit 2b processes the second expression. The 2nd, 6th, and 1st iteration of the process
The central processing unit 2c processes the third expression for the 0th time, and the central processing unit 2d processes the fourth expression for the 3rd, 7th, 11th, and so on. Uke holds the 4th, 8th, 12th, etc. of a certain repetition. This means that data that is spatially concentrated, for example, the elements of array A, will be purposely divided into multiple central processing units, so the cache memories 3a to 3d of multiple central processing units 2a to 2d will be The result is that there are blocks of identical data for the elements of array A.

In order to maintain the validity of the data in the plurality of cache memories 3a to 3d, each time each central processing unit writes data to a block, the address of the written block must be sent to the other system. It is necessary to send the data to the central processing unit and invalidate the data in the corresponding cache memory block of the central processing unit that has the block at that address in the cache memory. When a central processing unit that had an invalidated block wants to use that block, it needs to access the block from the main memory 1 again, only a portion of which has been changed.

In the example of FIG. 2, 1 in each central processing unit 2a to 2d.
This situation occurs every time one operation is processed. Each time, the performance of the invalid processor system of the data in the cache memories 3a-3d in each central processing unit 2a-2d is greatly affected.

[Problems to be Solved by the Invention] Since the conventional cache memory control method operates as described above, in a multi-processor sensor system that executes parallel processing, the cache memory is There is a problem in that each time a request is made to invalidate the contents of a file, data is transferred between the cache memory and the main storage, resulting in a significant drop in processing performance.

This invention was made to solve the above-mentioned problems, and it improves processing performance by invalidating the contents of the cache memory corresponding to all central processing units every time a write operation is performed. The purpose of this invention is to obtain a cache memory control system that can improve the performance of cache memory.

[Means for Solving the Problems] A cache memory control method according to the present invention provides that when two or more designated central processing units are executing parallel data processing, the designated central processing units Recognition means for recognizing that the central processing unit is one of the groups of central processing units 2a to 2d (parallel processing mode flags 9a to 9d)
and a transfer means (data bus 11) for directly transferring data between each cash memory 3a to 3d,
During a write operation, the write data is broadcast to all the central processing units 2a to 2d, and the write data is transferred to the cache memory corresponding to the central processing unit recognized by the recognition means via the transfer means. The feature is that the data is actually written.

[Operation] In the cache memory control method of the present invention, corrupted data is sent to all central processing units 2 during a write operation.
a to 2d, and the broadcast write data is sent to the cache memory corresponding to the central processing unit recognized by the recognition means (parallel processing mode flags 9a to 9d) via the transfer means (data bus 11). actually written.

[Embodiment of the Invention] FIG. 1 is a block diagram showing the configuration of a multiprocessor system employing a cache memory control method according to an embodiment of the invention. In the figure, 1 is a main memory that stores data necessary for data processing, 2a to 2d are a plurality of central processing units (CPUs) that share the main memory 1 and perform calculations and controls related to data processing, and 3a to 3d are CPUs that perform calculations and controls related to data processing. A plurality of cache memories are provided corresponding to the central processing units 2a to 2d, respectively, to speed up data transfer between the central processing units 2a to 2d and the main storage device 1; A global memory path 11 for accessing the storage device 1 is each cash memory 3a to 3.
data buses 9a to 9 that broadcast write data to all central processing units 2a to 2d during write operations;
d is for recognizing that the designated central processing unit is one of the plurality of central processing unit groups 2a to 2d when parallel data processing is being executed by two or more designated central processing units. This is a parallel processing mode flag as a recognition means.

Next, the operation will be explained.

FIG. 1 shows a multiprocessor system having four central processing units 2a to 2d. When performing parallel processing in this multiprocessor system, the simplest and most common method is to divide the loop portion of the program. If parallelization is automatically performed by a compiler or the like, the division is often as simple as this due to the difficulty of parallelization. For example, as shown in Figure 2, a loop with a large number of repetitions is divided into four,
Transform as indicated by the DOALL statement.

The statement DOALL indicates parallel processing and indicates that each of the four expressions in this loop is assigned to one central processing unit. In other words, the repetition of the loop is divided into four parts, and the central processing unit 2a processes the first expression in the first, fifth, ninth, and so on.
The central processing unit 2b processes the second expression for the second, sixth, tenth time, etc.
The central processing unit 2d processes the fourth expression in the 4th, 8th, and so on for the 3rd, 7th, 11th, etc. of the repetition in which C processes the 3rd expression. The 12th time...
・Uke is assumed to have.

FIG. 3 shows the data in the cache memories 3a to 3d of the respective central processing units 2a to 2d at this time. Assuming that arrays A1 to AS are in the same block in the main memory device 1, this block is divided into four central processing units 2
All four central processing units 2a to 2d write to this program. In this case, the central processing unit 2a stores array A1, the central processing unit 2b stores array A2 as its adjacent element, the central processing unit 2C further stores array A3 as its adjacent element, and the central processing unit 2d stores the array A2 as its adjacent element. Array A of adjacent elements of A3
4 will be written into the same block. The flow of this operation [t continues after this point, and the adjacent central processing unit always writes data to an element adjacent to the element to which writing has been performed. At this time, each central processing unit 2
The parallel processing mode flags 9a to 9d in a to 2d are all on, indicating that all central processing units 2a to 2d are in parallel processing mode. According to this, write operation 1 sometimes sends the address where the data was written to the central processing unit of the other system, and instead of invalidating the cache memory of the central processing unit of the other system,
The write data is broadcast from the data bus 11 to all the central processing units along with the address of the data written to the old central processing unit. As a result, each central processing unit 2a to 2d whose parallel processing mode flags 9a to 9d are on and which holds a block containing written data takes in the written data sent to the cache memory 3a. By actually writing into cache memories 3a to 3d, the contents of cache memories 3a to 3d can be maintained valid, eliminating the need for invalidation.

In the above embodiment, the multiprocessor system operates in the parallel processing mode, but it is desired that the system has a certain degree of effect even when running in the normal mode. In addition, in the embodiment, instead of invalidating the cache memory when storing data only during parallel processing operation, the store data (write data) is broadcast to all central processing units, and the parallel processing mode flag is turned on. It was supposed to be written to the cache memory of the central processing unit. This is based on the fact that during normal parallel processing operations, loops are often divided as mentioned above, and there is a very high possibility that multiple central processing units will share and use the same block of data. . However, in some actual jobs, the user may explicitly declare in the program that multiple central processing units will be used to perform processing. Even in this case, since data may be shared among multiple central processing units, the central processing unit used in the software should be aware that the user will access the same block of data between multiple central processing units. The desired effect can also be obtained by specifying a device and broadcasting stored data without invalidating the cache in the specified central processing unit.

[Effects of the Invention] As described above, according to the present invention, write operation 1 is performed by broadcasting write data to all central processing units at the same time, and writing data to the cache memory corresponding to the central processing unit recognized by the recognition means. Since the data is actually written by transferring it via a transfer means, the writing operation is 1t.
Each time, processing is performed without invalidating the contents of the cache memory corresponding to all central processing units, and write data is written to the cache memory corresponding to the recognized central processing unit, thereby updating the data in the cache memory. This has the effect of reducing data exchange between main storage devices such as the cache memory, thereby improving processing performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a multiprocessor system that employs a cache memory control method according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of a typical program that is processed in parallel in this embodiment. , Fig. 3 is a diagram showing how data is divided on the cache memory of each central processing unit when the program is executed in this embodiment, and Fig. 4 is a diagram showing how data is divided on the cache memory of each central processing unit when the program is executed in this embodiment. FIG. 5 is a block diagram showing the structure of a multiprocessor system employing a conventional cache memory control system, and FIG. 6 is a flowchart showing the operation of the cache memory in this conventional example.

Claims (1)

[Claims] A main storage device that stores data necessary for data processing;
A plurality of central processing units that share this main storage device and carry out calculations and controls related to data processing, and are provided corresponding to each of these central processing units to speed up data transfer between the central processing unit and the main storage device. In a multiprocessor system with multiple cache memories for
recognition means for recognizing that the designated central processing unit is one of the plurality of central processing unit groups when parallel data processing is being executed by the designated two or more central processing units; , a transfer means for directly transferring data between each of the cache memories, and transfers write data to all central processing units during a write operation, and corresponds to the central processing unit recognized by the recognition means. A cache memory control method characterized in that the write data is transferred to the cache memory via the transfer means to be actually written.