JPH02887B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a low output impedance circuit used in an output stage of an operational amplifier or the like.

A conventional low output impedance circuit of this type is constructed as shown in FIG. In the same figure
Both T ₄ and T ₅ are p-channel (or n-channel) MOS transistors, and are connected in series between power supplies V _A and V _C . Transistor T ₄ is a constant current source, and a constant voltage V _B is applied to its gate. Transistor T ₅ is used as a source hollow,
An input voltage V _io is applied to its gate. The potential V ₃ at the connection point of transistors T ₄ and T ₅ is the output voltage V _put
and is applied to a load (not shown). Let the current amplification factors of the transistors T ₄ and T ₅ be β ₄ and β ₅ , and let their threshold voltage be V _th , and furthermore, the current flowing through the transistors T ₄ and T ₅ and the load current are I ₀ , I ₂ , and If I ₁ , then the transistor
Assuming that T ₄ and T ₅ operate in a saturated state, the following equation holds.

I ₀ ≒β ₄ /2 (V _B −V _A −V _th ) ² ...(a) I ₂ ≒β ₅ /2 (V _io −V _put −V _th ) ² ...(b) I ₁ +I ₂ =I ₀ (const.) ……(c) From these formulas, the input/output voltage difference is If there is no load (I ₁ = 0), I ₂ = I ₀ = const., so V _put −V _io = (const.) ...(e). However, since the load current is generally not zero, _I2 changes in the opposite direction to _I1 . When I ₂ changes
As is clear from equation (d), the input/output voltage difference changes approximately in proportion to the square root of the change. Therefore, in order to satisfy the requirement for a low output impedance circuit that the output voltage _Vput does not change even if the load current _I1 changes, in other words, the input/output voltage difference does not change, the circuit shown in Figure 1 (d ) by increasing β ₅ in the equation, or by always passing a large current with I ₀ , the change in I ₁ and therefore
This can be ignored because the change in I ₂ is relatively small and works as a square root.

Therefore, this type of circuit has the following drawbacks.
(1) Even if the load current I ₁ is small, I ₀ is always the maximum current, so power is wasted. (2) When the output impedance is given, β, which is a problem in IC,
Taking into account variations in V _th, etc., it is necessary at the worst.
If I ₀ is made to be obtained, I ₀ as a design value becomes a considerably large value, which results in aggravating the drawback of (1) above.

The present invention proposes a low output impedance circuit free from such drawbacks, and its features include a first MOS transistor that serves as a variable constant current source, and a second MOS transistor to which an input voltage is applied to the gate. are connected in series and the connection point is set as the output terminal, and the current flowing through the load connected to the output terminal and the second
The sum of the currents flowing through the MOS transistors is the first
In a low output impedance circuit that is supplied from a power source through a MOS transistor,
a linear voltage generating element that converts a change in the current flowing through the second MOS transistor into a voltage change; a gate receives the output voltage of the voltage generating element; the voltage change is transferred from the source to the gate of the first MOS transistor; 3rd MOS that returns with level shift
transistor, and a fourth MOS transistor connected to the source of the third MOS transistor and operating as a constant current source.
MOS transistors, the first to fourth MOS transistors are of the same conductivity type and are operated in a saturated state, and the voltage applied to the gate of the first MOS transistor is adjusted according to changes in the current flowing through the load. By changing the current flowing through the second MOS transistor and keeping it constant regardless of changes in the load current, the potential difference between the input voltage and the output voltage is kept constant.

The present invention will be described in detail below with reference to the embodiment shown in FIG. The figure shows the circuit in Figure 1 with a resistor R and MOS transistors T ₁ to T ₃ added, but the gate of transistor T ₄ (first MOS transistor) is connected to transistors T ₁ and T ₂ . A point potential V ₁ is applied. Therefore, unlike in FIG. 1, the transistor _T4 becomes a variable constant current source controlled by the potential _V1 . The resistor R is a linear voltage generating element connected between the transistor _T5 and the power supply _Vc , and the potential _V4 at the connection point with the transistor _T5 is applied to the gate of the transistor _T3 .
Transistor connected in series between power supplies V _A and V _C
Among T ₁ to T ₃ , transistor T ₁ has a constant voltage on the gate
V _B is applied, and it functions as a constant current source that always flows a constant current I ₃ . The potential V ₂ at the connection point with the transistor T ₃ is applied to the gate of the transistor T ₂ ,
Functions as a constant voltage element for level shifting.

In the above configuration, assuming that transistors T ₁ to _{T 5} are all p-channel type and operate in a saturation region, the following equations (1) to (6) hold true.

I ₀ = I ₁ + I ₂ ... (1) I ₀ = β ₄ /2 (V ₁ − V _A − V _th ) ² ... (2) V ₄ = V _C + I ₂ R ... (3) I ₃ (const)≒β ₁ /2 (V _B −V _A −V _th ) ² …(4) ≒β ₂ /2 (V ₂ −V ₁ −V _th ) ² …(5) ≒β ₃ /2 (V ₄ −V ₂ −V _th ) ² ...(6) Below, the change ΔI ₂ in the current I 2 when the output load current I ₁ increases _{by ΔI 1 is} calculated. Change in voltage V ₄ ΔV ₄
is ΔV ₄ =V _C +R(I ₂ +ΔI ₂ )−(V _C +RI ₂ ) =RΔI ₂ ...(7), so from equations (1) to (7), ΔV ₁ ≒ΔV ₄ =RΔI ₂ ... …(8) The following relationship is derived. Therefore, the change ΔI ₀ in the current I ₀ is calculated from equations (2) and (8) as follows: ΔI ₀ =β ₄ /5(V ₁ +RΔI ₂ −V _A −V _th ) ² −β ₄ /2(V ₁
−V _A −V _th ) ² …(9) = β ₄ /2・R・ΔI ₂ {2(V ₁ −V _A −V _th )+RΔI ₂ }
...(10) becomes. Also, as is clear from equation (1), ΔI ₀ =ΔI ₁ +ΔI ₂ ...(11), so the following equation can be derived from equations (10) and (11).

β ₄ RΔI ₂ {V ₁ −V _A −V _th +RΔI ₂ /2} = ΔI ₁ +ΔI ₂ ...(12) In order for the p-channel transistor T ₄ to be in a conductive state, in equation (10), V ₁ +RΔI ₂ −V _A −V _th <0 ...(13) V ₁ −V _A −V _th <0 ...(14) Therefore, V ₁ +1/2RΔI ₂ −V _A −V _th <0... (15) is derived, and then the following equation can be derived from equations (12) and (15).

1+ΔI ₁ /ΔI ₂ <0 ...(16) Equation (16) is ΔI ₂・ΔI ₁ <0 ...(17) and |ΔI ₂ |<|ΔI ₁ |...(18) It is shown that.

On the other hand, by transforming equation (12), ΔI ₂ is expressed as follows.

ΔI ₂ =−ΔI ₁ /1+β ₄ R(V _A +V _th −V ₁ )−
β ₄ ／2R ² ΔI ₂ ...(19) ∴｜ΔI ₂ ｜=｜ΔI ₁ ｜/｜1+β ₄ ／2R(V
_A +V _th −V ₁ ) β ₄ R/2 (V _A +V _th −V ₁ −RΔI ₂ ) |……(
20) Here, from equations (13) and (14), 1+β ₄ /2R(V _A +V _th −V ₁ )+β ₄ R/2(V _A +V _th −V
₁ −RΔI ₂ )＞1+β ₄ /2R(V _A +V _th −V ₁ )……(21)
1+β ₄ /2R(V _A +V _th −V ₁ )＞1 …(22) ∴｜1+β ₄ /2R(V _A +V _th −V ₁ )+β ₄ R/2(V _A +V _t
h −V ₁ −RΔI ₂ ) | ＞1+β ₄ /2R(V _A +V _th −V ₁ )＞0 ...(23) holds, so if we introduce equation (2) into equation (20), |ΔI ₂ | ＜｜ΔI ₁ ｜/1+β ₄ /2R(V _A +V
_th −V ₁ )=｜ΔI ₁ |/1+RI ₀ /V _A +V _th −V ₁ ……(24
) becomes. The term that includes I ₀ on the right side of the inequality in equation (24) is
If I ₀ as a set value is considered constant, ΔI ₂ can be made as small as possible by (i) increasing R or (ii) decreasing (V _A + V _th − V ₁ ) (ΔI ₂ ≒ 0)
It is shown that. Therefore, even if the load current I ₁ changes, I ₂ can be held approximately constant, that is, the output voltage
Since _Vput can be kept constant, it satisfies the requirements for a low output impedance circuit. Here, since I ₂ ≈(const), the current I ₀ in the relationship expressed by equation (1) changes to the value ΔI ₂ ≒0 in equation (11), that is, ΔI ₀ ≈ΔI ₁ . This means that if the load current I ₁ is small, the current I ₀ may also be small, and as I ₁ increases, I ₀ increases to keep the output voltage V _put constant. Therefore, it is not necessary to constantly flow a large current that does not reduce the output voltage in anticipation of the maximum load current as in the conventional case as I ₀ , so that power is prevented from being wasted.

On the other hand, if the transistor 5 operates in the saturation region, I ₂ ≒ β ₅ /2 (V _io −V _put −V _th ) ² (25) holds, so the potential difference between the input voltage V _io and the output voltage V _put is Since _I2 is constant, equation (26) is constant regardless of changes in load current _I1 . Therefore, since the low output impedance circuit of the present invention also has a level shift function and an output impedance conversion function, it is extremely effective when used in the output stage of an operational amplifier.

The conventional circuit (Japanese Unexamined Patent Publication No. 51-94747) includes the circuit shown in Fig. 3. In this circuit, the transistor T ₆ is controlled and the transistor T ₇ to which the input voltage V ₆ is applied is controlled.
Controls the current I ₅ flowing into the input voltage V ₆ and the load Z ₂
The output voltage V ₅ is faithful to the input voltage V ₆ regardless of changes in the voltage, and is stable against load fluctuations.

However, in this circuit, the resistor is supplied from the power supply.
Current I ₅ through R ₂ and transistor T ₇ , current I ₆ through transistor T ₆ , current through load Z ₂
I ₄ has a relationship of I ₅ = I ₆ + I ₄ , and the current I ₅ supplied from the power supply is controlled to be constant even if the load current I ₄ changes. That is, an increase or decrease in the load current _I4 is compensated for by a decrease or increase in the current _I6 , and the sum of these, and thus the current _I5 supplied from the current, is kept constant.

In the invention shown in FIG. 2, a current I ₀ supplied from the power supply flows through the transistor T ₄ , a current I ₁ flows through the load connected to the output terminal, and a current I ₂ flows through the transistor T ₅ to which the input voltage V _io is applied. There is a relationship of I ₀ = I ₁ + I ₂ , and the current I ₂ is controlled by the transistor T ₄ to be constant. Therefore, if the load current I ₁ increases or decreases, the current I ₀ supplied from the power supply increases or decreases. When the load current increases, it is supplied from the power supply at that time. On the other hand, in the circuit of FIG. 3, it is necessary to always supply a large current I ₅ =I ₄ +I ₆ from the power supply in anticipation of the maximum load current change, and the power consumption is larger than that of FIG. 2.

Further, in the present invention, the transistor is operated in the saturated region, but it is also desirable to operate it in the saturated region in FIG. 3 (in the unsaturated state, the current I ₅ is affected by the output voltage V ₅ ). However, in FIG. 3, it is difficult to stably operate the transistor in the saturation region.
That is, in Fig. 3, to operate transistors T ₆ and T ₇ in the saturation region, V ₇ −V ₅ >V ₆ −V ₅ −Vt ₇ ……(27) V ₅ >V ₇ −Vt ₆ ……(28 ) must be satisfied. Here, Vt ₆ and Vt ₇ are threshold voltages of transistors T ₆ and T ₇ . Input voltage _V6
Since trying to keep the difference between the output voltage V 5 and the output voltage V ₅ constant is to keep the current I ₅ constant, V ₇ ≒ const ……(29). The range of input voltage V ₆ that satisfies the conditions expressed by these three equations is very narrow. In this regard, in the present invention, a level shift circuit is provided to enable transistors T ₄ and T ₅ to operate in the saturation region over a wide input range.

In the embodiment, a resistor R is used as a linear voltage generating element.
This is based on the viewpoint that the variation temperature characteristics between elements are better than those of the transistor β and V _th , and the accuracy is good. Therefore, if there is no problem in this point, the resistor R may be replaced with a transistor. Also, when using resistance R, there is a tendency that accuracy cannot be expected if the sheet resistance is increased, but in such a case, increase the initial value of I ₀ using equation (24) and reduce R by that amount. by voltage
Can maintain the accuracy of V ₄ . Further, the level shift transistor _T2 is used only when creating a potential difference between _V1 and _V2 , and in some cases, a plurality of transistors may be connected in series. If you use a transistor, you can set the shift level arbitrarily, but
This can also be replaced with another constant voltage element, such as a Zener diode. Further, in the embodiment, the voltage V ₁ is directly applied to the gate of the transistor T ₄ , but an amplifier may be used to control the gate voltage of the transistor T ₄ as α·V ₁ using its gain α. Additionally, transistors T ₁ to _{T 5}
Although all are shown as P-channel MOS transistors, they may all be N-channel MOS transistors.

As mentioned above, a linear voltage generating element is provided in a part where voltage drop is not a problem, the element generates a voltage change according to the fluctuation of the load current, and the voltage change is passed through the level shift circuit to the transistor.
According to the present invention, which feeds back to T ₄ , the power consumption of the low output impedance circuit that maintains the output voltage constant even when the load current changes can be reduced, and the power consumption of the transistors T ₄ and T 4 can be reduced over a wide voltage range. ₅ can be operated in the saturation region, and the above-mentioned operations such as keeping the input/output voltage difference constant can be performed correctly as planned.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a conventional low output impedance circuit, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a circuit diagram showing a known impedance conversion circuit. T ₁ ... p channel MOS transistor (fourth
MOS transistor), T ₂ ... p channel MOS transistor (constant voltage element), T ₃ ... p channel
MOS transistor (third MOS transistor),
T ₄ ... p channel MOS transistor (first
MOS transistor), _T5 ...p channel transistor (second MOS transistor), R...resistor (linear voltage generating element).

Claims (1)

[Claims] 1. A first MOS transistor serving as a variable constant current source, and a second MOS transistor to which an input voltage is applied to the gate.
MOS transistors are connected in series and the connection point is set as an output terminal, and the sum of the current flowing through the load connected to the output terminal and the current flowing through the second MOS transistor is supplied from the power supply through the first MOS transistor. In the low output impedance circuit configured to be from the source to the first MOS
A third MOS transistor whose level is shifted and fed back to the gate of the transistor, and a fourth MOS transistor which is connected to the source of the third MOS transistor and operates as a constant current source, The MOS transistors are of the same conductivity type and are operated in the saturation region, and the voltage applied to the gate of the first MOS transistor is varied in accordance with the change in the current flowing through the load, thereby increasing the current flowing through the second MOS transistor. A low output impedance circuit characterized by keeping the potential difference between input voltage and output voltage constant by keeping it constant regardless of changes in load current. 2. The source voltage of the third MOS transistor is changed to the source voltage of the first MOS transistor through a constant voltage element for level shifting.
2. The low output impedance circuit according to claim 1, wherein the voltage is applied to the gate of a MOS transistor.