JPH0284740A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain an insulated gate type field effect transistor wherein sheet resistance and junction leak current are reduced by backing the source.drain with silicide by a method wherein the silicide layer of the source.drain region is arranged at the part higher than the surface of an Si substrate turning to the source.drain region. CONSTITUTION:In an insulated gate type field-effect transistor, a silicide layer 16 of a source.drain region is arranged at the part higher than the surface of an Si substrate 10 turning to the source.drain region. For example, on a P-type substrate 10, an element isolation layer 11, a polysilicon gate 12, a gate oxide film 13, a gate side wall 14 and a diffusion layer 15 are formed. Next, Si is deposited in a thickness of 1000Angstrom on a sample by sputtering; Ti is deposited in a thickness of 600Angstrom without exposing the sample to the air: then annealing is performed at 600 deg.C for 30 seconds by infrared ray lamp heating; thereby obtaining silicide in N2 atmosphere. After that, in order to eliminate the silicide layer 16 on an oxide film, the silicide layer 16 is selectively etched by dry etching method after a resist mask is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same.

[Conventional technology]

With the miniaturization of semiconductor devices, it is becoming more important to make source/drain junctions shallower. However, simply lowering the energy of ion implantation during source/drain formation increases the sheet resistance and the contact resistance with the wiring material, making it difficult to increase the speed. Currently, in order to lower the sheet resistance of the source/drain and, in turn, the contact resistance, a method of lining the source/drain with a silicide material is often used (K, Tsukamot
o, T.

Okamoto, M., Shimizu, T., Mat
sukawa and H,)larada:16th
SSDM P47 (1984)).

[Problem to be solved by the invention]

Generally, in the case of a silicide-lined source/drain, although the sheet resistance decreases, it is known that the junction leakage current increases. Several factors are thought to be responsible for this. The first factor is knock-on of the metal in the silicide when ions are implanted through the silicide layer, and the second factor is the entire surface of the oxide film when forming the gate sidewall. This is due to the regression of the LOGO5 element isolation layer during etching, and the regression of the LOGO3 element isolation layer due to wet etching to remove damage at that time.The third factor is element isolation during silicide formation-81
It is thought that the points listed above 0 are the cause of junction leakage, which may be due to stress at the interface.

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, an object of the present invention is to provide an insulated gate field effect transistor that uses silicide to line the source and drain to lower sheet resistance and reduce junction leakage current, and a method for manufacturing the same.

[Means to solve the problem]

In order to achieve the above object, the semiconductor device of the present invention is an insulated gate field effect transistor in which a silicide layer for the source/drain region is provided above the surface of the Si substrate serving as the source/drain region.

The method for manufacturing a semiconductor device of the present invention includes a step of depositing two or more layers of Si and metal or silicide after forming a structure having element isolation, a gate oxide film, a gate, a diffusion layer, and a gate side wall on a substrate. , a step of siliciding the sample by annealing, a step of removing the silicided layer on the oxide film by a lithography technique and an etching method, and a step of annealing after ion implantation.

Further, the semiconductor device of the present invention includes a step of forming a structure having element isolation, a gate oxide film, a gate, a diffusion layer, and a gate sidewall on a substrate, a step of selectively growing Si on a surface other than the oxide film surface, and a step of selectively growing Si on a surface other than the oxide film surface. a step of depositing the sample, and a step of siliciding the sample by annealing,
It is obtained by a manufacturing method including a step of annealing after ion implantation.

[Effect]

Conventionally, the silicide layer-silicon interface was formed below the surface before silicide, that is, the Si substrate surface, but in the present invention, the silicide layer-silicon interface is formed in a structure in which the region to be silicided is raised above the source/drain SL surface. There is.

Conventionally, the method for forming the above structure was to deposit metal directly on the surface of the source/drain 81, but in the present invention, Si is first deposited, then metal is deposited, and then silicide is formed. is undergoing annealing. The silicided region on the oxide film is removed by etching. Alternatively, in order to prevent the reaction on the oxide film, Si is not deposited on the oxide film using selective growth, but only on the Si surface, followed by metal deposition, and then silicided by annealing. obtained by doing.

By using the above structure and manufacturing method, the p-n junction becomes effectively shallow and no silicide reaction occurs with the Si substrate, so stress at the element isolation-Si interface can be avoided. Therefore, junction leakage, which has traditionally been a serious drawback of silicide electrodes, is at the same level as that of a normal diffusion layer, and contact resistance can be lowered.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

(Example 1) FIG. 1 shows a structural diagram applied to an MO3 type transistor.

FIG. 1(a) shows an element isolation layer 11 formed on a p-type substrate 10 by the LOCO3 method. Poly-Si gate 12. A structural diagram in which a gate oxide film 13, a gate sidewall 14, and a diffusion layer 15 are formed is shown. In this example, the LOCO5 oxide film thickness is 8000, and the gate width is 0.5. a, the gate sidewall 14 is a 2,500-Si film etched over the entire surface by CVD and dry etching using CHF. The diffusion layer 15 is formed by forming the poly-Si gate 12 before forming the gate sidewall 14, and then implanting As by ion implantation to form an LDD structure of 5 x 10" ato+ng/a (with a junction depth of 0.14). And so.

Using the structure shown in FIG. 1(a) as a sample, Si was first sputter-deposited by 1000 people using a DC sputtering device under conditions of an Ar pressure of 2 mTorr and 0.4 KM. The metal was heated under the same conditions for 60 minutes without subsequently exposing the sample to the atmosphere.
0 people were deposited. Titanium was used as the metal in this example. After that, 600℃ was heated using an infrared lamp.
C. for 30 seconds, and silicidation was performed in N2. Unreacted Ti was removed with a mixture of ammonia, hydrogen peroxide, and water. FIG. 1(b) shows a structural diagram of the steps up to the formation of the silicide layer 16.

Next, since a silicidation reaction also occurs on the oxide film including the gate sidewall 14, the silicide layer 1 on the oxide film
In order to remove the silicide layer 16, after forming a resist mask, the silicide layer 16 was selectively etched by dry etching. The resist was removed using Os plasma. The gas is CF4. A mixed gas of CCQ4 was used. The obtained structure is shown in FIG. 1(c).

(Example 2) In this example, for the sample with the structure shown in FIG. 1(a), 5i17 was selectively added to 10 on only the 81 surface as shown in FIG. 1(d).
A selective growth method was used to prevent Si from growing on the oxide film. Thereafter, Ti is deposited by a 600-person sputtering method. After that, 60% by lamp heating method.
Annealing was performed in N2 at 0° C. for 30 seconds to form a silicide. Unreacted Ti was removed with a mixture of ammonia, hydrogen peroxide, and water. Therefore, the structure was the same as that of the previous embodiment as shown in FIG. 1(c), and the structure of the present invention was realized.

Above is Example 1. For the sample obtained in Example 2, 80
Annealing is performed using a lamp heating method in Ar at 0° C. for 10 seconds. As a result, Ti becomes in four stable states of Ti5Lz. After that, in order to form a junction, As was ion-implanted at 70KeV, 5X10"ato+ms/cd.
Annealing for activation was performed at 900° C. for 60 minutes in N2. A sheet resistance of 1Ω/mouth was obtained.

Note that FIGS. 2(a) and 2(b) show structural diagrams of samples in which the Ti film thickness, annealing conditions, etc. are the same, and the structure is the conventional technique, that is, Ti is directly silicided in the diffusion layer. Under these conditions, the sheet resistance was 1Ω/mouth. FIG. 2(a) is a diagram showing only the joint portions of the structure of the present invention and FIG. 2(b) is the structure of the prior art. In the structure of the present invention shown in FIG. 2(a), since the silicide layer 21 rises upward, the diffusion layer 23 formed through the silicide becomes shallower in appearance and forms the first junction, that is, the gate. The diffusion layer 22 formed in a self-aligned manner is maintained at a junction depth of 0.1-0.1 mm in the present device. However, in the conventional technique shown in FIG. 2(b), it can be seen that the bond is as deep as 0.257 m. As mentioned earlier, in order to make this junction shallow using the conventional method, if the Ti film thickness is 200 keV and the As implantation energy is 30 KeV, the sheet resistance will be 30 to 8
The resistance was as high as 0Ω/mouth, and the controllability was also poor.

In the present invention, a salicide structure is adopted in which the gate portion is also silicided, but it is also possible to cover the gate portion with an oxide film and silicide only the source/drain portions. In addition, although poly-Si was used as the gate electrode, it goes without saying that other materials can be used and the effects of the present invention are not impaired in any way.Although Ti was used in the present invention, W It goes without saying that it can also be used for commonly used silicide materials such as Mo, Ta, etc., considering the principle. When performing silicidation, a two-stage lamp heating method was used in the example, but annealing using an electric furnace was also possible. However, in the case of electric furnaces, there is also the problem of oxidation at the inlet of the electric furnace, which requires careful attention.However, in the structure and manufacturing method of the present invention, this is not a particularly essential problem. ℃～200℃
The resistance values shown in the examples could also be obtained when silicidation was performed using the following. Further, although the structure of the embodiment uses an MO5 type transistor with a Si oxide film gate, the present invention can also be applied to other than the SL oxide film gate, that is, an insulated gate type field effect transistor.

Table 1 shows the junction leakage current and sheet resistance of the MO5 type transistor prototyped by the manufacturing method of the present invention. 1 In Table 1, first, the leakage current for each component of perimeter and area for a junction that does not use silicide is 5 x 10- ”A/4
．． Although the value is low at I x 10-"A/7m", the sheet resistance is high at ~80Ω/mouth. Next, in the conventional silicide structure, even when the junction depth is <0.254, the leakage current is as high as 2XlO-"A/*, lXl0-"A/u".

Although not shown in Table 1, when the joint was closed by 0.15-1, the area component showed a high value of I x 10-1'', which is nearly 3 digits.Next, Example 1 with the structure of the present invention Both when using the method of Example 2 and when using the method of Example 2, the seek current of 5X10-" is approximately the same level as a normal seek current without silicide.
It was possible to obtain A/p, lXl0-"A/4", sheet resistance of 1 Ω/hole, and junction depth of 0.1-. In addition, almost the same value could be obtained in the case of p-Ch.

The reason for this is, as mentioned earlier, that the junction formed through silicide, that is, the metal knock-on that causes leakage current, is inside the initially formed diffusion layer (n-layer), and the junction is This is due to the fact that it is maintained by the n'''' layer. Another factor is also considered to be that the stress at the LOGO3 element isolation-Si interface does not cause the Si substrate to react, but is silicided with the later deposited Sl, so that it is considerably reduced. Another major factor is that silicide does not sneak into the LOCO8 element isolation layer.

〔Effect of the invention〕

As described above, according to the structure and manufacturing method of the present invention, it is possible to completely solve the conventional problems by forming a low resistance, shallow junction, and a low leakage current junction, and it is possible to completely solve the problems of the conventional MO3 type, which will be miniaturized in the future. This has an effect that can be widely used in transistors.

[Brief explanation of the drawing]

1(a) to 1(c) are schematic cross-sectional views showing the structure of the present invention and the manufacturing method of the first embodiment in order of steps, and FIG. 1(d) shows the main parts in the manufacturing process of the second embodiment. 2(a) and 2(b) are schematic sectional views for explaining the bonding of the diffusion layer, (a) is a structural diagram of the present invention, and (b) is a structural diagram of the conventional technology. be. 10...Substrate 11...Element isolation 12...Gate 13...Gate oxide film 14...Gate side wall 15.22...
・Diffusion layer 16.21... Silicide layer 17・
...Si23...diffusion layer (a) formed through silicide

Claims (3)

[Claims] (1) A semiconductor device in an insulated gate field effect transistor, characterized in that a silicide layer for the source/drain region is provided above the surface of the Si substrate that will become the source/drain region. (2) After forming a structure having element isolation, a gate oxide film, a gate, a diffusion layer, and gate sidewalls on a substrate, a step of depositing two or more layers of Si and metal or silicide, and silicide of the above sample by annealing. a step of removing the silicided layer on the oxide film by lithography technology and etching method, and after ion implantation,
1. A method of manufacturing a semiconductor device, comprising the step of annealing. (3) A step of forming a structure having element isolation, a gate oxide film, a gate, a diffusion layer, and a gate sidewall on the substrate, a step of selectively growing Si on a surface other than the oxide film surface, and a step of depositing metal or silicide. A method for manufacturing a semiconductor device, comprising the steps of: siliciding the sample by annealing; and annealing after ion implantation.