JPH0281245A - Multiplexing system for cache memory - Google Patents

Abstract

PURPOSE:To prevent the function of a cache memory from being lost immediately even if an error is generated in the cache memory, and to improve the reliability of the whole system by multiplexing the cache memory and switching it successively. CONSTITUTION:For instance, in a tag memory 10, tag data containing a tag entry address, etc., is stored, and a cache RAM 20 is constituted of four pieces of bank A 21, bank B 22, bank C 23 and bank D 24. Also, to all the banks, necessary data is transferred in advance. In such a way, even if an error is generated in one piece of bank of the cache memory, the function of the cache memory does not stop by switching the bank successively, its function is fulfilled, and the reliability of the whole system is improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a cache memory multiplexing method used in a microprocessor system such as a numerical control device, and particularly to a cache memory multiplexing method in which the cache memory is divided into banks. Regarding.

[Prior Art] In control devices such as numerical control devices and robot control devices, between a high-speed processor and a slow, large-capacity main memory,
A cache memory is provided to process data at high speed.

Generally, a large-capacity DRAM is used as the main memory, and an SRAM is used as the cache memory. Main memory is slow, but has a large capacity per chip and is cheap, while cache memory is fast, but
The capacity per chip is small and the cost is high. Therefore,
By taking these advantages and disadvantages into consideration, by using a cache memory, the processing power of a processor can be increased and a low-cost microprocessor system can be constructed.

[Problem to be solved by the invention]

However, because cache memory is fast, there is a higher possibility of errors occurring than in main memory.

When an error such as a parity error occurs in the cache memory, the data or program to be processed must be processed in the main memory instead of being transferred to the cache memory, reducing the processing speed of the entire system and reducing the processing speed of the numerical control device. If there are many tasks that need to be processed in real time, the system will effectively go down.

The present invention has been made in view of these points, and it is an object of the present invention to provide a cache memory multiplexing system in which the cache memory is divided into banks.

[Means to solve the problem]

In order to solve the above problems, the present invention uses a cache memory multiplexing method that stores data from the main memory and processes the data at high speed.The present invention divides the cache memory into multiple banks and stores all the necessary data. A cache memory multiplexing method is characterized in that cache memory is stored in banks and multiplexed so that when an error occurs in one bank, the next bank can be used.
provided.

[Effect]

Cache memory is divided into banks and necessary data is transferred to all banks. Even if an error occurs in one bank, the cache memory can be used as is by switching to another bank. .

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 2 shows a block diagram of a microprocessor system implementing the cache memory multiplexing scheme of the present invention. Microprocessors 1 and 2 are coupled to system bus 6 through cache units 3 and 4, respectively.

Since system bus 6 is used by multiple microprocessors 1 and 2, use of system bus 6 is arbitrated by system bus controller 5.

The main memory 7 is composed of a DRAM, and its data is transferred to the cache units 3 and 4, processed by the microprocessors 1 and 2, and returned to the main memory 7, or the processed data is transferred to the system bus 6. is transferred to l108 connected to.

FIG. 1 shows a configuration diagram of a cache unit used in the cache memory multiplexing method of the present invention.

Tag memory 10 stores tag data including tag entry addresses and the like. Cache RAM 20 is 4
Bank A2, L bank B22, bank C23, and bank D24.

For example, if the tag memory 10 has 512 entries x 4 sets and the cache RAM has 8 words, the total number of tag entries is 2 words, and the capacity of the cache RAM 20 is four times that of 4. By dividing into banks, it is possible to make it quadruple.

Initially, bank A21 is used. When bank A21 becomes inoperable due to a parity error, etc., tag memory 1
The tag of 0 is rewritten and the bank is switched to bank B22, and when an error occurs in bank B22, the bank is sequentially switched to bank C23. Of course, when the switching reaches bank D24 and an error occurs, the cache memory is deemed unusable and stopped.

In this way, by multiplexing the cache memory, even if an error occurs in one bank of the cache memory, by sequentially switching banks, the function of the cache memory will not stop and its function will continue. This will improve the reliability of the entire system.

〔Effect of the invention〕

As explained above, in the present invention, the cache memory is multiplexed and switched sequentially, so even if an error occurs in the cache memory, the function of the cache memory is not immediately lost, and the reliability of the entire system is improved. Improves sex.

7・----1・−・−・−・Main memory 10−・・
−・−・・・−・−Tag memory 20・−・−・−・−・
- Catshu RAM patent applicant FANUC Co., Ltd. agent Patent attorney Takeshi Hattori

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a cache unit used in the cache memory multiplexing method of the present invention, and FIG. 2 is a block diagram of a microprocessor system implementing the cache memory multiplexing method of the present invention. 1.2・・−・−・・−・・Processor 3.4−・・−
−−−1−−・−・Cache unit 5・・−−−
−−−−−−−1・System bus controller 6...
−・−・・・・・・・・・System bus diagram 2

Claims (2)

[Claims] (1) In a cache memory multiplexing method that stores data from the main memory and performs data processing at high speed, the cache memory is divided into multiple banks, the necessary data is stored in all banks, and one A cache memory multiplexing method characterized by multiplexing so that when an error occurs in a bank, the next bank can be used. (2) The cache memory multiplexing system according to claim 1, wherein the switching of the banks is performed by changing the contents of the tag memory.