JPH0278967A - Period measuring circuit - Google Patents

Abstract

PURPOSE:To accurately measure the length of one period by performing counting operation equivalent to the length of each wave by a counting means, comparing last and current counting results in 1st and 2nd holding means with each other, and detecting the transition of counted values with time. CONSTITUTION:An input signal (a) is processed by a waveform shaping circuit 11 into a signal (b) converted so as to become a pulse, which is supplied to a one-shot circuit 12 and an AND gate 13. The circuit 12 generates a signal c' and an inverted signal (c) is synchronism with the pulse falling of the signal (b), and supplies the signal (c) to latch circuits 16 and 17 and the signal c' to the counter 15. The counted value signal of the counter 15 is latched by the circuit 16 at the rise of the signal (c) and the counted value signal which is latched by the circuit 16 is latched by the circuit 17 at the rise of the signal (c). The counted value signals which are latched by the circuits 16 and 17 are compared by a comparing circuit 18 with each other and the result is outputted to an FF 19. A signal (f) is inputted to a counter 6 through an FF 2 and an AND gate 5. The counted value of the counter 6 indicates one period and an accurate measurement is taken.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention provides a method for forming one cycle by gradually decreasing the wavelength of each wave of an input signal from the maximum and returning to the maximum again. Or, the period of a so-called repetitive signal in which the wavelength of each wave of the input signal gradually decreases from the maximum, reaches the minimum, increases gradually, and returns to the single wave with the maximum wavelength, forming one cycle (the above-mentioned period). The present invention relates to a period measuring circuit used when measuring one period).

(Prior art) In conventional sterilization measuring circuits, the input signal is divided appropriately using a gate signal corresponding to a period of -1, so that the frequency is reduced by one.
. However, this conventional period measuring circuit has a problem in that highly accurate measurement cannot be performed due to a shift in the phase relationship between the gate signal and the input signal, and the circuit becomes complicated to correct this.

(Problem to be Solved by the Invention) As mentioned above, in the conventional period measuring circuit, the input signal is appropriately divided by the gate signal corresponding to the - period and the frequency is counted. A problem arises in that a shift in phase relationship becomes a problem, and the circuit required to correct this becomes complicated.

The present invention was made to solve the problems of the conventional period measuring circuit, and its purpose is to reduce the period of the so-called carry-back signal to l! With a medium composition! An object of the present invention is to provide a period measuring circuit that can quickly measure the period.

[Configuration of the Invention (Means for Solving the Problems)] In the present invention, the hl number means performs 91 numbers corresponding to the approximation of one wave of input signals, and the δ1 actually obtained by the hi number means A first holding means for holding and covering the counting result, a second holding means for holding the counting result obtained last time by the counting means, and a cutting means held by the first and second holding means. The period measuring circuit is provided with a period length determining means for comparing the numerical values and determining the length of one cycle based on the change in the comparison result.

(Function) According to the u4 configuration above, when the input signal is a repeating signal, when the - period is exceeded, the wavelength of one wave necessarily transitions from the maximum to the shortest one, so the counting means successively corresponds to the wavelength of one wave. do. i+fi is 1! ′? If the numerical values are held in the first and second holding means and compared and their changes over time are monitored by the period length determining means, then the wavelength will always be the maximum. It is possible to detect the above transition from short to short and determine one period.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a block [1] of a period measuring circuit according to an embodiment of the present invention.
This is a diagram. In the figure, reference numeral 1 denotes a trigger circuit that changes the signal level (here, to 1 level) when the wavelength of one wave of the input signal a becomes shorter than the wavelength of the previous wave. This trigger circuit 1 includes a waveform shaping circuit 11, which converts a sine wave input signal a as shown in FIG. 2 into a pulse from the inflection point to the next inflection point, including the mountain side part Obtain the signal converted as follows. This signal is applied to a one-shot multivibrator (referred to as a one-shot circuit) 12 and an AND gate 13. The one-shot circuit 12 generates a signal C and its inverted signal C as shown in FIG. 2, which fall with a predetermined width in synchronization with the fall of the pulse of the signal S. The signal C is applied to the clock terminal of the latch circuit 10.17, and the signal C is applied to the clock terminal of the counter 15 and the flip-flop 19. The AND gate 13 becomes open when a pulse is generated in the signal and prevents the clock output from the clock generation circuit 14 from passing through. As a result, a clock d corresponding to the pulse width of the signal S is output from the AND gate 13 and is applied to the clock terminal of the counter 15. Here,
The clock generated by clock generation circuit 14 has a frequency sufficient to identify the pulse width of each pulse of the signal. The counter 15 receives the signal σ whenever the pulse of the signal S falls.
is cleared by becoming Trubel. The count value signal of the counter 15 is latched by the latch circuit 16 at the rising edge of the signal C. Further, the count value signal latched by the latch circuit 16 is latched by the latch circuit 17 at the rising edge of the signal C.

Therefore, in the latch circuit 16, the counter 15 is actually 51.
I counted. ? 1 numerical signal is latched, and the l numerical signal which the counter 16 counted the previous time is latched into the latch circuit 11.

The count value signals latched by the latch circuits 16 and 17 are provided to the comparator circuit 18, and their magnitudes are compared. Comparison circuit 1
8 applies a Torbel signal to the input terminal of the flip-flop 19 if the count value signal of the latch circuit 16 is higher than the count value signal of the latch circuit 17; The Noritsubu flop 19 receives the output signal of the comparison circuit 18 at the rising edge of the signal and applies it to the clock terminal of the flip-flop 2 as a take-in signal f. The flip-flop 2 takes in the output signal of the flip-flop 3 and outputs it as a signal at the rising edge of the signal f. When the start signal q given by operating a switch or the like (not shown) rises, the flip-flop 3 converts its output into a torque signal and supplies it to the input terminal of the flip-flop 2 since Vcc is given to the input terminal. It is reset when becomes set state. The output (qgh) of the flip-flop 2 is given to the AND gate 5, which passes the clock output from the clock generation circuit 4 during the period in which the output signal is Torbel and supplies it to the counter 6. Generate a clock with the frequency necessary to change the period by 1-Tj.Counter 6G and gate 5
It is incremented by the clock that arrives via @.

In this manner, an input signal (gE), which is a repetitive signal as shown in FIG. Suppose that Then, the flip-flop 3 goes into the LEF1~ state, and the Trubel signal is given to the input terminal of the Noritsubu flop 2. However, since the output signal r of the trigger circuit 1 remains at Trubel, the Noritsubu flop Since the output signal of 2 is at the 1- level, the AND gate 5 is not heard. The pulse width of each pulse of the signal output from the waveform shaping circuit 11 corresponding to the wavelength of each wave of the input signal a is shown in FIG.
If you repeat the gradual decrease and increase as "4", "6", and "8", it will become 16.
When the pulse b1 of the signal S is output from the waveform shaping circuit 11, the AND gate 13 outputs a clock d1 corresponding to the pulse width of the pulse b1 to the counter 15. Note that, before this, the counter 15 has been cleared at the falling edge of the signals output from the one-shot circuits 1 to 12.

The count value signal of the clock d1 is held in the output 1 counter 15, and then the signal C rises when the pulse b1 of the signal S falls, and the 51 value signal of the clock d1 is latched to the wrap circuit 1G. Clock d that was already latched in circuit 16. The reduction value signal of is latched, and the counter 15 is cleared when the signal @6 becomes the torque level. As a result, the comparator circuit 18 compares the count value signals corresponding to the clock d0 and the clock d1, and the latch signal of the latch circuit 16 (corresponding to the clock d1) becomes the latch signal of the latch circuit 17 (corresponding to the clock d0). .

Next, pulse b2 arrives and counter 15 clocks d
A count of 2 is performed, and a clock d2 is applied to the latch circuit 1G.
The count value signal corresponding to the clock d is latched, and the latch circuit 17 latches the 31 value signal corresponding to the clock d.

In the comparison by the comparison circuit 18 at this time, the latch circuit 1
The wrap signal of 6 becomes smaller than the latch signal of the latch circuit 17, and the output signal of the comparison circuit 18 transitions to the trubel.

This is taken into the flip-flop 1 and 9 at the rising edge of the signal C, so the signal f' transitions to l-level, and the flip-flop 2 is also set, so the signal jiffih becomes 1.
(The level is reached and AND gate 5 is heard, counter 6
is incremented by the clock provided from the clock generation circuit 4.

Thereafter, the latch signal of the error latch circuit 16 becomes smaller than the latch signal of the latch circuit 17 due to the pulse b3, and the output signal of the comparator circuit 18 exhibits a torque level, and the latch signal of the latch circuit 16 becomes smaller than the latch signal of the latch circuit 17 due to the pulse b4. The latch signal of the latch circuit 16 becomes larger than the latch signal of the latch circuit 17 due to pulse b5, and the output signal of the comparator circuit 18 exhibits a torque level. The latch signal of 16 becomes smaller than the latch signal of latch circuit 17, and the output signal of comparison circuit 18 changes to 1-level.

The output signal of the comparator circuit 18 that has changed in this way is the signal C.
The output signal f is taken into the flip-flop 19 at the rising edge of the clock d4, and the output signal f falls after the clock d4.
After counting 6, it rises again and becomes a trubel. on the other hand,
Flip-flop 2 is set at the first rising edge of signal Qj and re-hit at the next rising edge, so its output signal remains - from the rising edge of signal 1' until it rises again.
Therefore, after the output signal of the comparator circuit 18 becomes the torque level due to the pulse b2, the output signal of the comparison circuit 16 is maintained at the torque level until the output signal of the comparison circuit 16 becomes the same level due to the pulse b6 one cycle later. As a result, during one cycle 11A shown in FIG. It can be seen that the value shown below is obtained.

In this embodiment, considering that when the input signal @a exceeds one full cycle, the wavelength of that one wave (from one trough of the sine wave to the next trough) always changes from large to small, the length relationship of the wavelength is Since the values are replaced with the old values, it is possible to repeatedly accurately measure the brightness of the 15th month.

[Effect of the Invention 1] As explained above, according to the present invention, as long as the incoming horn signal is a repetitive signal, the wavelength of one wave will necessarily overflow from the maximum to the shortest one when the - period is exceeded. perform 51 numbers corresponding to the length of each wave, and hold the previous and current 84 number results in first and second holding means;
Comparing these, the tl number fi+: The size of i is -
It is possible to detect that the wavelength of the wave corresponds to the 4-dimensional repetition, and based on this, it is possible to measure one round with high precision with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a period measuring circuit according to an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation of the embodiment shown in FIG. 1...1-Riga circuit 2, 3.19...Flip-flop 4.14...Clock generation circuit 6.15...Counter 11...Waveform shaping circuit 12
...1 Non-shot circuit 16, 17...Latch circuit 18...Comparison circuit Agent Patent attorney Nori Chika Ken Yudo Sanno −

Claims (1)

[Claims] A counting means that performs counting corresponding to the length of one wave of an input signal, a first holding means that holds the counting result currently obtained by the counting means, and a counting result obtained last time by the counting means. and period length determining means that compares the count values held by the first and second holding means and determines the length of one period based on the change over time of the comparison result. A period measurement circuit characterized by comprising: