JPH0276048A - Disk cache control system - Google Patents

Abstract

PURPOSE:To prevent a reading data part from being unreadable even when an error is generated in a preceding reading data part by reading only the instructed reading data without executing preceding reading when the address space of reading subject data includes a part to be coincident with an error address space up to preceding operation. CONSTITUTION:When one part of the address space in the reading subject data is coincident with the error address space, which is detected until the preceding operation, at least, a disk cache control unit (DCCU) 14 executes the reading of only the data part, which is read and instructed by a from a software, by an external memory device 13 without executing the preceding reading. Thus, when there is no error in the data part to be instructed from the software and there is the error in the preceding reading data part, the reading concerning the reading data part not to have any error is normally executed.

Description

[Detailed Description of the Invention] [Summary] Regarding a disk cache control method in which read instruction data is read from an external storage device along with its pre-read data and stored in a cache memory, even if an error occurs in the pre-read data part, the software The purpose is to improve the reliability of disk cache control by preventing the instructed read data portion from becoming unreadable,
In a disk cache control method that controls reading data instructed by the software that controls the system and its pre-read data as data to be read from an external storage device and storing it in the cache memory, the data to be read from the external storage device is When an error occurs, the address space of the data to be read is stored as an error address space, and if the address space of the data to be read includes a part that matches the error address space up to the previous time, an instruction is issued without pre-reading. The configuration is configured so that only read data that has been read is read.

[Industrial application field]

The present invention relates to a disk cache control method that controls reading data instructed by software that controls a system, together with its pre-read data portion, from an external storage device such as a disk device and storing it in a cache memory.

[Conventional technology]

In recent years, with the demand for faster processing systems, there has been a demand for improved performance of disk devices in order to increase data reading speed. As one means for achieving this, a disk cache control method is used in which a cache memory is provided between a disk device and a soft memory in which software for controlling the system is stored to speed up data access.

In this disk cache control method, in order to improve access efficiency, prefetch processing is performed by taking advantage of the fact that programs have local referentiality. Read-ahead processing is a process in which when a disk device is instructed to read data, data several times more than the actual amount of data (byte count value) instructed to be read is read from the disk device and stored in the cache memory. This can speed up reading. In other words, the access time of a disk device consists of seek time, rotational wait time, and data transfer time, and the seek time and rotational wait time are several times larger than the data transfer time (for example, the seek time is 10-odd ms). , the rotational latency is about 8 ms, while the data transfer rate is 1 to 2 KB/ms). Therefore, if read-ahead processing is performed, the read-ahead portion will be accessed more often due to the local reference nature of the program, and the read-ahead portion only takes data transfer time when there is a read instruction from software. Therefore, access can be made several times faster than when no read-ahead processing is performed.

Problems to be Solved by the Invention C] The disk cache control method that performs pre-read processing can speed up access to read data as described above.

However, if there is an error in the read-ahead data part due to a media error, etc., error recovery processing is performed, and if the error is not recovered, it is generally difficult to determine the part where the error occurred, so the read instruction data and the read-ahead data are The entire file is considered unreadable. For this reason, there is a problem in that even if there is no error in the read instruction data part, the data cannot be read.

For example, S CS I (Small Compute
In intelligent disk cache control devices that are connected via interfaces such as ER System Interface), error processing such as retries is performed on the disk side, so if an error occurs, the disk cache side cannot perform recovery processing. The situation is impossible. In a disk cache control device, even if a medium error occurs in the pre-read data portion of the disk device, it is difficult to determine whether the error occurred in the data portion that was instructed to be read by the software or in the pre-read data portion. Therefore, even if an error occurs in the pre-read data part, if it cannot be recovered by retrying, it is reported as a normal software error. When the software is notified of a software error, it usually retries to recover from the error, but if the medium error is already such that retry is not possible, as in 5cSI, the reading instruction data itself cannot be read even if there is no error. This was an inconvenience.

In this way, data that should normally be read cannot be read by software, resulting in a problem of lower system reliability and lower processing efficiency.

The present invention provides an improved disk cache control method that improves the reliability of disk cache control by preventing the read instruction data part required by software from becoming unreadable even if an error occurs during pre-reading. The purpose is to

[Means to solve the problem]

The means adopted by the present invention to solve the above-mentioned problems are as follows:
This will be explained with reference to the principle diagram shown in FIG.

In FIG. 1, reference numeral 11 denotes a software memory in which software for controlling the system is stored.

A cache memory 12 stores data read from an external storage device.

Reference numeral 13 denotes an external storage device, which is composed of a disk device and the like, and stores various data.

Reference numeral 14 denotes a disk cache control unit (hereinafter referred to as DCCU), which uses the read data instructed by the software and its pre-read data portion as data to be read, and detects that an error has occurred in the data to be read from the external storage device 13. Sometimes, an error address space storage unit (hereinafter referred to as EASR) 141 is provided to store the address space of data to be read as an error address space, and performs disk cache control. If the read data instructed by the software and the address space of its pre-read data include a portion that matches the previously detected error address space, the data portion instructed to be read by the software without pre-reading. Control is performed to read only the data from the external storage device 13.

Note that the soft memory 11 and the cache memory 12 are provided within a host (not shown), but the DCCU 14 is provided within the host or as an independent device outside the host.

The disk cache control method of the present invention is implemented by the system shown in FIG. 1, and is configured as follows.

That is, in a disk cache control method that controls reading data instructed by software that controls the system and its pre-read data portion as read target data from the external storage device 13 and storing it in the cache memory 12, (A) external storage When an error occurs in the data to be read read by the device 13, the address space of the data to be read is stored as an error address space, and (B) the address space of the data to be read is the previously detected error address space. If the data contains a portion that matches the above, only the read data portion instructed by the software is read from the external storage device 13 without pre-reading.

[For production]

The operation of the present invention, that is, the operation of the implementation system shown in FIG.
The process steps will be explained with reference to the disk cache control process flowchart of FIG.

■ Processing S1 The software in the software memory 11 is the DCC
It instructs tJ14 to read data (actually, the instruction is given in accordance with software read out from the soft memory 11 by a processor (not shown), but for simplicity, it is referred to this way).

■ Processing 52 The DCCU14 uses the read data instructed by the software and its pre-read data portion as the read target data, and selects the part where the address space of the read target data matches the error address space detected when reading the read target data up to the previous time. Determine if there is. The previously detected error address spaces are stored and held in the EASR 141.

■ Processing 53 When at least part of the address space of the data to be read matches the previously detected error address space, the DCCU 1, 4 instructs the software to read from the external storage device 13 without pre-reading. Read only the data part that has been updated.

As a result, if there is no error in the read data portion instructed by the software and there is an error in the pre-read data portion, the read data portion without errors is normally read.

(2) Processing S4 In processing S2, if the address space of the data to be read and the error address space do not match, the data to be read can be read, so the DCCU 14 reads the data to be read from the external storage device 13.

In this case, if there is no error in the data to be read read from the external storage device 13, the data to be read is transferred to and stored in the cache memory 12.

If an error occurs in the read target data, the DCCU 14 uses the address space of the read target data as an error address space, stores the address information in the EASR 141, and notifies the higher-level software.

When the software performs a retry upon receiving this notification, the aforementioned processes S to S3 are performed, and only the read data portion instructed by the software is read.

In addition, in process S2, it is practically sufficient that the previous error address space to be compared with the address space of the data to be read this time is one error address space detected last time. A plurality of error address spaces detected in the error address spaces may be compared.

As explained above, if there is a part where the read target data address matches the error address space, read ahead is not performed and only the data instructed by the software is read. Even if an error occurs, it is possible to prevent data portions required by software from becoming unreadable.

This ensures that reading is possible if there are no errors in the data specified by the software.
The reliability of the disk cache control device can be improved and the processing efficiency of the system can be improved. Furthermore, by setting the address space of the data to be read and the error address space to be compared with a plurality of error address spaces in the past, it is possible to more reliably detect whether an error exists in the address space of the data to be read. Can be done.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. 3 and 4. FIG. 3 is an explanatory diagram of the configuration of an implementation system according to an embodiment of the present invention, and FIG. 4 is a processing flowchart of an embodiment of the present invention. In the following embodiment, it is assumed that the external storage device is a disk device.

(A) Configuration of implementation system In FIG. 3, soft memory 11. Cache memory 12. External storage device 13. Disk cache 'M control unit (DCCU) 14 and error address space storage unit (E
ASR) 141 is as explained in FIG. 1o is a host in which a soft memory 11 and a cache memory 12 are provided.

In the software memory 11, CAW is a channel
Channel Address Word
rd) and the channel command word (Channel
The address of the Command Word (hereinafter referred to as CCW) is stored. The CCW contains commands to be executed on the external storage device 14, which is an input/output device, for example,
Type of operation to be executed, type of external storage device, address information of read data, length of read data, cache memory 12 or software memory 11 to which data is transferred
address etc. are specified. DATA is a data area where read data is stored.

In the cache memory 12, B L OCK (1
1 to BLOCK (e) are data storage units, and the data to be read consisting of the read data instructed by the software and its pre-read data portion is stored in this BLOCK.
transferred in units.

The external storage device 13 is composed of a disk device, and the RDAT
A is read data instructed by software, PFD
ATA is the pre-read data part.

0BDATA is data to be read including both.

ER is a location where an error occurs due to a media defect or the like.

In EASR141 of DCCU14, 5AD1 and FADI are the previously detected error address space (
These are the start and end addresses of ESA (hereinafter referred to as ESA),
5ADz and FADz are the start and end addresses of the error address space (hereinafter referred to as ESA2) detected two times before.

The DCCU 14 may be provided within the host 10, but in this embodiment, it is provided separately from the host IO as shown.

(B) Operation of the Embodiment The operation of the implementation system of FIG. 3, that is, the disk cache control operation of the embodiment of the present invention, will be explained according to its processing steps with reference to the processing flowchart of FIG. 4. In the following embodiments, the address space of the data to be read is the error address space ESA detected twice in the past.

and ESA! shall be compared with Further, in FIG. 4, the contents of the processes 81 to S are as explained in FIG. , S 41 = S 44 indicates the internal processing of processing S4. Note that, as described above, the external storage device 13 is
Assume that it is a disk device (hereinafter referred to by the same reference numeral 13).

■ Processing S1 The software in the soft memory 11 is
Instructs to read data.

The DCCU 14 takes out the CAW from the soft memory 11. Furthermore, the CCW of the specified address is retrieved from the soft memory 11, and disk cache control is started according to the instruction. CCW contains read data RD.
The cylinder address of ATA, the byte count value of its data length, and pre-read data PFDATA are specified.

■ Processing 521 When starting a read command to the disk device 13, the DCC'U 14 reads the address space of the data to be read 0BDATA (hereinafter referred to as 0BA) instructed by the CCW of the software.
(denoted by S) matches the previously detected error address space RAS.

First, the last address of the address space 0BAS of the data to be read (already shown below) is stored in the EASRI41, and the error address space RAS detected last time is stored in the EASRI41.
, the starting address SAD of , is smaller than, i.e., b
< Determine whether S A D I.

The final address b of the data to be read 0BDATA is obtained from the following equation.

b = a + (byte count of read data RDATA) + (data length of pre-read data PFDATA) When b < S A D + holds, the address space 0BAS of the data to be read matches the previous error address space ESAI. Since the part does not exist, further processing is performed to determine whether there is a part that matches the error address space E S A 2 from the time before the previous time (processes S0 and 5 described later).
24) is performed.

■ Processing SZZ Next, the DCCU 14 reads the start address of the address space 0BAS of the data to be read, that is, the read data RDAT.
The first address of A (hereinafter referred to as a) is EASR141
The final address FAD of the error address space RA S r stored in is greater than or equal to a >
It is determined whether F A D +.

When a > F A D + holds true, there is no part in the address space 0BAS of the data to be read that matches the previous error address space RAS, so it further matches the error address space E S A z from the time before the previous one. Determine whether there is a part (processing SK+ and 52 described later)
4) is performed.

■ Processing S.

b<SAD does not hold in process S21, and process S2
If a>FAD+ does not hold in □, there is a portion in 0BAS of the address space of the data to be read that matches the previous error address space E A S I .

Therefore, if the entire read target data 0BDATA is read, it will be notified that reading is not possible, so the DC
CU1'4 does not perform pre-reading and sends the read data RDAT specified by the software CCW to the disk device 13.
Instructs to read only part A.

As a result, there is no error in the read data RDATA part instructed by the software, and the pre-read data PFDA
If there is an error in the TA portion, reading of the error-free read data RDATA portion is performed normally. In this case, the process of reading directly from the disk device 13 to the software memory 11 without going through the cache memory 12 is performed.

■ Processing 5i13 In both processing SKI and S2□, if it is determined that there is no part where the address space 0BAS of the data to be read matches the previous error address space EAS, then the error address detected two times before Space E
It is determined whether there is a portion that matches AS2.

First, in the same manner as in processing SK+, the final address b of the address space 0BAS of the data to be read is set to EASR14.
The previous error address space E A stored in 1
It is determined whether it is smaller than the first address 5ADZ of Sz, that is, b<5ADz.

When b<5AD2 holds true, the address space 0BAS of the data to be read contains the error address space E from the time before the previous one.
Since there is no matching part with SA2 and there is no problem in pre-reading, the pre-reading process S41, which will be described later, is carried out.
"" S44 is performed.

■ Processing SZa Next, the DCCUI4 determines that the start address a of the address space 0BAS of the data to be read is, similar to processing S2□.
Error address space E stored in EASR141
A S 2 final address FAD.

It is determined whether a>FADz.

When a>FADz holds true, the address space 0BAS of the data to be read contains the error address space E from the time before the previous one.
Since there is no part that matches ASt and there is no problem in pre-reading, pre-reading processes Sal to S44, which will be described later, are performed.

■ Process S3 If b < S A D t does not hold in process S23, and a > FADt does not hold in process Sta, the address space 0BAS of the data to be read matches the error address space E A S 2 from the previous time. Part exists.

Therefore, in this case as well, the data to be read is 0BDATA.
If the entire data is read, it will be notified that the data cannot be read, so the DCCUI 4 does not perform pre-reading and instructs the disk device 13 to read only the read data RDATA portion specified by the CCW of the software.

As a result, there is no error in the read data RDATA part instructed by the software, and the pre-read data PFDA
If there is an error in the TA portion, reading of the error-free read data RDATA portion is performed normally. In this case, the process of reading data directly from the disk device 13 to the soft memory 11 without going through the cache memory 12 is performed.

■ Processing S 41 "S 44 In both processing S!3 and S24, if there is no part where the address space ○BAS of the data to be read matches the error address space EAS! of the previous time, the above-mentioned processing SZ+ and S2 have already been carried out. Since it is known from □ that there is no part that matches the previous error address space RASI, the DCCUI 4 instructs the disk device 13 to read 0BDATA of the data to be read (processing S4). Read target data 0BD
Process S4 to determine whether or not there is an error in the ATA
□), if there is no error, the data to be read is 0.
BDATA is transferred to and stored in a designated block (BL OCK (assumed 11)) on the cache memory 12 (processing 543).

If an error exists (ER point in the pre-read data PFDATA of the disk device 13), the DCCU 14 stores the start address a and the end address b of the read target data 0BDATA where the error has occurred in the EASR 141, and makes it impossible for the software to read it. (processing 544)
.

The software will try if it is notified that it cannot read. As a result, the above-described processes S to S3 are repeated, and only the instructed read data RDATA is read.

As described above, the address space 0BAS of the data to be read is converted into the error address space EAS and EA detected in the past two times.
Although the embodiment has been described in which the error address space is compared with S, the present invention is also applicable to the case where the error address space to be compared is the past number of times and the case where there are more than two times.

〔Effect of the invention〕

As explained above, according to the present invention, the following effects can be obtained.

(1) If there is a part where the data address to be read matches the error address space, do not read ahead;
Since only the data instructed by the software is read, even if an error occurs in the pre-read data part, it is possible to prevent the data part required by the software from becoming unreadable.

(2) According to (1) above, reading is always possible if there is no error in the data part specified by the software, so the reliability of the disk cache control device is improved and the processing efficiency of the system is improved. Can be done.

(3) By setting the address space of the data to be read and the error address space to be compared with the address space of multiple errors in the past, it is possible to more reliably detect whether an error exists in the address space of the data to be read. be able to.

[Brief explanation of the drawing]

FIG. 1 is a diagram of the principle of the present invention. FIG. 2 is a flowchart of disk cache control processing of the present invention. FIG. 3 is an explanatory diagram of the configuration of an implementation system of the present invention. 2 is a flowchart of a disk cache control process according to an embodiment. 1 and 3, 11... soft memory, 12... cache memory, 13... external storage device or disk device, 14...
- Disk cache control device 1.141...Error address space storage unit (EASR). Non-topping Q Hara Tomoe Figure 1 Impossibility ii [a Purple! Wholesale of Skayayan Yuya 1 (1 mile pro valley - 2nd figure to the credit size e product' 3rd figure how to get 7 I prayer 1's diizuku 'f,'/>> rume town number ξ logic flow Dessert Figure 4

Claims (1)

[Claims] 1. A disk that controls reading data instructed by software that controls the system and its pre-read data portion as data to be read from an external storage device (13) and storing it in a cache memory (12). In the cache control method, (A) when an error occurs in the data to be read read from the external storage device (13), the address space of the data to be read is stored as an error address space; (B) the data to be read is When the address space of contains a portion that matches the previously detected error address space, read only the read data portion instructed by the software from the external storage device (13) without performing pre-reading. Characteristic disk cache control method. 2. The disk cache control according to claim 1, wherein the previously detected error address spaces compared with the address space of the data to be read are a plurality of past error address spaces starting from the previous time. method.