JPH0274076A - Mos type transistor - Google Patents

Abstract

PURPOSE:Not only to enable the improvement of a MOS type transistor of this design in breakdown strength and the reduction of a leakage current but also to make it low in resistance to an on-current by a method wherein an insulating film whose dielectric constant is higher than that of a gate insulating film is provided between a second high resistive semiconductor region and a gate electrode. CONSTITUTION:A second high resistive semiconductor region 8 (offset section) is provided between first high resistive semiconductor regions 5 and 6 under a gate electrode 4 and a low resistive semiconductor region 7a of a channel region 7, and an insulating film 9, whose dielectric constant is higher than that of a gate insulating film 3, is provided between the offset section 8 and the gate electrode 4. Therefore, when a transistor is ON, the insulating film 9 of high dielectric constant functions as a parasitic MOS and the offset section 8 changes to the same conductivity type as the source and the drain region, 5 and 6. Therefore, the resistance of the offset section 8 is made to decrease with the rise of a gate voltage, in result, an ON-current is not restricted by the resistance of the offset section 8. When the transistor is OFF, as it is of offset gate structure, the electric field of a P-N<+> junction is not intensified by a gate voltage, so that the transistor is improved in breakdown strength and a leakage current is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a MOS type transistor, and particularly to a MOS type transistor having a so-called offset gate structure in which the gate position is separated from at least a drain region.

[Summary of the invention]

The present invention provides a MOS transistor with an offset gate structure, which includes a second high-resistance semiconductor region between a high-resistance semiconductor region and a low-resistance semiconductor region in a portion l below a gate electrode, and wherein the second high-resistance semiconductor region By configuring an insulating film with a higher MN ratio than the gate insulating film between the semiconductor region and the gate electrode, breakdown voltage can be improved and leakage 'T! This is intended to reduce the L current and also to lower the resistance to on-current.

[Conventional technology]

Recently, in MOS transistors such as thin film transistors, in order to improve breakdown voltage and reduce leakage current,
As shown in FIG. 3, a so-called offset gate structure has been proposed in which the gate position is separated from at least the drain region.

The MO5 type transistor with an offset gate structure shown in the figure is an N-channel type 'iR# transistor, and for example, an active layer (22) made of a polycrystalline silicon thin film is formed on a SiO□ insulating substrate (21). , a source region (23) and a drain region (
A gate insulating film (25) made of SiO□ and a gate electrode (26) made of polycrystalline silicon are placed at a position away from
) is formed, and a 5iOt layer (27
) is deposited, and a source voltage i (
2B) and drain if! 1 (29) are ohmically connected.

[Problem to be solved by the invention]

However, M with conventional offset gate structure
In an OS type transistor, the source region (23) and drain region (24) do not overlap with the gate, so that part (hereinafter simply referred to as the offset part)
(30) becomes resistance. The larger this resistance is, the better it is in terms of improving withstand voltage and reducing leakage current.
There is a disadvantage that the resistor limits the on-current when the transistor is turned on.

There is no way to suppress the limitation of on-current while maintaining both of these characteristics, that is, improving withstand voltage and reducing leakage current.The only way is to control the resistance of the offset part (30) to the optimum value There is a method to do this, but the method of manufacturing the transistor is extremely difficult.

The present invention has been made in view of the above points, and its purpose is to suppress the limitation of on-current while maintaining the characteristics of improving withstand voltage and reducing leakage current, with a simple configuration. The purpose of this invention is to provide a MOS type transistor that can be used.

[Means to solve the problem]

The MOS transistor of the present invention has a first high-resistance semiconductor region (source, drain region) under the gate electrode (4) (
5) and (6) and the low resistance semiconductor region (7a) in the channel region (7), a second high resistance semiconductor region (
offset portion) (8);
A gate insulation MtJ (
3) Constructed to have an insulating film (9) with a higher dielectric constant.

[For production]

According to the configuration of the present invention described above, since the film (9) having a higher dielectric constant than the gate insulating film (3) is formed from the gate electrode (4) to the offset portion (8), when the transistor is turned on, The high dielectric constant insulating film (9) becomes a parasitic MOS, and the offset part (8) becomes the source and drain regions (
It changes to the same conductivity type as 5) and (6). Therefore, the resistance of the offset portion (8) decreases as the gate voltage increases, and as a result, the on-current decreases in the offset portion (8).
is no longer limited by the resistance of

When the transistor is turned off, the channel region (the junction between the blade and at least the drain region (6), the first
In the illustrated example, the leakage current is determined by the electric field applied to the PN' junction.

However, since this configuration has an offset gate structure,
Since the electric field at the PN'' junction does not become stronger due to the gate voltage, the withstand voltage is improved and leakage current is reduced.

Embodiment C] The present invention will be described in detail below with reference to FIGS. 1 and 2.

FIG. 1 shows an MO of an offset gate structure according to this embodiment.
FIG. 2 is a configuration diagram showing an example in which an S-type transistor is applied to a thin film transistor.

In this figure, (1) is an insulating substrate made of 5i02;
(2) is an active layer made of polycrystalline silicon, (3) is a Si
O! (4) is a gate electrode made of polycrystalline silicon, and in the active layer (2),
It has a source region (5) and a drain region (6) in which, for example, N-type impurities are ion-implanted on the left and right sides, and a channel region (7) under the gate electrode (4).
the low resistance region (7a) of the channel region (7) and the source.

An offset portion (8), which is a high resistance region, is provided between the drain regions (5) and (6).

A sidewall portion (9) is formed between the gate electrode (4) and the offset portion (8) by a film having a higher dielectric constant than the gate insulation III (3), for example, a Taxes film. Then, a SiO2 layer (10) for surface protection is deposited over the entire surface, and source electrodes (made of Al, for example) are formed on the source region (5) and drain region (6), respectively.
11) and a drain electrode (12) are ohmically connected.

As will be clear from the description below, the conditions for the parasitic MOS in the sidewall part (9) by the Taxes film are such that the capacitance (per unit area) of the parasitic MOS is at least offset from the gate capacitance in the gate part (8). The condition is such that it becomes smaller in some part.

Next, the operation of the MOS transistor according to this embodiment when it is off and on will be explained.

When the transistor is off, the junction between the channel region (7) and at least the drain region (6), in the illustrated example P-
The leakage current is determined by the electric field applied to the N'' junction (8a).

However, since this embodiment uses an offset gate structure, the electric field at the PN' lateral junction 8a) does not become stronger due to the gate voltage (an effect due to the so-called offset gate structure). However, since the sidewall portion (9) formed by the Taxes DI is a parasitic MOS, if the space here is large, the effect of the offset gate structure described above will be diminished. That is, when a negative electric field is applied to the gate electrode (4), the offset portion (8) changes to P in the illustrated example, and the offset portion (8) changes accordingly.
) and at least the drain region (5), the electric field applied to the P'-N' lateral junction 8a) increases and a leakage current occurs. However, the sidewall portion (9) is formed to have a substantially triangular cross section, and the capacitance of its long side portion (9a) is small, so the parasitic M in this sidewall portion (9)
The OS conditions satisfy the above conditions, and P”
The leakage current of the -N' lateral junction 8a) becomes very small, and does not affect the improvement of breakdown voltage and reduction of leakage current, which are the characteristics of the offset gate structure.

Conversely, when it is on, that is, when a positive electric field is applied to the gate electrode (4), the sidewall portion (9) becomes a parasitic MO5, and the offset portion (8) changes to N type in the illustrated example. Therefore, as the gate voltage increases, the offset part (
8) is reduced, and the M limit on the on-current no longer occurs.

In this example, the sidewall portion (9) made of a high dielectric constant film of TazO@ is formed to have a substantially triangular cross section.
As shown in FIG. 2, a high dielectric constant film (13) of Ta205 may be formed to cover the gate electrode (4) up to the offset portion (8), or a 5iJa film may be used instead of the Ta20B film. Alternatively, a multi-Jii structure of 5rxNa film 5iOzlHI may be used.

Furthermore, although this example deals with N-channel thin film transistors, it is of course possible to apply the present invention to P-channel thin film transistors, and also to ordinary MOS type transistors.

FIG. 3 is a configuration diagram showing a conventional example.

(1) is an insulating substrate, (2) is an active layer, (3) is a gate insulating film, (4) is a gate electrode, (5) is a source region, and (6) is a gate insulating film.
) is the drain region, (7) is the channel region, (7a)
is a low resistance region, (8) is an offset portion, (9) is a sidewall portion, (10) is a SiO□ layer, (11) is a source electrode, and (12) is a drain electrode.

〔Effect of the invention〕

The MOS transistor according to the present invention has a second high-resistance semiconductor region between the first high-resistance semiconductor region and the low-resistance semiconductor region above which the gate is raised, and the second high-resistance semiconductor region and the second high-resistance semiconductor region. Since it is configured to have an insulating film with a higher dielectric constant than the gate insulating film between the gate electrode and the gate electrode, it is possible to improve the withstand voltage and reduce leakage current, and also to reduce the resistance to on-ta. You can also do that.

[Brief explanation of the drawing]

Claims (1)

[Claims] A second high-resistance semiconductor region is provided between the first high-resistance semiconductor region and the low-resistance semiconductor region under the gate electrode, and the second high-resistance semiconductor region and the gate electrode are connected to each other. A MOS transistor characterized by having an insulating film with a higher dielectric constant than a gate insulating film between the gate insulating films.