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JPH0274046A - 半導体集積回路装置 - Google Patents

半導体集積回路装置

Info

Publication number
JPH0274046A
JPH0274046A JP63225767A JP22576788A JPH0274046A JP H0274046 A JPH0274046 A JP H0274046A JP 63225767 A JP63225767 A JP 63225767A JP 22576788 A JP22576788 A JP 22576788A JP H0274046 A JPH0274046 A JP H0274046A
Authority
JP
Japan
Prior art keywords
integrated circuit
case
chip
semiconductor integrated
size
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63225767A
Other languages
English (en)
Inventor
Masaaki Ideno
井手野　雅明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP63225767A priority Critical patent/JPH0274046A/ja
Publication of JPH0274046A publication Critical patent/JPH0274046A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路装置に関し、特に複合チップ構
造の半導体集積回路装置に関する。
〔従来の技術〕
第２図は従来の複合チップ半導体集積回路装置の平面図
で、１個或いは複数個の半導体集積回路チップ８が２次
元的にケース内に配置されケース・リード２と相互接続
される。ここで、３はケース・アイランド、５および７
はそれぞれ外部接続用導電膜およびボンディング・ワイ
ヤである。
〔発明が解決しようとする課題〕
しかしながら、上述した従来の半導体集積回路装置は、
ケース内に集積回路チップが２次元的に配置されている
為、大規模な回路を２チツプに分は同一ケースに搭載し
た場合、或いは大規模な回路を１チツプで実現しケース
に搭載した場合の何れでも、ケースのサイズは大きくな
り、また集積回路チップのサイズも大きくなる為、歩留
りの低下をまねく欠点がある。
本発明の目的は、ケース・サイズを大型化することなき
複合チップ構造の半導体集積回路装置を提供することで
ある。
〔課題を解決するための手段〕
本発明によれば、半導体集積回路装置は、チップ・サイ
ズの異なる複数個の半導体集積回路チッブと、前記半導
体集積回路チップをチップ・サイズの大きさ順にケース
・アイランド上に順次載置するケースと、前記ケースの
ケース・リードと半導体ｉ積回路チップの外部接続用導
電膜とを相互接続するボンディング・ワイヤとを備える
ことを次に本発明について１図面を参照して説明する。
第１図（ａ）および（ｂ）はそれぞれ本発明の一実施例
を示す複合チップ半導体集積回路装置の斜視図およびそ
のＡ−Ａ’断面図である０本実施例によれば、第１の集
積回路チップ１がケース・アイランド３上に搭載され、
また第２の集積回路チップ４が第１の集積回路チップ１
の外部接続用導電膜５を露出させるように第１の集積回
路チップ１１に固着される。ここで第１のＳ積回路チッ
プ１の外部接続用導電膜５と第２の集積回路チップ４の
外部接続用導電膜６とはボンディング・ワイヤ７によっ
てケース・リード２とそれぞれ接続される。
〔発明の効果〕
以上説明したように本発明によれば、半導体集積回路装
置は、複数個のチップを重ねて搭載する為、ケースのサ
イズを拡大することなく、大規模な回路を同一ケース内
に納めることが可能となる。
又、上記の構造により、大規模な回路を１チツプで構成
する必要がないので、集積回路チップのサイズも小さく
なり、歩留りの向上をはかることができる。
【図面の簡単な説明】
第１図（ａ）および（ｂ）はそれぞれ本発明の一実施例
を示す複合チップ半導体集積回路装置の斜視図およびそ
のＡ−Ａ’断面図、第２図は従来の複合チップ半導体！
４積回路装置の平面図である。 １・・・第１の集積回路チップ、２・・・ケース・リー
ド、３・・・ケース・アイランド、４・・・第２の集積
回路チップ、５・・・第１の集積回路チップの外部接続
用導電膜、６・・・第２の集積回路チップの外部接続用
導電膜、７・・・ボンディング・ワイヤ。

Claims (1)

    【特許請求の範囲】
  1. チップ・サイズの異なる複数個の半導体集積回路チップ
    と、前記半導体集積回路チップをチップ・サイズの大き
    さ順にケース・アイランド上に順次載置するケースと、
    前記ケースのケース・リードと半導体集積回路チップの
    外部接続用導電膜とを相互接続するボンディング・ワイ
    ヤとを備えることを特徴とする半導体集積回路装置。
JP63225767A 1988-09-09 1988-09-09 半導体集積回路装置 Pending JPH0274046A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63225767A JPH0274046A (ja) 1988-09-09 1988-09-09 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63225767A JPH0274046A (ja) 1988-09-09 1988-09-09 半導体集積回路装置

Publications (1)

Publication Number Publication Date
JPH0274046A true JPH0274046A (ja) 1990-03-14

Family

ID=16834484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63225767A Pending JPH0274046A (ja) 1988-09-09 1988-09-09 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPH0274046A (ja)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0503201A3 (ja) * 1990-12-20 1994-03-16 Toshiba Kk
US5327584A (en) * 1991-03-11 1994-07-05 Matsushita Electric Industrial Co., Ltd. Portable radio having cover releasing mechanism and receive switch which are operable together
US5485517A (en) * 1993-12-07 1996-01-16 Gray; Robert R. Portable wireless telephone having swivel chassis
US5504813A (en) * 1993-02-12 1996-04-02 Sony Corporation Portable telephone
US5614766A (en) * 1991-09-30 1997-03-25 Rohm Co., Ltd. Semiconductor device with stacked alternate-facing chips
US5886412A (en) * 1995-08-16 1999-03-23 Micron Technology, Inc. Angularly offset and recessed stacked die multichip device
US6051886A (en) * 1995-08-16 2000-04-18 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
KR20000063735A (ko) * 2000-08-01 2000-11-06 홍영희 밀집도가 높은 패드
US6884657B1 (en) 1995-08-16 2005-04-26 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
JP2009540606A (ja) * 2006-06-15 2009-11-19 マーベル ワールド トレード リミテッド スタックダイパッケージ

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5715147A (en) * 1990-12-20 1998-02-03 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board
US5473514A (en) * 1990-12-20 1995-12-05 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board
EP0503201A3 (ja) * 1990-12-20 1994-03-16 Toshiba Kk
US5613295A (en) * 1990-12-20 1997-03-25 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board and method for manufacturing same
US5646830A (en) * 1990-12-20 1997-07-08 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board
US5327584A (en) * 1991-03-11 1994-07-05 Matsushita Electric Industrial Co., Ltd. Portable radio having cover releasing mechanism and receive switch which are operable together
US5614766A (en) * 1991-09-30 1997-03-25 Rohm Co., Ltd. Semiconductor device with stacked alternate-facing chips
US5504813A (en) * 1993-02-12 1996-04-02 Sony Corporation Portable telephone
US5485517A (en) * 1993-12-07 1996-01-16 Gray; Robert R. Portable wireless telephone having swivel chassis
US5886412A (en) * 1995-08-16 1999-03-23 Micron Technology, Inc. Angularly offset and recessed stacked die multichip device
US6051886A (en) * 1995-08-16 2000-04-18 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US6563205B1 (en) 1995-08-16 2003-05-13 Micron Technology, Inc. Angularly offset and recessed stacked die multichip device and method of manufacture
US6884657B1 (en) 1995-08-16 2005-04-26 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
KR20000063735A (ko) * 2000-08-01 2000-11-06 홍영희 밀집도가 높은 패드
JP2009540606A (ja) * 2006-06-15 2009-11-19 マーベル ワールド トレード リミテッド スタックダイパッケージ

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