JPH0269854A - Information transfer control method - Google Patents

Abstract

PURPOSE:To prevent the fall of the processing capacity of a common processing part due to the queuing of a common bus by providing a processed result storing means which stores executed result which an individual processing part having executed information processing based on a processing request stored in a processing request storing means informs to a common processing part and which the common processing part extracts directly through the common bus. CONSTITUTION:The processing request storing means 301 stores directly the processing request the common processing part 100 transmits to the individual processing part 300 through the common bus 400. The processed result storing means 302 stores the executed result the individual processing past 300 having executed the information processing based on the processing request stored in the processing request storing means 301 informs to the common processing part 100, and the common processing part 100 extracts it directly through the common bus 400. Thus, the use frequency of the common bus is reduced, and the fall of the processing capacity of the common processing part due to the queuing of the common bus can be avoided.

Description

[Detailed Description of the Invention] [Summary] A common processing unit, a common storage unit, and a plurality of individual processing units are connected by a common bus, and each individual processing unit performs information processing based on a processing request transmitted from the common processing unit. Regarding the information transfer control method in the communication processing device that executes, the purpose is to avoid as much as possible the chance that the processing capacity of the common processing section will be reduced due to waiting until the common bus becomes available, and each individual processing section is equipped with the following: A processing request accumulation means directly accumulates processing requests transmitted from the common processing section to the individual processing sections via a common bus, and an individual processing section that executes information processing based on the processing requests accumulated in the processing request accumulation means. The apparatus is configured to include a processing result accumulation means for accumulating execution results to be notified to the common processing section and for the common processing section to directly extract them via the common bus.

[Industrial application field]

The present invention provides a communication processing device in which a common processing unit, a common storage unit, and a plurality of individual processing units are connected by a common bus, and each individual processing unit executes information processing based on a processing request transmitted from the common processing unit. Related to information transfer control method.

[Conventional technology]

FIG. 4 is a diagram showing an example of a conventional communication processing device,
FIG. 5 is a diagram illustrating the information transfer process in FIG. 4.

In FIG. 4, a common processor unit 3 is connected via a transfer control device 2 to a central processing unit 1 that controls communication processing of the communication processing device in general, and a common processor unit 3 is necessary for executing various information processing. A common memory section 5 that stores various types of information is connected to a plurality of individual processors 6 (individual processors are referred to as 61 to 6-n, hereinafter the same) through a common processor bus 4.

4 and 5, when the central processing unit 1 transmits a required processing request a to the common processor section 3 via the transfer control device 2, the common processor section 3 analyzes the received processing request a. , create command words b and b2 that instruct the individual processors (for example, 6-1) to execute the information processing corresponding to the processing request a, and share them via the common processor bus 4. After being stored in the area 51-1 corresponding to the individual processor 6-1 of the memory unit 5, the activation signal C is transmitted to the individual processor 6-1 via the common processor bus 4.

The individual processor 6-1 that has received the activation signal C refers to the area 51-1 corresponding to its own individual processor 6-1 in the common memory unit 5 via the common processor bus 4, and reads the stored command word b and After extracting the command word b2 via the common processor bus 4 and executing the information processing instructed by the command word b and b2, a status word d indicating the execution result is created, and the status word d is extracted via the common processor bus 4 to the common memory section. After being accumulated in the area 52-1 corresponding to the own individual processor 6-1 in 5, the end interrupt signal e is transmitted to the common processor unit 3 via an interrupt signal line (not shown).

When the common processor unit 3 detects the end interrupt signal e transmitted from the individual processor 6-1, the common processor unit 3 interrupts the individual processor 6-1 in the common memory unit 5 via the common processor bus 4.
Referring to the corresponding area 52-1, the accumulated status word d is extracted via the common processor bus 4, and the individual processor 6-1 analyzes the execution result of the information processing instructed by the command words b and b2. Then, a completion report f is created based on the analysis result and transmitted to the central processing unit 1 via the transfer control device 2.

Note that the common processor bus 4 is shared by the common processor unit 3 and each individual processor 6, so while the common processor unit 3 or any individual processor 6 is using the common processor bus 4, other common processor units 3 and The individual processors 6 must wait until the common processor bus 4 becomes free.

[Problems to be Solved by the Invention] As is clear from the above description, in a conventional communication processing device, the common processor section 3 sends the command word b instructing each individual processor 6 to process information via the common processor bus 4. Each individual processor 6 stores information in the common memory section 5 via the common processor bus 4.
The individual processor 6 which has extracted the command word b instructed by the command word b and has finished executing the information processing based on the command word b stores the status word d indicating the execution result in the common memory unit 5 via the common processor bus 4. , the common processor section 3 extracts the status word d from the common memory section 5 via the common processor bus 4, so when the common processor section 3 and each common processor bus 4 access the common memory section 5, the common processor bus 4 If the common processor section 3 is frequently forced to wait to occupy the common processor bus 4, there is a problem in that the processing capacity of the common processor section 3 is reduced.

SUMMARY OF THE INVENTION An object of the present invention is to avoid as much as possible the possibility that the processing capacity of a common processing section is reduced due to waiting until a common bus becomes available.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, 100 is a common processing section, 200 is a common storage section, 300 is a plurality of individual processing sections, and 400 is a common bus.

Reference numeral 301 denotes a processing request storage means provided in each individual processing unit 300 according to the present invention.

Reference numeral 302 denotes a processing result storage means provided in each individual processing section 300 according to the present invention.

[Effect]

The common processing unit 100, the common storage unit 200, and the plurality of individual processing units 300 are connected by a common bus 400 to constitute a communication processing device, and each individual processing unit 300 is connected to the common processing unit 10.
Information processing is executed based on the processing request transmitted from 0.

The processing request storage unit 301 directly stores processing requests transmitted from the common processing unit 100 to the individual processing units 300 via the common bus 400.

The processing result accumulation means 302 accumulates execution results to be notified to the common processing section 100 by the individual processing sections 300 that have executed information processing based on the processing requests accumulated in the processing request accumulation section 301, and the common processing section 100 Direct extraction via common bus 400.

Therefore, compared to the case where the common processing unit and each individual processing unit exchange processing requests and processing results via the common storage unit, the frequency of use of the common bus is significantly reduced, and the frequency of use of the common bus is greatly reduced. Conflicts are eliminated, and deterioration in the processing capacity of the common processing unit due to waiting for the common bus can also be avoided.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a communication processing device according to an embodiment of the present invention, and FIG. 3 is a diagram illustrating the information transfer process in FIG. 2. Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 2, the common processing unit 1OO1 in FIG.
A common processor section 3, a common memory section 5, n individual processors 6, and a common processor bus 4 are shown as a common memory section 200, a plurality of individual processing sections 300, and a common bus 400, respectively, and the processing in FIG. A command register 612 and a status register 613 as a request storage means 301 and a processing result storage means 302 are connected to the interface unit 6 in each individual processor 6.
1 is provided.

In FIGS. 2 and 3, when the central processing unit 1 transmits a required processing request a to the common processor section 3 via the transfer control device 2, the common processor section 3 processes the received processing request a. An individual processor (e.g. 6-
1), create command words b, t, and b2° that instruct the execution of the required information processing, and send the commands provided in the interface section 61 of the individual processor 6-1 via the common processor bus 4. After being stored in the register 612, the activation signal C° is stored in the activation signal register 611 provided in the interface unit 61 of the individual processor 6-1 via the common processor bus 4.

When the processing unit 63 in the individual processor 6-1 detects that the activation signal C'' has been accumulated in the activation signal register 611, it transfers the command words b1' and b2' stored in the command register 612 to the internal bus 62. After executing the information processing instructed by the command words b, 1 and b2° using the program stored in the storage unit 64, a status word d9 indicating the execution result is created, and A status register 61 provided in the interface unit 61 via
3, the interrupt sending section 65 is sent via the internal bus 62.
and causes the end interrupt signal e° to be transmitted to the common processor unit 3 via the interrupt signal line 7-1.

When the common processor section 3 detects the end interrupt signal e transmitted from the individual processor 6-1, it refers to the status register 613 provided in the interface section 61 of the individual processor 61 via the common processor bus 4. Then, the accumulated status word d" is extracted via the common processor bus 4, and the individual processor 6-1 analyzes the execution results of the information processing instructed by the command words b, 1 and b2', and the analysis result is A completion report f is created based on the
to communicate.

As is clear from the above description, according to this embodiment, the common processor unit 3 stores the command words b, l, and b2 in the command register 612 in the required individual processor 6-1.
° is stored directly via the common processor bus 4, and also in the status register 613 in the individual processor bus 6-1.
To directly store the status word d" stored in Therefore, there is no need to access the common memory unit 5 via the common processor bus 4, the frequency of use of the common processor bus 4 is reduced, and the common processor bus 4 is occupied by the common processor unit 3 and each individual processor 6. Therefore, there is no competition for the common processor bus 4, and a decrease in the processing capacity of the common processor section 3 due to the waiting of the common processor bus 4 is prevented.

Note that FIGS. 2 and 3 are only one embodiment of the present invention, and are limited to, for example, transmitting two command words b' and b2' from the common processor section 3 to the individual processor 6-1. Although many other variations may be considered, such as transmitting a single command word or three or more command words, the effect of the present invention does not change in any case. Furthermore, the objects to which the common processor section 3 transmits the command words b, ", and b21 are not limited to the individual processors +6-1, and many other modifications may be considered, but in any case, the present invention can be applied. The effects remain the same.Furthermore, it goes without saying that the configuration of the communication processing device to which the present invention is applied is not limited to that shown in the drawings.

〔Effect of the invention〕

As described above, according to the present invention, in the communication processing device, the common bus is used much more frequently than when the common processing unit and each individual processing unit exchange processing requests and processing results via the common storage unit. In addition, there is no competition for occupying the common bus, and a reduction in the processing capacity of the common processing unit due to waiting for the common bus can be avoided.

In the figure, ■ is the central processing unit, 2 is the transfer control device, and 3 is the central processing unit.
is a common processor section, 4 is a common processor bus, 5 is a common memory section, 6 is an individual processor, 7 is an interrupt signal line, 5
1 and 52 are areas corresponding to individual processors, 61 is an interface section, 62 is an internal path, 63 is a processing section, 64 is a storage section, 65 is an interrupt sending section, 100 is a common processing section, 200
300 is a common storage unit, 300 is an individual processing unit, 301 is a processing request storage unit, 302 is a processing result storage unit, 400 is a common bus, 611 is a start signal register, 612 is a command register, 613 is a status register,

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a communication processing device according to an embodiment of the present invention, FIG. 3 is a diagram illustrating the information transfer process in FIG. 2, and FIG. FIG. 5 is a diagram illustrating an example of a conventional communication processing device, and FIG. 5 is a diagram illustrating the information transfer process in FIG. 4. Principle of the present invention Figure 1) Figure 1, (-1) September 2016; 2Kri device 1 move diagram Traditionally, how many fortunes do you have in a week? 2 units presented R' system l!

Claims (1)

[Claims] A common processing unit (100), a common storage unit (200), and a plurality of individual processing units (300) are connected by a common bus (400), and each of the individual processing units (300) In a communication processing device that executes information processing based on a processing request transmitted from the common processing unit (100), in each of the individual processing units (300), the common processing unit (100) is connected to the individual processing unit (300). processing request storage means (301) for directly storing the processing requests to be transmitted to the computer via the common bus (400); and executing information processing based on the processing requests stored in the processing request storage means (301). The individual processing unit (30
0) accumulates execution results to be notified to the common processing section (100), and the common processing section (100) directly extracts them via the common bus (400).
02).