JPH0263059A - Formation of minute pattern - Google Patents
Formation of minute patternInfo
- Publication number
- JPH0263059A JPH0263059A JP21573988A JP21573988A JPH0263059A JP H0263059 A JPH0263059 A JP H0263059A JP 21573988 A JP21573988 A JP 21573988A JP 21573988 A JP21573988 A JP 21573988A JP H0263059 A JPH0263059 A JP H0263059A
- Authority
- JP
- Japan
- Prior art keywords
- resist film
- resist
- pattern
- opening hole
- electron beam
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000000203 mixture Substances 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 2
- 238000010894 electron beam technology Methods 0.000 abstract description 25
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 239000007788 liquid Substances 0.000 abstract 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000010030 laminating Methods 0.000 abstract 1
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 6
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 4
- 239000004926 polymethyl methacrylate Substances 0.000 description 4
- 206010011732 Cyst Diseases 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- NTIZESTWPVYFNL-UHFFFAOYSA-N Methyl isobutyl ketone Chemical compound CC(C)CC(C)=O NTIZESTWPVYFNL-UHFFFAOYSA-N 0.000 description 2
- UIHCLUNTQKBZGK-UHFFFAOYSA-N Methyl isobutyl ketone Natural products CCC(C)C(C)=O UIHCLUNTQKBZGK-UHFFFAOYSA-N 0.000 description 2
- 208000031513 cyst Diseases 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 244000046146 Pueraria lobata Species 0.000 description 1
- 235000010575 Pueraria lobata Nutrition 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001803 electron scattering Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- WFGFAPPOWRDEGZ-UHFFFAOYSA-M tributyl(pyren-4-ylmethyl)phosphanium;bromide Chemical compound [Br-].C1=CC=C2C(C[P+](CCCC)(CCCC)CCCC)=CC3=CC=CC4=CC=C1C2=C34 WFGFAPPOWRDEGZ-UHFFFAOYSA-M 0.000 description 1
Landscapes
- Photosensitive Polymer And Photoresist Processing (AREA)
- Electron Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
(産業上の利用分野)
本発明は微細パターン形成方法に係り、特に集積回路、
GaAsを素材とするマイクロ波半導体素子の製造にお
ける微細パターンの形成方法に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a method for forming fine patterns, and particularly to integrated circuits,
The present invention relates to a method for forming fine patterns in the manufacture of microwave semiconductor devices made of GaAs.
(従来の技術)
近年、高速のスタティックRAMや乗算器等の集積回路
、あるいはGaAsを素材とするマイクロ波半導体素子
の特性は、微細加工技術の進歩を背景とし飛躍的に向上
した。特に、高電子移動度トランジスタで代表される低
雑音マイクロ波半導体素子で、実用化されているゲート
長は0.3μm以下に達している。この様な微細パター
ンを形成する方法として、電子ビーム露光法が広く採用
されている。(Prior Art) In recent years, the characteristics of integrated circuits such as high-speed static RAMs and multipliers, and microwave semiconductor elements made of GaAs have been dramatically improved due to advances in microfabrication technology. In particular, in low-noise microwave semiconductor devices represented by high electron mobility transistors, the gate lengths in practical use have reached 0.3 μm or less. Electron beam exposure is widely used as a method for forming such fine patterns.
第2図(a)〜(c)は電子ビーム露光法を用いて半導
体基板上にレジストパターンを形成する方法を具体的に
示す図である。先ず、第2図(a)に示すように半導体
基板101上に電子線レジスト膜102を形成する。次
に第2図(b)に示すように、電子線レジスト膜102
に矢印で示す方向から電子ビーム103を照射する。こ
の電子線レジスト膜102としてポジ形のレジスト膜を
用いると、第2図(c)に示すように、電子ビームに照
射された部分が現像により除去され、半導体基板101
上にレジストパターン112が形成される。ところで、
電子ビーム露光法を用いてレジストパターンを再現性良
く安定に形成するためには、露光条件及びレジスト膜の
現像条件を精密に制御するとともに、レジスト膜102
に入射する電子ビーム径を要求されたパターン寸法以下
に絞る必要がある。特に、0.3μm程度のレジストパ
ターンを形成する場合には、レジスト内あるいは半導体
基板からの電子散乱が無視出来なくなるため、レジスト
膜に入射する電子ビーム径を0.1μm以下に絞りこむ
ことが望ましい。FIGS. 2(a) to 2(c) are diagrams specifically showing a method of forming a resist pattern on a semiconductor substrate using an electron beam exposure method. First, as shown in FIG. 2(a), an electron beam resist film 102 is formed on a semiconductor substrate 101. Next, as shown in FIG. 2(b), the electron beam resist film 102
An electron beam 103 is irradiated from the direction shown by the arrow. When a positive resist film is used as the electron beam resist film 102, the portion irradiated with the electron beam is removed by development, as shown in FIG.
A resist pattern 112 is formed thereon. by the way,
In order to stably form a resist pattern with good reproducibility using the electron beam exposure method, exposure conditions and resist film development conditions must be precisely controlled, and the resist film 102 must be precisely controlled.
It is necessary to narrow down the diameter of the electron beam incident on the pattern to the required pattern size or less. In particular, when forming a resist pattern of approximately 0.3 μm, it is desirable to narrow down the diameter of the electron beam incident on the resist film to 0.1 μm or less, as electron scattering within the resist or from the semiconductor substrate cannot be ignored. .
般に、レジスト膜に入射する電子−ビーム径と電子ビー
ム電流は比例関係にあり、電子ビーム電流と露光に要す
る時間は同一感度のレジスト膜を用いた場合、逆比例関
係にある。従って電子ビーム径を絞りこむことは、露光
に要する時間が増大し、時間内の処理数の低下を招く。Generally, the diameter of an electron beam incident on a resist film and the electron beam current are in a proportional relationship, and the electron beam current and the time required for exposure are in an inversely proportional relationship when resist films of the same sensitivity are used. Therefore, narrowing down the electron beam diameter increases the time required for exposure, leading to a decrease in the number of processing steps within that time.
(発明が解決しようとする課題)
叙上の如く、従来の技術によると、露光時間が増大し、
時間当り処理数が低減するとともに、電子ビーム径を0
.1μm以下に設定するためには電子ビーム露光装置の
電子光学系の入念な整備と調整が必要なため、電子ビー
ム露光装置の稼動率が大幅に低下する問題点もある。(Problems to be Solved by the Invention) As mentioned above, according to the conventional technology, the exposure time increases,
The number of processing per hour is reduced and the electron beam diameter is reduced to 0.
.. In order to set the thickness to 1 μm or less, careful maintenance and adjustment of the electron optical system of the electron beam exposure apparatus is required, which poses the problem that the operation rate of the electron beam exposure apparatus is significantly reduced.
この発明は上記従来の問題点に鑑み、微細なレジストパ
ターンを能率良く形成するレジストパターン形成方法を
提供することを目的とするものである。SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, it is an object of the present invention to provide a resist pattern forming method that efficiently forms fine resist patterns.
(課題を解決するための手段)
本発明にかかる微細パターン形成方法は、半導体基板上
に第1のレジスト膜を設けこれに露光処理および現像処
理を施して所定の開孔を有するパターンに形成する工程
と、前記第1のレジスト膜とその開孔の側面にこの第1
のレジスト膜と組成の異なる第2のレジスト膜を積層し
て被着し両レジスト膜の接触界面に両レジスト膜の反応
層を形成する工程と、前記第2のレジスト膜の未反応層
を除去する工程とを具備し、前記第1のレジスト膜の開
孔よりも小さな開孔を形成するものである。(Means for Solving the Problems) A fine pattern forming method according to the present invention includes forming a first resist film on a semiconductor substrate and subjecting it to exposure and development to form a pattern having predetermined openings. step, and the first resist film and the side surface of the opening are coated with the first resist film.
A step of stacking and depositing a second resist film having a different composition from the resist film of the first resist film, forming a reaction layer of both resist films at the contact interface between the two resist films, and removing an unreacted layer of the second resist film. and forming apertures smaller than the apertures in the first resist film.
(作 用)
この発明は第1のレジスト膜の開花よりも小さい開孔が
最終的に得られるので、第1のレジスト膜に設ける開孔
を所定の開孔寸法よりも広く設定できる。このため、照
射する電子ビーム径に対して十分な余裕度をもって形成
でき、しかも、第2のレジスト膜に対しては開孔を施す
ことなく微細パターンが容易に、かつ再現性良く達成で
きる。(Function) In the present invention, the openings smaller than the bloom of the first resist film are finally obtained, so the openings provided in the first resist film can be set wider than the predetermined opening size. Therefore, it is possible to form the resist film with a sufficient margin for the diameter of the irradiated electron beam, and moreover, a fine pattern can be easily achieved with good reproducibility without forming holes in the second resist film.
(実施例) 以下、本発明の一実施例を図面を参照して説明する。(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
まず第1図(a)に示すように、半導体基板101上に
第1のレジスト膜11として、例えばポジタイプの電子
線レジストPMMA (ポリメチルメタアクリレート)
を1μm厚に形成し、ついで前記第1のレジスト膜11
に矢印で示す方向から所定のパターンに従って電子ビー
ム13を照射する。次に第1図(b)に示すように、第
1のレジスト膜11を例えばMIBK(メチルイソブチ
ルケトン)とIPA (イソプロピルアルコール)を容
積比1:2に混合してなる現像液を用いて現像し、例え
ば0.5μmの開孔11aを形成する。電子ビーム露光
法を用いた場合、開孔寸法0.5μm程度のパターンは
比較的大ビーム電流で形成できるため、描画に要する時
間は短時間で済む。First, as shown in FIG. 1(a), a first resist film 11 is formed on a semiconductor substrate 101 using, for example, a positive electron beam resist PMMA (polymethyl methacrylate).
is formed to have a thickness of 1 μm, and then the first resist film 11 is formed to have a thickness of 1 μm.
The electron beam 13 is irradiated according to a predetermined pattern from the direction indicated by the arrow. Next, as shown in FIG. 1(b), the first resist film 11 is developed using, for example, a developer consisting of a mixture of MIBK (methyl isobutyl ketone) and IPA (isopropyl alcohol) at a volume ratio of 1:2. Then, for example, an opening 11a of 0.5 μm is formed. When electron beam exposure is used, a pattern with an opening size of about 0.5 μm can be formed with a relatively large beam current, so the time required for drawing can be shortened.
レジスト膜12として例えばポジタイプのフォトレジス
トAZ1350 (商品名、シブレイ社製)を0.5μ
m厚に塗布し、例えば90℃10分間の熱処理を加え第
1のレジスト膜11と第2のレジスト膜12との境界に
第1図(C)に示すような第2のレジスト膜12の剥離
処理で剥離されない両レジスト膜の反応層14を形成す
る。ここで第2のレジスト膜12を塗布した後の熱処理
は、両レジスト膜の反応層14を安定に形成することを
目的として行なっているが。As the resist film 12, for example, a positive type photoresist AZ1350 (trade name, manufactured by Sibley Co., Ltd.) is used with a thickness of 0.5μ.
The second resist film 12 is peeled off at the boundary between the first resist film 11 and the second resist film 12 as shown in FIG. A reaction layer 14 of both resist films that is not peeled off during processing is formed. Here, the heat treatment after applying the second resist film 12 is performed for the purpose of stably forming the reaction layer 14 of both resist films.
第2のレジスト膜12を塗布しただけでも両レジスト膜
の反応M14を形成することが可能であるため、必ずし
も必要ではない。次に未反応の第2のレジスト膜12を
剥離するために、例えば半導体基板上に紫外線を照射し
た後、AZ現像液に浸漬し、第1図(d)に示すレジス
トパターン15を形成する。This is not necessarily necessary, since the reaction M14 of both resist films can be formed by simply applying the second resist film 12. Next, in order to peel off the unreacted second resist film 12, the semiconductor substrate is irradiated with ultraviolet rays, for example, and then immersed in an AZ developer to form a resist pattern 15 shown in FIG. 1(d).
未反応の第2のレジスト膜12を剥離した後の半導体基
板(1)上のレジスト膜の厚さは、剥離されない反応層
14の存在により当初の第1のレジスト膜12の厚さよ
りも0.1μm厚くなり、同時に開口部の周辺が0.1
μmずつ狭くなることが判っている。The thickness of the resist film on the semiconductor substrate (1) after peeling off the unreacted second resist film 12 is 0.0 mm thicker than the original thickness of the first resist film 12 due to the presence of the reaction layer 14 that is not peeled off. 1μm thicker, and at the same time the area around the opening is 0.1μm thicker.
It is known that the width becomes narrower by μm.
従って第1のレジスト膜の開孔11aの寸法を上記実施
例のように0.5μmと設定した場合、第2のレジスト
膜12を剥離した後の開孔23の寸法は0.3μmとな
る。Therefore, if the dimension of the opening 11a in the first resist film is set to 0.5 μm as in the above embodiment, the dimension of the opening 23 after peeling off the second resist film 12 is 0.3 μm.
なお、上記実施例ではPMMAにAZ1350を用いた
例について説明したが、第2のレジスト膜12を剥離し
た後の開孔の寸法が若干異なるもののPMTPににAZ
1350を、また、PMMAIIPR−1182(商品
名、GAF社製)等のレジストを組合せであってもよい
。また、第1および第2のレジスト膜11.12のパタ
ーン形成に用いる露光手段は、電子ビーム露光に限らず
、Xa露光、あるいはこれらの組合せであってもよい。In the above example, an example was explained in which AZ1350 was used for PMMA, but AZ1350 was used for PMTP, although the dimensions of the openings after peeling off the second resist film 12 were slightly different.
1350 may be combined with a resist such as PMMA II PR-1182 (trade name, manufactured by GAF). Furthermore, the exposure means used to pattern the first and second resist films 11 and 12 is not limited to electron beam exposure, but may be Xa exposure or a combination thereof.
さらに、半導体基板101上にSiO□、あるいはAQ
の膜が形成されている場合にも適用可能である。Furthermore, SiO□ or AQ is formed on the semiconductor substrate 101.
It is also applicable to cases where a film of
以上述べたように本発明によれば、第1のレジスト膜の
開孔を最終的に必要な開孔寸法よりも広く設定すること
が可能となるため、照射する電子ビーム径に対して十分
な余裕度をもって形成出来、しかも第2のレジスト膜を
塗・布した後剥離するだけで必要とする開孔が形成でき
るために、0.3μm程度あるいはそれ以下の開孔寸法
を有する微細パターンの形成が容易に、しかも再現性良
く達成できる顕著な効果がある。As described above, according to the present invention, it is possible to set the openings in the first resist film to be wider than the final required opening size, so that the openings in the first resist film can be set to be larger than the diameter of the electron beam to be irradiated. Formation of fine patterns with an opening size of about 0.3 μm or less because it can be formed with sufficient margin and the required openings can be formed simply by applying and peeling off the second resist film. This has remarkable effects that can be achieved easily and with good reproducibility.
第1図(a)〜(d)は本発明にかかる一実施例の微細
パターン形成方法を工程順に示すいずれも断面図、第2
図(a)〜(c)は従来例の微細パターン形成方法を工
程順に示すいずれも断面図である。
11 第1のレジスト膜
12−−−−−−−−−−一第2のレジスト膜13−−
−−一 電子ビーム
14−−−−一一−−−−−反応層
15 レジストパターン101−−−一
半導体基板
代理人 弁理士 大 胡 典 夫
tt: :lA +のLシスト膜 I3二’fL)ヒ゛
−ム23:開孔
第 1
1!11:Lジストパアー′ノ
図(vsZ)
11α:開)し
tot: 牛’4f23=¥3− roz:<M&b
ynHlZ: 葛2のLシスト膜 /4:51Lら1第
1 丙 (稚乃1)
@2 図 (号ψlンFIGS. 1(a) to 1(d) are sectional views showing a fine pattern forming method according to an embodiment of the present invention in the order of steps;
Figures (a) to (c) are all cross-sectional views showing a conventional fine pattern forming method in the order of steps. 11 First resist film 12--Second resist film 13--
---1 Electron beam 14--11-----Reaction layer 15 Resist pattern 101--1 Semiconductor substrate agent Patent attorney Norihiro Ogott: :lA +L cyst film I32'fL ) beam 23: open hole No. 1 1! 11: L dystopia' figure (vsZ) 11α: open) and tot: cow'4f23=¥3-roz:<M&b
ynHlZ: L cyst membrane of Kuzu 2 /4:51L et al. 1 1st C (Wakano 1) @2 Fig.
Claims (1)
および現像処理を施して所定の開孔を有するパターンに
形成する工程と、前記第1のレジスト膜とその開孔の側
面にこの第1のレジスト膜と組成の異なる第2のレジス
ト膜を積層して被着し両レジスト膜の接触界面に両レジ
スト膜の反応層を形成する工程と、前記第2のレジスト
膜の未反応層を除去する工程とを具備し、前記第1のレ
ジスト膜の開孔よりも小さな開孔を形成する微細パター
ン形成方法。a step of providing a first resist film on a semiconductor substrate and subjecting it to exposure and development to form a pattern having predetermined openings; A step of stacking and depositing a second resist film having a different composition from the resist film of the first resist film, forming a reaction layer of both resist films at the contact interface between the two resist films, and removing an unreacted layer of the second resist film. A method for forming a fine pattern, comprising the step of forming an opening smaller than the opening in the first resist film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21573988A JP2723260B2 (en) | 1988-08-30 | 1988-08-30 | Fine pattern forming method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21573988A JP2723260B2 (en) | 1988-08-30 | 1988-08-30 | Fine pattern forming method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0263059A true JPH0263059A (en) | 1990-03-02 |
JP2723260B2 JP2723260B2 (en) | 1998-03-09 |
Family
ID=16677397
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21573988A Expired - Fee Related JP2723260B2 (en) | 1988-08-30 | 1988-08-30 | Fine pattern forming method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2723260B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6127098A (en) * | 1994-02-24 | 2000-10-03 | Fujitsu Limited | Method of making resist patterns |
US10248023B1 (en) | 2017-09-14 | 2019-04-02 | Mitsubishi Electric Corporation | Method of manufacturing semiconductor device |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030008968A1 (en) | 2001-07-05 | 2003-01-09 | Yoshiki Sugeta | Method for reducing pattern dimension in photoresist layer |
WO2005116776A1 (en) | 2004-05-26 | 2005-12-08 | Jsr Corporation | Resin composition for forming fine pattern and method for forming fine pattern |
JP5233985B2 (en) | 2007-02-26 | 2013-07-10 | Jsr株式会社 | Resin composition for forming fine pattern and method for forming fine pattern |
-
1988
- 1988-08-30 JP JP21573988A patent/JP2723260B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6127098A (en) * | 1994-02-24 | 2000-10-03 | Fujitsu Limited | Method of making resist patterns |
US10248023B1 (en) | 2017-09-14 | 2019-04-02 | Mitsubishi Electric Corporation | Method of manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP2723260B2 (en) | 1998-03-09 |
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