JPH0262793A - Nonvolatile ram - Google Patents

Abstract

PURPOSE:To attain the simultaneous data transfer of all bits with simple constitution by providing amplification MOSFET to transmit the holding voltage of a capacitor for information holding a dynamic type memory cell to an nonvolatile storage element constituting an unvolatile memory cell. CONSTITUTION:A memory cell MC11 is constituted of first MOSFETQ1 for address selection and a capacitor C for information storage to obtain a dynamic type memory cell. On the other hand, the nonvolatile memory cell is constituted of second MOSFETQ2 and the stuck gate MOSFETQ3 of FLOTOX (floating gate tunnel oxide) type. The holding voltage of the capacitor C for storage of the dynamic type memory cell is supplied to a gate and amplification MOSFETQ4 to transmit its drain output to the drain of the stuck gate MOSFETQ3 is provided. Thus, the simultaneous data transfer of all bits to the nonvolatile storage element can be executed with the simple constitution.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a nonvolatile RAM, and particularly to a technique that is effective when used in a combination of a dynamic memory cell and a nonvolatile memory cell. .

[Conventional technology]

A large-capacity EEFROM (Electrically Erasable & Programmable Read Only Memory) that can be written/erased has been developed. Due to its long time span, it cannot be used like static RAM or dynamic RAM.For this reason, a non-volatile RAM that combines dynamic RAM and EEFROM has been proposed.This non-volatile RAM uses RAM in normal operation. However, in the event of an accident such as a power outage, the data in the RAM is transferred to the EEPROM and retained.

Regarding such non-volatile RAM, for example, 1988
IEEE Journal Op, published in February.
Solid-state circuits (IEEE JOUR
NAL OF 5OLID-STATE CIRCUI
TS) VOL23, 1st volume, PP86-90.

[Problem to be solved by the invention]

The above non-volatile RAM is dynamic RAM and FLO
TOX is used, and the number of elements used can be reduced, but
Since data cannot be transferred from the dynamic RAM to the EEPROM for all bits at the same time, data transfer takes time and requires a large charging capacity for transfer. Therefore, there remains a major problem in making stored information non-volatile in response to unexpected power failures such as those mentioned above.

Although a nonvolatile RAM in which a static RAM is combined with the above-mentioned nonvolatile memory elements has been developed, it is not suitable for increasing storage capacity due to the large number of elements used.

An object of the present invention is to provide a nonvolatile RAM that has a simple configuration and is capable of simultaneously transferring data for all bits.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, an amplification MOSFET is provided that transmits the holding voltage of the information holding capacitor of the dynamic memory cell to the nonvolatile storage element constituting the nonvolatile memory cell.

[For production]

According to the above means, the held information is transmitted to the nonvolatile memory element via the amplification MOSFET, so that data transfer to the nonvolatile memory element can be performed simultaneously for all bits with a simple configuration.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a main part of a nonvolatile RAM according to the present invention.

Each circuit element in the figure is formed on a single semiconductor substrate such as single crystal silicon by a semiconductor integrated circuit manufacturing technique as described below.

In the figure, in order to facilitate understanding of the invention, 2×2
The arrangement of memory cells is shown as a representative example. As shown by the dotted line in the figure, a specific circuit configuration of the memory cell MCII is exemplarily shown as a representative. The memory cell MC11 is a first MOS F for address selection.
The ETQ 1 and the information storage capacitor C constitute a known dynamic memory cell. On the contrary,
2nd MOSFETQ2 and FLOTOX for address selection
(Floating gate tunnel oxide) type stacked gate MOSFET Q3 constitutes a nonvolatile memory cell. In this embodiment, in order to enable simultaneous data transfer of all bits from the dynamic memory cell side to the nonvolatile memory cell, the holding voltage of the storage capacitor C of the dynamic memory cell is supplied to the gate, and the drain Amplifying MOSFET that transmits the output to the drain of the stacked gate MOSFET Q3
Q4 is provided. Other memory cells MC12 and MC21 arranged in a matrix together with the memory cell MCII
And MC22 also has the same circuit configuration as the memory cell MCII.

Memory cells MCII and MC12 and MC21 and MC22 arranged in the same row are connected to a data line D arranged in the horizontal direction.
Commonly connected to I and D2, respectively. Specifically, regarding memory cell MCII, the drains of address selection MOSFETs QI and Q2 are commonly connected to data line DI.

Among the memory cells MCII and MC21 arranged in the same column, the gates of the first MOS FETQ1, etc. for address selection forming the dynamic memory cell are coupled to the first word line WDI extending in the vertical direction. Ru. Address selection fourth 2nd MOS that constitutes a non-volatile memory cell
The gates of FETQ2 etc. are coupled to the second word line WSI. The control gates of the stacked gate MOSFETQ3 etc. that constitute the nonvolatile memory cell are
It is combined with the third word \aWFl. The gates of the MOSFETs of the memory cells MC12 and MC22 arranged in other columns are also connected to the first to third word lines WD2 and WS similar to the above.
2 and WF3, respectively.

Amplification MOS such as the above memory cells MCII to MC22
The sources of FETQ4 etc. are coupled to a common source line. This common source line is connected to the potential V3 via a switch MOSFETQ5 that is switch-controlled by a control signal FF that enables the operation of the amplification MOSFETQ4 and the like. This potential V3 is set as the ground potential of the circuit, although it is not particularly limited.

The data lines Di, D2, etc. are provided with a sense amplifier for reading dynamic memory cells, an active restore circuit and a precharge circuit as necessary, a dummy cell and a column switch circuit for forming a read reference voltage, etc. It is something that can be done. Such a circuit can be similar to that of a known dynamic RAM, and since it is not directly related to the present invention, its explanation will be omitted. Similarly, the word line WDiWD2 and the like are coupled to the output terminal of a word line selection circuit similar to a known dynamic RAM. Note that when dynamic memory cells are arranged in a two-intersection method with a pair of complementary data lines arranged in parallel, the arrangement of the word lines is changed accordingly. In other words, one word line is connected to one of the memory cells connected to the inverted or non-inverted data line.

Next, write/read operations of the memory cell will be explained.

(2) Operation of dynamic RAM The word lines WS and WF to which nonvolatile memory cells are coupled are set to a low level non-selected state. This allows MO5
FETQ2 is turned off, and the data line DI and the like are not coupled to the nonvolatile memory cell. Therefore, writing/reading to/from the selected dynamic memory cell is performed in accordance with the word line WD selection operation and the data &%D selection operation, as in a normal dynamic RAM.

As a result, data is rewritten in the information storage capacitor C of the dynamic memory cell. During this time, no writing is performed to the nonvolatile memory cell, so the problem of limiting the number of times of writing that nonvolatile memory elements have is solved.

2) Data transfer from the dynamic memory cell to the nonvolatile memory cell When the power supply is cut off, in other words, the information stored in the dynamic memory cell is transferred to the stack toggle that constitutes the nonvolatile memory cell.
The data shall be written according to the retained information. In this write operation, each word line WDI, WSI, and WF is set to a low non-selection level, and the signal FF is set to a high level to turn on MOSFET Q5. This activates the amplification MOSFET Q4 and the like.

Thereafter, a high level for writing is supplied to the data line D1.

Then, when each word line WSI, W32, etc. is set to a high level for writing, if the holding potential of the information storage capacitor C is at a high level, the amplification MOSFET Q4 is turned on, and the data line DI and the second MOS for address selection are turned on.
Even though the FET is in the on state, the drain potential of the stacked gate MOSFET Q3 is set to low level. As a result, a high electric field does not act between the floating gate and the drain, so that the electrons accumulated in the floating gate remain in the accumulated state.

That is, the stacked gate MOSFET Q3 is in the enhanced mode.

On the other hand, when the holding potential of the information storage capacitor C is low level, the amplification MOSFET Q4 is turned off, and the data line D1 and the second MOSFET for address selection are
Stacked gate MOSF depending on the on state of ETQ2
The drain potential of ETQ3 becomes high level. As a result, a high electric field acts from the floating gate toward the drain, and electrons accumulated in the floating gate are pulled out toward the drain by tunneling. This causes the stacked MOSFET to go into depletion mode.

In this way, when data is transferred from dynamic memory cells to nonvolatile memory cells, data transfer is automatically performed within each memory cell by setting the word line and data line levels, so all memory cells can be transferred simultaneously. Transfer becomes possible.

3) Data transfer from non-volatile memory cell to dynamic memory cell When power is turned on again, word vAWF1. Set WF2 etc. to low level like the ground potential of the circuit, and control signal FF
to low level. This allows stacked gate M
The ground potential of the circuit is applied to the control gates of OSFETQ3 and the like, MOSFETQ5 is turned off, and amplification MOSFETQ4 is turned off.

When the word line WSI is set to high level, the second MOSFET Q2 for address selection is turned on, and when the stacked gate MOSFET Q3 is in the enhanced mode, it is turned off due to the ground potential of the word line WFI to which the control gate is connected. , data & ID
The read data to I becomes high level. Then, when the word line WDI corresponding to the word line WSI is set to a high level, the first MOSFET Q1 for address selection is turned on, and the read high level of the data line D1 is written into the capacitor C. On the other hand, when the stacked gate MOSFET Q3 is in the depletion mode, it is turned on by the ground potential of the word 6mWF1 to which the control gate is connected, and the read data to the data line DI becomes low level. This low level signal is transferred to the capacitor C in the same manner as described above. In this way, it becomes possible to recover (non-volatize) the stored data before the power was cut off.

By repeating the above operations sequentially for each column,
Data recovery of all memory cells is performed.

In other words, data transfer from a nonvolatile memory cell to a dynamic memory cell is performed via a data line, which is different from data transfer from a dynamic memory cell to a nonvolatile memory cell inside the memory cell. , the word line selection operation is performed column by column. That is, the selection operation of the word lines WS and WD as described above is performed by a selection operation similar to a refresh operation in a dynamic RAM.

Therefore, when automatically transferring data within the NVRAM, an address counter circuit similar to an automatic refresh circuit is provided.

4) Initialization of non-volatile memory cells After all of the above data has been transferred, the non-volatile memory cells are initialized (erase operation).

That is, the data lines D, '7-)'vAWD, WS and the control signal FF are set to low level, and only the word line WF is set to high level for erasing. This allows stack toge)
Electrons are injected into the floating gate of MOSFET Q3 from the drain, resulting in a state where charges are accumulated as described above. This will erase previous memory data and
Prepare for write operation at the next power-off.

In the memory cells of this embodiment, amplification MOSFETs are added to the dynamic memory cells and the nonvolatile memory cells, so the number of elements can be reduced to five in total. In addition, the data held in the dynamic memory cell is amplified by a MOS
This allows simultaneous writing to nonvolatile memory elements via FETs.

FIG. 2 shows a block diagram of an embodiment of a microcomputer system using the nonvolatile memory NVRAM as shown in FIG. 1 above.

The microprocessor CPU is composed of a control section, a calculation section, some registers, etc., and performs various controls and calculations. As mentioned above, the nonvolatile memory NVRAM transfers the data in the dynamic memory cell to the nonvolatile memory cell when the power is turned off, and transfers the data held in the nonvolatile memory cell to the dynamic memory cell when the power is turned on again. Perform this action. For this reason, it is convenient to use the nonvolatile memory NVRAM as a register for temporarily storing data that is being operated on in the microprocessor CPU. Thereby, when the power is turned on again, the calculation can be restarted from the middle of the calculation. On the other hand, the memory RAM is composed of a dynamic type RAM or a static type RAM, and is used to store data that does not cause any problem even if it disappears when the power is cut off.

Furthermore, the memory ROM is composed of a read-only memory, and mainly stores programs that instruct calculation procedures and the like. This ROM is a mask type ROM or E
PROM etc. are used.

The input/output circuit I10 is a human output interface that exchanges data with the outside. Each of the circuit blocks described above is connected to the microprocessor CPU by an address bus ABUS, a data bus DBUS, and a control bus CBUS. Furthermore, although not shown, it should be understood that the nonvolatile memory NVRAM includes a booster circuit (charge pump circuit) that generates a high voltage necessary for its operation. A charging circuit using a capacitor or the like is also provided to ensure power supply during the data transfer even if the external power supply is cut off. Each of the above-mentioned circuit blocks is, but is not particularly limited to, one formed of one chip of semiconductor integrated circuit to constitute one chip of microcomputer;
Alternatively, it is mounted on a mounting board such as one or more printed circuit boards.

38 to 3D and FIG. 4 show each element C, Q1 . ．． Q3 and surrounding CMOs
N-channel MOSFET (NMO
3) A cross-sectional view of the manufacturing process for explaining the manufacturing method of the P-channel O8FET (PMO3) is shown.

In FIG. 3A, an N-type well region 21 is formed on the entire surface of the P-type semiconductor substrate 1. As shown in FIG. A P-type channel stopper 3 is formed under the field insulating film 2 with substantially the same structure as the relatively thick field insulating film 2. The field insulating film 2 is formed on the surface of the semiconductor substrate 1 excluding the element formation region.

In FIG. 3B, one electrode of a capacitor constituting a dynamic memory cell and a stacked gate MOS
An N-type diffusion layer 5 is formed to serve as the diffusion N (drain) under the tunnel insulating film of the FET (FLOTOX type). This diffusion layer 5 is formed by selectively implanting arsenic as an N-type impurity using an ion implantation technique.

After removing the insulating film 4' on the element formation area, a clean first
A gate insulating film 4 is formed. At this time, a thick gate insulating film 6 is formed above the diffusion layer 5.

In FIG. 3C, capacitor C1 stacks gate 1-
After removing the insulating film 6 in the tunnel portion of M0SFETQ3, a thin gate insulating film 22 is formed. This thin gate insulating film 22 is an insulating film of capacitor C and F
This becomes the tunnel insulating film of the LTOX type stacked toggle 1-M0SFETQ3.

After depositing the first conductive film made of polycrystalline silicon or the like, predetermined patterning is performed to form one electrode of the capacitor C,
A floating gate of MOSFETQ3 and a gate electrode 7 of first MOSFETQl for address selection are formed. Note that a second MOSFET for address selection (not shown)
Q2 is also formed in the same manner as the above MOSFET QI. In this case, a FLOTOX type stacked gate MOS F
Diffusion layer 6 provided under the tunnel insulating film 22 of ETQ3
is the second MOSFET (not shown) for selecting the above address.
It is shared with one source and drain 'pMM of Q2.

In FIG. 3D, a thick interlayer insulating film 8 is formed. At least the interlayer insulating film 8 above the floating gate electrode of the FLOTOX type stacked gate MOSFET Q3 and the NMO3, P
After removing the insulating film on the semiconductor substrate 1, 21 on which MO3 is to be formed, an interlayer insulating film 9 thinner than the interlayer insulating film 8 is formed. At this time, in the same process, NMO3, PMO
A gate insulating film 10 of No. 8 is also formed.

After depositing a second conductive film made of polycrystalline silicon or the like, predetermined patterning is performed to form the control gate of FLOTOX type stacked gate MOSFETQ3, NMO3,
A gate electrode 11 of PMO3 is formed.

In FIG. 4, in order to increase the withstand voltage of NMO3, an N-type diffusion layer 12 with a low impurity concentration that constitutes the source and drain regions is formed. Similarly, in order to increase the breakdown voltage of the PMO 8, a P-type diffusion layer 13 with a low impurity concentration, which constitutes the source and drain regions thereof, is formed.

A thermal oxide film is formed on the side surfaces of the gate insulating film and on the substrate.

This is a FLOTOX type stacked MOSFET
This is to prevent electrons from leaking from the floating gate 7 of Q3 and to improve the withstand voltage at the end of the gate electrode.

After depositing a silicon oxide film over the entire surface by CVD, sidewalls 14 are formed by anisotropic etching. Then, N-type diffusion layers 15 with high impurity concentration constituting the source and drain of NMO3 are formed. Similarly, PMO3
A P-type diffusion JW16 with a high impurity concentration is formed to constitute the source and drain of.

After this, although not shown, an interlayer insulating film made of PSG, BPSG, or a combination thereof is deposited. After forming contact holes for electrical connection with the source and drain of the device and depositing wiring material such as aluminum,
A predetermined patterning process is performed to form wiring interconnecting elements. Then, a final passivation film made of PSG or the like is formed.

By adopting such a manufacturing method, each element constituting the dynamic memory cell and the FLOTOX type stacked gate (MOSF) constituting the nonvolatile memory cell
ET can be formed in an intermediate process, thereby simplifying the manufacturing process.

The effects obtained from the above examples are as follows. That is, (1) By providing an amplification MOS FET that transmits the holding voltage of the information holding capacitor of the dynamic memory cell to the nonvolatile storage element that constitutes the nonvolatile memory cell, data transfer is enabled inside the memory cell. , it is possible to realize the simultaneous data transfer of all bits from the dynamic memory cell to the nonvolatile memory cell with a simple configuration.

(2) As a non-volatile memory element, a FLOTOX type stacked gate MOSFET is used, and charge is accumulated in its floating gate, and when the potential of the capacitor is at a high level, the charge is accumulated in the floating gate by an amplifying MOSFET. By employing a configuration that extracts the charged charges, it is possible to achieve the effect that data transfer can be performed simply and easily.

(3) Since all bits of data are transferred simultaneously due to (1) above, the effect is that even in the event of an accident such as a power cut, data can be made non-volatile using a relatively simple charging circuit. can get.

(4) One electrode of a capacitor that constitutes a dynamic memory cell and a FLOT that constitutes a nonvolatile memory cell
A diffusion layer (drain) below a tunnel insulating film of an OX type nonvolatile memory element, an insulating film of a capacitor and a tunnel insulating film of the nonvolatile memory element, the other electrode of the capacitor and a floating gate of the nonvolatile memory element. By simultaneously forming them in the same process, it is possible to simplify the number of manufacturing steps.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it goes without saying that various changes can be made without departing from the gist thereof. Nor. For example, as a nonvolatile memory element, in addition to the FLOTOX type, an element that generates hot electrons, injects them into the floating gate, and extracts the electrons accumulated in the floating gate using a tunneling phenomenon is used. It may also be one that uses MNOS (silicon nitride oxide semiconductor). However, regarding the writing, the condition is that charge is injected or extracted from the floating gate according to the on/off state of the amplification MOS FET that receives the holding voltage of the capacitor as described above. It is something. Moreover, the manufacturing method and its structure are not limited to the above-mentioned embodiments, but can be implemented in various embodiments.

This invention can be widely used as a nonvolatile RAM.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, by providing an amplifying MOS FET that transmits the holding voltage of the information holding capacitor of the dynamic memory cell to the nonvolatile storage element constituting the nonvolatile memory cell and transferring data within the memory cell, a simple configuration can be achieved. Simultaneous data transfer of all bits from dynamic memory cells to nonvolatile memory cells becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a main circuit diagram showing an embodiment of a non-volatile RAM according to the present invention, FIG. 2 is a block diagram showing an embodiment of a microcomputer system using the above-mentioned non-volatile RAM, and FIG. 3A 3D to 3D and FIG. 4 are process cross-sectional views showing one embodiment of the manufacturing method. MCII to MC22...Memory cell, Ql...First MOSFET for address selectionSC...Capacitor for information retention, Q2...Second MOSFET for address selection,
Q3...FLOTOX type stocked gate MOSFET
SQ4...Amplification MOSFET, CPU...Microprocessor, NVRAM...Nonvolatile memory, RAM...Random access memory, ROM...Read only memory, Ilo...I/O circuit, ABUS...Address bus, CBUS・Control bus, DBUS・
・Data paste P type substrate, 21...N type well region, 2...Field insulating film, 3...Channel stopper, 4゛...
Insulating film, 4. First gate insulating film, 5. Diffusion layer, 6.
・Thick gate insulating film, 22...Thin gate insulating film (tunnel insulating film), 7...Gate electrode (floating gate 1-), 8...Thick glabella insulating film, 9...Thin glabella insulating film, 10... Gate insulating film, 11... Gate electrode, 12.
13...Low concentration source, drain, 14...Side wall, 15.16...High concentration source, drainFigure 1

Claims (1)

[Claims] 1. A dynamic memory cell consisting of a first MOSFET for address selection and a capacitor for information storage, and a nonvolatile memory cell consisting of a second MOSFET for address selection and a stacked gate structure nonvolatile memory element. , a nonvolatile memory cell comprising an amplifying MOSFET whose gate is supplied with the holding voltage of the capacitor and whose drain is connected to a connection point between the address selection MOSFET and the nonvolatile memory element. Sex RAM
. 2. The dynamic memory cell and the nonvolatile memory cell are connected to a common data line, and the first MOSFE for address selection of the dynamic memory cell
Claim 1, characterized in that the gate of T, the gate of the second MOSFET for address selection of the nonvolatile memory cell, and the control gate of the nonvolatile memory element are coupled to respective word lines. Non-volatile RAM as described. 3. The nonvolatile memory element is such that when the potential of the capacitor is at a low level, the charge accumulated in the floating gate is extracted by the output signal of the amplifying MOSFET. Nonvolatile RAM according to item 2.