JPH0260216B2 - - Google Patents
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- Publication number
- JPH0260216B2 JPH0260216B2 JP15916986A JP15916986A JPH0260216B2 JP H0260216 B2 JPH0260216 B2 JP H0260216B2 JP 15916986 A JP15916986 A JP 15916986A JP 15916986 A JP15916986 A JP 15916986A JP H0260216 B2 JPH0260216 B2 JP H0260216B2
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- JP
- Japan
- Prior art keywords
- resist
- recess
- gate
- pattern
- pattern corresponding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 claims description 19
- 230000005669 field effect Effects 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 230000035945 sensitivity Effects 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 8
- 238000000034 method Methods 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004904 shortening Methods 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
〔概要〕
この発明は、電界効果型半導体装置を製造する
に際して、
第１のレジストマスクでリセスを形成し、第２
のレジストとこれより高感度の第３のレジストと
を積層して、ゲート長相当のパターンのソース電
極寄りの位置への露光と、ゲート電極の拡大寸法
相当のパターンのこれより低ドーズ量の露光とを
任意の順序で行い、現像処理してＴ形ゲート形成
用パターンを開口して、ゲート金属を被着してＴ
形ゲート電極を形成することにより、
非対称リセス・Ｔ形ゲート電極を容易に形成す
るものである。[Detailed Description of the Invention] [Summary] When manufacturing a field effect semiconductor device, the present invention forms a recess in a first resist mask, and a recess in a second resist mask.
This resist and a third resist with higher sensitivity are laminated, and a pattern corresponding to the gate length is exposed at a position close to the source electrode, and a pattern corresponding to the enlarged size of the gate electrode is exposed at a lower dose than this resist. are carried out in any order, developed to open a T-shaped gate forming pattern, deposited gate metal, and formed a T-shaped gate.
By forming a T-shaped gate electrode, an asymmetric recess/T-shaped gate electrode can be easily formed.
本発明は電界効果型半導体装置の製造方法、特
に非対称リセス・Ｔ形ゲート電極を有する電界効
果型半導体装置の製造方法に関する。
The present invention relates to a method of manufacturing a field effect semiconductor device, and more particularly to a method of manufacturing a field effect semiconductor device having an asymmetric recessed T-shaped gate electrode.
電子移動度が高い砒化ガリウム（GaAs）等の
−Ｖ族化合物半導体を用いて電界効果トランジ
スタの遮断周波数等の特性向上が進められている
が、ゲート電極及びリセスの構造は電界効果トラ
ンジスタの特性を大きく支配し、その製造方法の
改善が要望されている。 Progress is being made to improve the cutoff frequency and other characteristics of field effect transistors by using −V group compound semiconductors such as gallium arsenide (GaAs), which have high electron mobility. There is a need for improvement in the manufacturing method.
GaAsを半導体材料とするシヨツトキバリア形
電界効果トランジスタ（MES FET）がマイクロ
波帯域等において既に多数用いられており、更に
空間分離ドーピングと電子の２次元状態化により
一層の高移動度を実現した高電子移動度電界効果
トランジスタ（HEMT）の実用化が始まつてい
る。
Schottky barrier field effect transistors (MES FETs), which use GaAs as a semiconductor material, are already widely used in the microwave band, etc., and high electron Practical use of high mobility field effect transistors (HEMTs) has begun.
これらのFETの特性向上のために、ゲート電
極及びリセス構造について例えば下記の手段が従
来行われている。 In order to improve the characteristics of these FETs, for example, the following measures have been conventionally taken regarding the gate electrode and recess structure.
ゲート長の短縮：遮断周波数がゲート長の２
乗に反比例することから、最新の微細加工技術
を駆使してゲート長を極力短縮している。 Shortening the gate length: cutoff frequency is 2 times the gate length
Since the gate length is inversely proportional to the second power, the latest microfabrication technology is used to shorten the gate length as much as possible.
Ｔ形ゲート：ゲート長の短縮に伴うゲート抵
抗（ゲート電極の導体抵抗）の増大を防止する
ために、ゲート電極の断面形状をＴ字形として
断面積を増大する。 T-shaped gate: In order to prevent an increase in gate resistance (conductor resistance of the gate electrode) due to shortening of the gate length, the cross-sectional shape of the gate electrode is made T-shaped to increase the cross-sectional area.
リセス長の短縮：ソース抵抗（ソース−ゲー
ト間の直列抵抗）を減少して伝達コンダクタン
スgn等を増大する。 Reduction of recess length: Reduce source resistance (series resistance between source and gate) and increase transfer conductance g n etc.
非対称リセス：リセス長の短縮に伴うドレイ
ン耐圧の低下を防止するために、ドレイン電極
−ゲート電極間の間隔がソース電極−ゲート電
極間の間隔より大きい非対称構造として、ドレ
イン側の空乏層を伸ばし電界強度を減少させ
る。 Asymmetric recess: In order to prevent the drain breakdown voltage from decreasing due to the shortening of the recess length, an asymmetric structure is used in which the distance between the drain electrode and the gate electrode is larger than the distance between the source electrode and the gate electrode. Reduce intensity.
前記、については既に多くの製造方法が提
供されており、また、については例えば本発
明者が先に特願昭57−163063によりその製造方法
を提供している。 Many manufacturing methods have already been provided for the above, and for example, the present inventor has previously provided a manufacturing method for the same in Japanese Patent Application No. 57-163063.
該発明によれば、第２図ａ乃至ｅにその１例の
工程順模式側断面図を示す如く、基板２１上に半
導体活性層２３を形成して該半導体活性層２３上
にレジスト２６を被覆し、該レジスト層２６にゲ
ート電極パターンに従う主露光処理２７を行い、
かつ該露光処理２７の後又は前にドレイン電極２
５側に偏倚した補助露光２８を行う。前記露光２
７及び２８を行つたレジスト層２６を現像して断
面が非対称のレジスト空孔２９を形成し、該レジ
スト層２６をマスクとして該半導体活性層２３を
選択的にエツチングして該半導体活性層にリセス
３０を形成し、更に該レジスト層２６をマスクと
して該リセス３０の表面にゲート電極３４を形成
する。なお２２はバツフア層、２４はソース電
極、３４′はゲート金属層である。 According to the invention, as shown in FIGS. 2a to 2e, which are schematic side sectional views of an example of the process order, a semiconductor active layer 23 is formed on a substrate 21, and a resist 26 is coated on the semiconductor active layer 23. Then, main exposure treatment 27 is performed on the resist layer 26 according to the gate electrode pattern,
And after or before the exposure process 27, the drain electrode 2
Auxiliary exposure 28 biased toward the 5th side is performed. Said exposure 2
The resist layer 26 on which steps 7 and 28 were performed is developed to form a resist hole 29 with an asymmetric cross section, and the semiconductor active layer 23 is selectively etched using the resist layer 26 as a mask to recess the semiconductor active layer. Then, using the resist layer 26 as a mask, a gate electrode 34 is formed on the surface of the recess 30. Note that 22 is a buffer layer, 24 is a source electrode, and 34' is a gate metal layer.
前記発明によつて短リセス長の非対称リセスを
形成することができ、またＴ形ゲート電極も製造
されているが、非対称リセスとＴ形ゲート電極と
を併せて形成することは困難で未だ実現されず、
これを可能にする製造方法が要望されている。
According to the invention, an asymmetric recess with a short recess length can be formed, and a T-shaped gate electrode has also been manufactured, but it is difficult to form an asymmetric recess and a T-shaped gate electrode at the same time, and this has not yet been realized. figure,
There is a need for a manufacturing method that makes this possible.
前記問題点は、半導体基体上に第１のレジスト
を被覆してリセス形成用パターンを開口し、該パ
ターンをマスクとしてリセスを形成し、
第２のレジストを被覆してプリベーキングした
後に、該第２のレジストより高感度の第３のレジ
ストを被覆してプリベーキングし、
ゲート長相当のパターンの該リセスの中央から
ソース電極寄りの位置への露光と、ゲート電極を
Ｔ形に拡大する寸法相当のパターンの該ゲート長
相当のパターンより低ドーズ量の露光とを任意の
順序で行い、
該第２及び第３のレジストを現像処理してＴ形
ゲート形成用パターンを開口し、
次いでゲート金属を被着してＴ形ゲート電極を
形成する本発明による電界効果型半導体装置の製
造方法により解決される。
The above-mentioned problem is solved by coating the semiconductor substrate with a first resist, opening a recess formation pattern, forming a recess using the pattern as a mask, coating the semiconductor substrate with a second resist, and pre-baking. A third resist with higher sensitivity than the second resist is coated and prebaked, and a pattern corresponding to the gate length is exposed from the center of the recess to a position near the source electrode, and a pattern corresponding to the size to expand the gate electrode into a T shape is applied. The second and third resists are developed to open a T-shaped gate forming pattern, and then the gate metal is exposed to a lower dose than the pattern corresponding to the gate length. This problem is solved by a method for manufacturing a field-effect semiconductor device according to the invention, in which a T-shaped gate electrode is deposited.
本発明によれば、リセスを形成した半導体基体
上に例えば電子ビーム露光用ポジ形のレジストを
２層積層し、かつゲート長相当のパターンとゲー
ト電極をＴ形に拡大する寸法相当のパターンとの
露光を任意の順序で行う。
According to the present invention, two layers of, for example, a positive resist for electron beam exposure are laminated on a semiconductor substrate in which a recess is formed, and a pattern corresponding to the gate length and a pattern corresponding to the size for enlarging the gate electrode into a T-shape are formed. Perform exposures in any order.
ただし、下層のレジストを上層のレジストより
低感度でＴ形ゲート電極の断面寸法が小さい部分
の高さに相当する厚さとする。 However, the lower layer resist has lower sensitivity than the upper layer resist and has a thickness corresponding to the height of the portion of the T-shaped gate electrode having a smaller cross-sectional dimension.
またゲート長相当のパターンの露光はこの下層
のレジストに所要の露光量を与えるドーズ量と
し、Ｔ形に拡大する寸法相当のパターンの露光は
この上層のレジストに所要の露光量を与えるドー
ズ量とする。なお少なくともゲート長相当のパタ
ーンの露光はリセスの中央からソース電極寄りの
位置とする。 In addition, exposure of a pattern corresponding to the gate length is done at a dose that provides the required exposure amount for the resist layer below, and exposure for a pattern corresponding to the size that expands into a T-shape is set at a dose that provides the required exposure amount for the resist layer above. do. Note that the exposure of a pattern corresponding to at least the gate length is performed at a position close to the source electrode from the center of the recess.
この２層のレジストを現像処理すれば、上層の
レジストには拡大した寸法のパターンの開口、下
層のレジストにはゲート長相当のパターンの開口
が形成され、ゲート金属を被着してリフトオフす
ることによりＴ形ゲート電極が形成される。 If these two layers of resist are developed, an opening with an enlarged pattern will be formed in the upper resist, and an opening with a pattern equivalent to the gate length will be formed in the lower resist, and the gate metal will be deposited and lifted off. A T-shaped gate electrode is formed.
以下本発明を実施例により具体的に説明する。 The present invention will be specifically explained below using examples.
第１図ａ乃至ｆはMES FETにかかる本発明の
実施例を示す工程順模式側断面図である。 FIGS. 1a to 1f are schematic side sectional views in order of steps showing an embodiment of the present invention relating to an MES FET.
第１図ａ参照：半絶縁性GaAs基板１上に、例
えばノンドープのGaAsバツフア層２と不純物濃
度２〜３×1017cm-3、厚さ200〜300mm程度のｎ型
GaAs活性層３とをエピタキシヤル成長し、素子
間分離（図示を省略）を施した後に、例えば金ゲ
ルマニウム／金（AuGe／Au）を用いてソース
電極４及びドレイン電極５を配設する。 See Figure 1a: On a semi-insulating GaAs substrate 1, for example, a non-doped GaAs buffer layer 2 and an n-type layer with an impurity concentration of 2 to 3 x 10 17 cm -3 and a thickness of about 200 to 300 mm.
After epitaxially growing a GaAs active layer 3 and performing element isolation (not shown), a source electrode 4 and a drain electrode 5 are provided using, for example, gold germanium/gold (AuGe/Au).
この半導体基体上に、例えば富士通製CMR等
の電子ビーム露光用ポジレジストを厚さ例えば
0.3〜0.5μｍ程度に塗布してレジスト層６とし、
プリベーキング後露光、現像処理してリセス長相
当のパターンの開口７を設け、これをマスクとし
て例えば弗酸（HF）系溶液によるエツチングを
行いリセス８を形成する。なおリセス８下の活性
層３の厚さは例えば70〜100mm程度とする。 On this semiconductor substrate, a positive resist for electron beam exposure such as Fujitsu's CMR is applied to a thickness of e.g.
Apply to a thickness of about 0.3 to 0.5 μm to form a resist layer 6,
After prebaking, exposure and development are performed to form an opening 7 in a pattern corresponding to the recess length, and using this as a mask, etching is performed using, for example, a hydrofluoric acid (HF) solution to form a recess 8. The thickness of the active layer 3 under the recess 8 is, for example, about 70 to 100 mm.
第１図ｂ参照：この半導体基体上にまずレジス
ト層９を塗布する。ただし本実施例では前記レジ
スト層６を除去せず、これと同一の例えば富士通
製CMR等のレジストを重ねて塗布してレジスト
層９とし、そのリセス８上の厚さをＴ形ゲート電
極の断面寸法がゲート長に相当する部分の高さと
している。 See FIG. 1b: a resist layer 9 is first applied onto this semiconductor body. However, in this embodiment, the resist layer 6 is not removed, and the same resist, such as CMR made by Fujitsu, is coated on top of it to form a resist layer 9, and the thickness above the recess 8 is determined by the cross section of the T-shaped gate electrode. The dimension is the height of the part corresponding to the gate length.
このレジスト層９のプリベーキング後に、これ
より高感度の例えば東レ製EBR−９等のポジレ
ジストを厚さ例えば0.5μｍ程度に塗布してレジス
ト層１０とし、プリベーキングを行う。 After prebaking the resist layer 9, a positive resist having a higher sensitivity, such as EBR-9 manufactured by Toray Industries, is applied to a thickness of about 0.5 μm to form a resist layer 10, and prebaking is performed.
第１図ｃ参照：レジスト層９及び１０に例えば
下記の様に、ゲート長相当のパターンとゲート電
極をＴ形に拡大する寸法相当のパターンとの露光
を任意の順序で行う。 Refer to FIG. 1c: The resist layers 9 and 10 are exposed to light in an arbitrary order with a pattern corresponding to the gate length and a pattern corresponding to the size to enlarge the gate electrode into a T shape, for example, as shown below.
ゲート長相当のパターンの露光１１はドーズ量
を例えば1.5×10-4C／cm2程度として、レジスト層
９に必要な露光量を与え、他方Ｔ形に拡大する寸
法相当のパターンの露光１２はドーズ量を例えば
７×10-5C／cm2程度として、レジスト層１０のみ
に必要な露光量を与える。なお少なくともゲート
長相当のパターンの露光１１はリセス８の中央か
らソース電極４寄りの位置とする。 Exposure 11 of the pattern corresponding to the gate length is performed at a dose of, for example, about 1.5×10 -4 C/cm 2 to provide the necessary exposure amount to the resist layer 9, while exposure 12 of the pattern corresponding to the size expanding into a T-shape is performed. The dose amount is set to, for example, about 7×10 −5 C/cm 2 , and the necessary exposure amount is applied only to the resist layer 10 . Note that the exposure 11 of the pattern corresponding to at least the gate length is set at a position closer to the source electrode 4 from the center of the recess 8 .
第１図ｄ参照：レジスト層１０及び９を現像処
理する。この現像処理によりレジスト層１０には
開口１３ｂ、レジスト層９には開口１３ａが形成
される。 See FIG. 1d: Resist layers 10 and 9 are developed. Through this development process, an opening 13b is formed in the resist layer 10 and an opening 13a is formed in the resist layer 9.
第１図ｅ参照：ゲート金属として例えばアルミ
ニウム（Al）を真空中で被着する。このゲート
金属は開口１３ｂ内では図示の如く堆積してＴ形
ゲート電極１４が形成される。なおレジスト層１
０上にはゲート金属層１４′が堆積する。 See FIG. 1e: Aluminum (Al), for example, is deposited in vacuum as the gate metal. This gate metal is deposited in the opening 13b as shown in the figure to form a T-shaped gate electrode 14. Note that resist layer 1
A gate metal layer 14' is deposited on top of the gate metal layer 14'.
第１図ｆ参照：レジスト層１０，９及び６を剥
離、除去すればゲート金属層１４′も除去される。 Refer to FIG. 1f: When resist layers 10, 9 and 6 are stripped and removed, gate metal layer 14' is also removed.
本実施例はMES FETを引例しているが、
HEMT等についても同様に本発明を適用して、
非対称リセス・Ｔ形ゲート電極構造を容易に実現
することができる。 Although this example cites MES FET,
The present invention is also applied to HEMT etc.,
An asymmetric recess/T-shaped gate electrode structure can be easily realized.
以上説明した如く本発明によれば、非対称リセ
ス・Ｔ形ゲート電極構造により電界効果型半導体
装置の多くの特性向上を同時に実現して、その進
展に大きい効果が得られる。
As described above, according to the present invention, many characteristics of a field effect semiconductor device can be simultaneously improved by using the asymmetric recess/T-shaped gate electrode structure, and a large effect on the development of the field effect semiconductor device can be obtained.
第１図ａ乃至ｆは本発明の実施例の工程順模式
側断面図、第２図ａ乃至ｅは従来例の工程順模式
側断面図である。
図において、１は半絶縁性GaAs基板、２は
GaAsバツフア層、３はｎ型GaAs活性層、４は
ソース電極、５はドレイン電極、６はレジスト
層、７はリセスのパターン、８はリセス、９は低
感度のレジスト層、１０は高感度のレジスト層、
１１はゲート長相当のパターンの露光、１２はＴ
形に拡大する寸法相当のパターンの露光、１３ａ
はレジスト層９の開口、１３ｂはレジスト層１０
の開口、１４はＴ形ゲート電極、１４′はレジス
ト層上のゲート金属堆積を示す。
1A to 1F are schematic side sectional views in the order of steps of an embodiment of the present invention, and FIGS. 2A to 2E are schematic side sectional views in the order of steps of a conventional example. In the figure, 1 is a semi-insulating GaAs substrate, 2 is a semi-insulating GaAs substrate,
GaAs buffer layer, 3 is an n-type GaAs active layer, 4 is a source electrode, 5 is a drain electrode, 6 is a resist layer, 7 is a recess pattern, 8 is a recess, 9 is a low-sensitivity resist layer, 10 is a high-sensitivity resist layer resist layer,
11 is exposure of a pattern corresponding to the gate length, 12 is T
Exposure of a pattern corresponding to the size expanded to a shape, 13a
13b is an opening in the resist layer 9, and 13b is an opening in the resist layer 10.
14 is the T-shaped gate electrode, and 14' is the gate metal deposition on the resist layer.
Claims (1)
セス形成用パターンを開口し、該パターンをマス
クとしてリセスを形成し、 第２のレジストを被覆してプリベーキングした
後に、該第２のレジストより高感度の第３のレジ
ストを被覆してプリベーキングし、 ゲート長相当のパターンの該リセスの中央から
ソース電極寄りの位置への露光と、ゲート電極を
Ｔ形に拡大する寸法相当のパターンの該ゲート長
相当のパターンより低ドーズ量の露光とを任意の
順序で行い、 該第２及び第３のレジストを現像処理してＴ形
ゲート形成用パターンを開口し、 次いでゲート金属を被着してＴ形ゲート電極を
形成することを特徴とする電界効果型半導体装置
の製造方法。[Scope of Claims] 1. After coating a semiconductor substrate with a first resist and opening a recess formation pattern, forming a recess using the pattern as a mask, and coating a second resist and prebaking, A third resist having higher sensitivity than the second resist is coated and prebaked, and a pattern corresponding to the gate length is exposed from the center of the recess to a position near the source electrode, and the gate electrode is expanded into a T shape. A pattern corresponding to the size is exposed to light at a lower dose than a pattern corresponding to the gate length in any order, the second and third resists are developed to open a T-shaped gate forming pattern, and then the gate is formed. 1. A method of manufacturing a field effect semiconductor device, comprising depositing metal to form a T-shaped gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15916986A JPS6315475A (en) | 1986-07-07 | 1986-07-07 | Manufacture of field effect semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15916986A JPS6315475A (en) | 1986-07-07 | 1986-07-07 | Manufacture of field effect semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6315475A JPS6315475A (en) | 1988-01-22 |
| JPH0260216B2 true JPH0260216B2 (en) | 1990-12-14 |
Family
ID=15687786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15916986A Granted JPS6315475A (en) | 1986-07-07 | 1986-07-07 | Manufacture of field effect semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6315475A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0666282B2 (en) * | 1988-12-20 | 1994-08-24 | 日本電気株式会社 | Method of forming fine electrodes |
| JPH04167439A (en) * | 1990-10-30 | 1992-06-15 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH0661266A (en) * | 1992-08-06 | 1994-03-04 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| KR970000538B1 (en) * | 1993-04-27 | 1997-01-13 | 엘지전자 주식회사 | Method for manufacturing a field effect transistor having gate recess structure |
| JP3534624B2 (en) | 1998-05-01 | 2004-06-07 | 沖電気工業株式会社 | Method for manufacturing semiconductor device |
| KR101736914B1 (en) | 2010-12-06 | 2017-05-19 | 한국전자통신연구원 | Method of manufacturing high frequency device structures |
| KR101848244B1 (en) | 2011-12-13 | 2018-05-29 | 한국전자통신연구원 | Semiconductor device including step index gate electrode and fabrication method thereof |
| KR101903509B1 (en) | 2012-07-11 | 2018-10-05 | 한국전자통신연구원 | Method of making field effect type compound semiconductor device |
| KR101736277B1 (en) | 2012-12-12 | 2017-05-17 | 한국전자통신연구원 | Field Effect Transistor and Method of Fabricating the Same |
-
1986
- 1986-07-07 JP JP15916986A patent/JPS6315475A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6315475A (en) | 1988-01-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |