JPH0258338A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPH0258338A JPH0258338A JP63208259A JP20825988A JPH0258338A JP H0258338 A JPH0258338 A JP H0258338A JP 63208259 A JP63208259 A JP 63208259A JP 20825988 A JP20825988 A JP 20825988A JP H0258338 A JPH0258338 A JP H0258338A
- Authority
- JP
- Japan
- Prior art keywords
- film
- resist
- insulating film
- etching
- mesa structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000002184 metal Substances 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000004380 ashing Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 10
- 239000013078 crystal Substances 0.000 claims description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract 1
- 230000003321 amplification Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、例えば、マイクロ波帯での信号の増幅用に使
用するFET 、 HEMTなどのように、オーミック
電極間にリセス構造を伴うゲート長の短いゲート電極を
備えた半導体素子の製造方法に関するものである。Detailed Description of the Invention [Field of Industrial Application] The present invention is applicable to gate length devices with a recess structure between ohmic electrodes, such as FETs and HEMTs used for signal amplification in the microwave band. The present invention relates to a method of manufacturing a semiconductor device having a short gate electrode.
マイクロ波帯で使用するFET 、 HEJ/rrなど
では、ゲート長と呼ばれるゲート電極幅を狭くする必要
があ°る。また、高速性を上げるには相互コンダクタン
スgmの増大が必要で、高gmの実現にはソース・ゲー
ト間の直列抵抗Rsの低減が重要で、R3の低減のため
にリセス構造全形り入れたものがある。In FETs, HEJ/RRs, etc. used in the microwave band, it is necessary to reduce the gate electrode width, which is called the gate length. In addition, to increase the speed, it is necessary to increase the mutual conductance gm, and to achieve high gm, it is important to reduce the series resistance Rs between the source and gate. There is something.
以下、この種半導体素子の従来の製造方法の一例を第3
図によって説明する。Below, an example of the conventional manufacturing method for this type of semiconductor device will be explained in the third section.
This will be explained using figures.
図(、)に示すように、半導体基板(QaAs基板〕I
Kリフトオフ法などによりオーミック1唖4を形成し、
次に、図(b)に示すように、レジスト15全塗布し、
該レノスト15にゲートツヤターン16全オーミツク電
極11にアライメント(目合せ)して形成し、図(c)
に示すように、エツチングによりリセス構造7を形成す
る。As shown in the figure (, ), a semiconductor substrate (QAAs substrate) I
Form ohmic 1/4 by K lift-off method etc.
Next, as shown in Figure (b), the resist 15 is completely coated,
A gate gloss turn 16 is formed on the renost 15 in alignment with the all-ohmic electrode 11, as shown in FIG.
As shown in FIG. 3, a recess structure 7 is formed by etching.
次に、図(d)に示すように、表面に金属膜8を蒸着し
、レジストI5によるリフトオフを利用して、有機溶剤
などによりレジスト15を溶解除去し、同時に、レソス
)15上の金属膜8全も除去する方法で、図(e)に示
すように、リセス構造7にゲート電極8全形成する。Next, as shown in Figure (d), a metal film 8 is deposited on the surface, and using lift-off by the resist I5, the resist 15 is dissolved and removed using an organic solvent or the like. As shown in FIG. 8(e), the entire gate electrode 8 is formed in the recess structure 7 by a method of removing the entire gate electrode 8.
上記の従来の方法では、オーミック電極とr−ト電極の
アライメントが必要で、通常、アライメント時のピッチ
ずれ全考え、オーミック電極間(ソース・ドレイン電極
間)全狭くできず、 Rsと呼ばれる抵抗を小さくでき
ない。また、電極ゲートのパターニングは、リングラフ
ィによるが、遠紫外光を使用しても、0.5μm程度の
ゲート長が限度であり、マイクロ波特性の改善には、ゲ
ート長を短くすることが必要であるのに、ゲート長を0
.5μm以下にすることが難しいという問題があった。The conventional method described above requires alignment of the ohmic electrode and the r-t electrode, and usually takes into consideration the pitch deviation during alignment, and the gap between the ohmic electrodes (source and drain electrodes) cannot be completely narrowed, resulting in a resistance called Rs. Can't make it smaller. In addition, electrode gate patterning is done by phosphorography, but even if deep ultraviolet light is used, the gate length is limited to about 0.5 μm, and shortening the gate length is necessary to improve microwave characteristics. Setting the gate length to 0 even though it is necessary
.. There was a problem in that it was difficult to reduce the thickness to 5 μm or less.
本発明は、上記の問題に鑑みてなされたもので、従来の
方法に比べ、オーミック電極間を狭く、かつ、ケ°−ト
長を短くできる方法を提供することを目的とする。The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a method that can narrow the distance between ohmic electrodes and shorten the cable length compared to conventional methods.
本発明の方法は、半導体基板に該基板の結晶の持つ面方
位性を利用しエツチングにより幅の狭い/ぐターンのレ
ジスト下に逆メサ構造を形成し、この逆メサ構造上のレ
ジストによるリフトオフを利用し逆メサ構造の両側にオ
ーミック電極金属膜を形成し、オーミック電極金属膜及
び逆メツ構造を覆う絶縁膜を形成し、この絶縁膜上にレ
ジストを表面が平らになる厚さに塗布して、アッシング
などにより上配逆メサ構造上の絶縁膜が表面に現われる
まで除去し、表面に現われた絶縁膜をエツチングにより
除去し、絶縁膜?除去した面からの基板層のエツチング
によりメサ構造を除去しオーミ7り金属膜間にリセス構
造を形成し、このリセス構造にリセス構造上の絶縁膜に
よるリフトオフを利用しゲート電極金属膜を形成するも
のである。The method of the present invention is to form an inverted mesa structure under a resist with a narrow width/turn by etching a semiconductor substrate by utilizing the plane orientation of the crystal of the substrate, and to prevent lift-off by the resist on this inverted mesa structure. An ohmic electrode metal film is formed on both sides of the inverted mesa structure, an insulating film is formed to cover the ohmic electrode metal film and the inverted mesa structure, and a resist is applied on this insulating film to a thickness that makes the surface flat. The insulating film on the upper inverted mesa structure is removed by ashing until it appears on the surface, and the insulating film that appears on the surface is removed by etching. The mesa structure is removed by etching the substrate layer from the removed surface, a recess structure is formed between the ohmic metal films, and a gate electrode metal film is formed in this recess structure by utilizing the lift-off caused by the insulating film on the recess structure. It is something.
上記方法によると、オーミック電極間の距離は、逆メサ
構造全形成するためのレジスト/母ターンの線幅にほぼ
等しくなり、r−)長は上記/やターンの線幅より狭く
なり、また、アライメント時のピッチずれ?考慮する必
要がなくなる。According to the above method, the distance between the ohmic electrodes is approximately equal to the line width of the resist/mother turn for forming the entire inverted mesa structure, and the r-) length is narrower than the line width of the turn/or turn. Pitch deviation during alignment? There is no need to consider it.
以下、本発明の一実施例を第1図によって説明する。 An embodiment of the present invention will be described below with reference to FIG.
図(1)に示すように、半導体基板1表面にリングラフ
ィ法により線幅の狭いレジストノやターン2を形成し、
エツチングにより、口(b)に示すように、レジストパ
ターン2の下に逆メサ構造3を形成し、表面に金図膜4
を蒸着し、金属膜4を逆メサ構造3上のレジスト2によ
ってリストオフさせ、レジスト2を溶解除去することで
、逆メサ構造3の両側にオーミック電極金属膜4全形成
する。As shown in Figure (1), resist holes and turns 2 with narrow line widths are formed on the surface of the semiconductor substrate 1 by phosphorography,
By etching, as shown in (b), an inverted mesa structure 3 is formed under the resist pattern 2, and a gold pattern film 4 is formed on the surface.
The ohmic electrode metal film 4 is entirely formed on both sides of the inverted mesa structure 3 by vapor depositing the metal film 4, list-off the metal film 4 with the resist 2 on the inverted mesa structure 3, and dissolving and removing the resist 2.
逆メサ構造は、基板の結晶の持つ面方位性を利用してエ
ツチングすれば、得られる。第2内はGaAs基板での
一例を示す。An inverted mesa structure can be obtained by etching using the crystal orientation of the substrate. The second one shows an example using a GaAs substrate.
次に、グラズマCVDなどにより、図(c)に示すよう
に、表面に絶縁膜5を形成し、図(d)に示すように、
絶縁膜5上にレジスト6を表面が平らになる厚さに塗布
し、このし・シスト6を、図(e)に示すように、アッ
シングなどにより逆メサ構造3上の絶縁膜5が表面に現
われる厚さにまで除去し、図(f)に示すように、表面
に現われた絶縁膜5をエツチングによって除去し、次に
、基板層1のエツチングにより逆メサ構造3を除去しオ
ーミック電極金属膜4間にリセス構造7全形成する。Next, as shown in Figure (c), an insulating film 5 is formed on the surface by Glazma CVD or the like, and as shown in Figure (d),
A resist 6 is applied on the insulating film 5 to a thickness that makes the surface flat, and the resist 6 is removed by ashing etc. so that the insulating film 5 on the inverted mesa structure 3 is on the surface, as shown in Figure (e). As shown in Figure (f), the insulating film 5 appearing on the surface is removed by etching, and then the inverted mesa structure 3 is removed by etching the substrate layer 1 to form an ohmic electrode metal film. 4, the recess structure 7 is completely formed.
次に、図(tr)に示すように、表面に金属膜8を蒸着
し、リセス構造7上の絶縁膜5によってリフトオフさせ
、図(h)に示すように、絶縁膜5を一部工クチング除
去し、図(i)に示すように、有機溶剤などでレジスト
6を溶解し、レジスト6とともにレジスト6上の蒸着金
、属膜8を除去し、さらに、図(j)に示すように、残
った絶縁膜5をエツチング除去する。Next, as shown in Figure (tr), a metal film 8 is deposited on the surface and lifted off by the insulation film 5 on the recessed structure 7, and as shown in Figure (h), the insulation film 5 is partially etched. As shown in Figure (i), the resist 6 is dissolved with an organic solvent or the like, and the deposited gold and metal film 8 on the resist 6 are removed together with the resist 6, and then as shown in Figure (j), The remaining insulating film 5 is removed by etching.
以上の方法により、ソノグラフィ法によるレジスト・ぐ
ターン2幅にほぼ等しい距離全階てたオーミック電極4
と該オーミック電極4間に形成したリセス構造7を伴う
ゲート長が上記レノストノ!ターン幅より狭いr−ト電
極8が得られる。By the above method, the ohmic electrode 4 is placed over the entire distance approximately equal to the width of the resist pattern 2 using the sonography method.
The gate length with the recess structure 7 formed between the ohmic electrode 4 and the ohmic electrode 4 is the same as the above-mentioned length. An r-t electrode 8 narrower than the turn width is obtained.
以上説明したように、本発明によると、リセス構造で、
従来のものよりソース・ドレイ/電極間を狭く、かつ、
ゲート長を短くでき、マイクロ波での増幅用素子として
重要なN、F、Ga1n (雑音指数利得)と呼ばれる
マイクロ波特性の改善に寄与す4、zM21%辷才す顎
1図
第1図は本発明の一実施例を示す断面図、第2図は本発
明の方法における逆メサ構造の例を示す説明図、第3図
は従来の製造方法を示す断面図である。As explained above, according to the present invention, with the recessed structure,
The space between the source and drain/electrode is narrower than the conventional one, and
The gate length can be shortened, contributing to the improvement of microwave characteristics called N, F, and Ga1n (noise figure gain), which are important as microwave amplification elements. 2 is an explanatory diagram showing an example of an inverted mesa structure in the method of the invention, and FIG. 3 is a sectional view showing a conventional manufacturing method.
1・・・半導体基板、2・・・レジスト74′ターン、
3・・・逆メサ構造、4・・・オーミック電極金属膜、
5・・・絶縁膜、6・・・レジスト、7・・・リセス構
造、8・・・ゲート電極金属膜。1... Semiconductor substrate, 2... Resist 74' turn,
3... Inverted mesa structure, 4... Ohmic electrode metal film,
5... Insulating film, 6... Resist, 7... Recessed structure, 8... Gate electrode metal film.
なお図中同一符号は同一または相当する部分を示す。Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
ート電極を備えた半導体素子の製造方法において、半導
体基板に該基板の結晶の持つ面方位性を利用しエッチン
グにより幅の狭いパターンのレジスト下に逆メサ構造を
形成する工程と、上記逆メサ構造上のレジストによるリ
フトオフを利用し上記逆メサ構造の両側にオーミック電
極金属膜を形成する工程と、上記オーミック電極金属膜
及び逆メサ構造を覆う絶縁膜を形成する工程と、上記絶
縁膜上にレジストを表面が平らになる厚さに塗布する工
程と、塗布した上記レジストをアッシングなどにより上
記逆メサ構造上の絶縁膜が表面に現われる厚さになるま
で除去する工程と、表面に現われた上記絶縁膜をエッチ
ングにより除去し、絶縁膜を除去した面からの基板層の
エッチングにより上記逆メサ構造を除去し上記オーミッ
ク電極金属膜間にリセス構造を形成する工程と、上記リ
セス構造に該リセス構造上の絶縁膜によるリフトオフを
利用しゲート電極金属膜を形成する工程とを備えたこと
を特徴とする半導体素子の製造方法。In a method of manufacturing a semiconductor device having a short gate electrode with a recess structure between ohmic electrodes, a semiconductor substrate is etched to form a narrow pattern under a resist by using the plane orientation of the crystal of the substrate. a step of forming a mesa structure; a step of forming an ohmic electrode metal film on both sides of the inverted mesa structure using lift-off by a resist on the inverted mesa structure; and an insulating film covering the ohmic electrode metal film and the inverted mesa structure. A process of forming a resist on the insulating film to a thickness that makes the surface flat, and a process of applying the applied resist to a thickness such as ashing so that the insulating film on the inverted mesa structure appears on the surface. The insulating film appearing on the surface is removed by etching, and the inverted mesa structure is removed by etching the substrate layer from the surface where the insulating film is removed, forming a recess structure between the ohmic electrode metal films. and forming a gate electrode metal film on the recessed structure using lift-off caused by an insulating film on the recessed structure.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63208259A JPH0258338A (en) | 1988-08-24 | 1988-08-24 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63208259A JPH0258338A (en) | 1988-08-24 | 1988-08-24 | Manufacture of semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0258338A true JPH0258338A (en) | 1990-02-27 |
Family
ID=16553277
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63208259A Pending JPH0258338A (en) | 1988-08-24 | 1988-08-24 | Manufacture of semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0258338A (en) |
-
1988
- 1988-08-24 JP JP63208259A patent/JPH0258338A/en active Pending
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