JPH0254955B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to high resolution raster display devices, and more particularly to analog display circuits with broadband amplification circuits for use in such devices.

[Prior Art] Conventionally, cathode ray tube CRT direct viewing devices, CRT projection devices, and flat screen devices (e.g., LED displays, plasma display panels,
There are various devices for displaying data, including flat CRT panels, etc.). There are also different devices for generating displays for specific display devices. These display generators include raster scan display systems and stroke writer systems.
There is.

Recently, there has been increasing interest in aviation safety, particularly in the quality of air traffic control. As a result of a study of currently used air traffic control systems, particularly the displays used in these systems, it has been found that there is a need to improve and standardize these systems. In the United States,
Efforts are being made to update air traffic control equipment, and the U.S. Federal Aviation Administration (FAA) is
They want to create air traffic control work stations that are standardized to have 20" x 20"(20" x 20") displays with 2000 pixels wide and 2000 pixels wide. Note that a pixel is defined here as the smallest addressable dot that can be displayed on a screen. Also
The FAA states that these displays are bright and dark (shaded).
or a shaded background area (shaded
background areas) and a color display.

In displays used in air traffic control,
Traditionally, stroke writer technology has been used that can display bright, flicker-free lines and characters at acceptable brightness levels. However, with this type of display device, it is difficult to create a bright and dark background area or to create a color display. In particular, creating a tinted area on a display requires a high power deflection system that moves the beam fast enough to create the tinted area. Also, in order to create a color display, it is necessary to create a new device.

In contrast to stroke writer devices, raster display devices (eg, standard televisions) are relatively low power, do not have background color problems, and can now also provide color displays. However, currently available raster displays do not provide the large viewing area and high resolution necessary for some applications to meet the FAA's large screen and high resolution requirements.

Currently, commercial televisions have a 2:1 jump with a 30Hz playback cycle. It has 525 rows or horizontal lines. Therefore, 2000 rows and
The requirements for a 2000 pixel display are:
This would make the data processing requirements of the display device much greater than those of commercial television.

Today, high-quality raster displays are 1280
pixel, can provide 1024 pixels horizontally and requires a video bandwidth of 100MHz to 120MHz. For comparison, commercial broadcast video bandwidth is approximately
It is 3MHz. Symmetrically, 2048 pixels high and wide
Projecting a display with 2048 pixels (meeting the 2000 x 2000 pixel requirement to powers of 2), 2:1 interleaving or interlacing, and a 40Hz playback cycle requires approximately 210MHz of video bandwidth. shall be.

In addition to FAA requirements, air traffic control displays must have the ability to display various characteristics (weather, data, flight path, emergency conditions, map area, etc.) in a manner that can be changed at will by the operator viewing the display. It is desirable to have high resolution. This is because allowing the operator to adjust the relative intensity of selected portions of the display provides the operator with the opportunity to more clearly interpret the data being displayed. This type of flexible display also allows air traffic controllers to clearly see what they see on the display, and in an effort to make the operator's image clearer (e.g., by making certain display features brighter or darker). ) can provide a better view of specific parts of the display.

In addition to the need to use displays of the type described above in air traffic control work stations, large, high resolution displays may also be commonly required in various industries. For example, such high-resolution displays are used in computer graphics, CAD/
It is advantageous for use as a monitor in CAM, medicine, defense and other fields.

Therefore, in display technology, digital image data or digital video data must be processed at high data rates to obtain processed image data as display signals for use in high resolution raster scan display devices. A circuit that can do this is required.
Processing circuitry is also required to make certain attributes of the display programmable. Such processing circuitry allows the display to be programmed to display different types of features needed for different types of displays. Additionally, there is a need for an analog display circuit that can receive high speed display signals and drive high resolution raster displays. There is also a need for analog circuitry that can vary the relative display intensity of certain features on the display.

OBJECTS OF THE INVENTION It is an object of the present invention to provide an analog display circuit for a high resolution raster display device that overcomes the above-mentioned drawbacks of conventional display devices.

In particular, the present invention includes a wideband amplifier that receives a display signal at high speed and converts the display signal into a drive signal that drives a CRT color gun to enable the display device to provide a high resolution raster display. The purpose is to provide analog display circuits.

According to one embodiment of the present invention, a broadband amplifier can be provided using a high speed current switching circuit that outputs a drive signal to an analog display circuit based on a display signal.

Further embodiments of the present invention include a plurality of digital-to-analog converters connected to receive an operator-controlled intensity control signal and a current output from the current switching circuit (and drive A broadband amplifier can be provided that provides a voltage output signal to the current switching circuit such that the level of the signal) can be varied by operator control. In this way, an operator viewing a high-resolution raster display can vary the intensity of selected portions of the display, allowing the operator to easily distinguish between different features appearing on the display. can.

[Configuration of the Invention] The analog display circuit of the present invention has many novel features as follows. The analog display circuit of the present invention includes a wideband amplifier circuit that provides a drive signal to the color gun of a CRT, and a display drive circuit that provides a sweep signal to the CRT. And the wideband amplifier circuit is
It has an amplifier circuit for each of the CRT color guns, and each amplifier circuit has 10 channels, a main current source connected to the 10 channels, and a main current source connected to the outputs of the 10 channels. and a current/voltage converter connected thereto. Each channel has a digital-to-analog converter circuit that receives an operator-controlled intensity control signal from the central processing unit and outputs a voltage output signal having a level responsive to the intensity control signal. There is. Each channel also has a current switching circuit connected to one of the ten differential lines that derives the display signal from the pixel rate converter within the digital image processing circuit. Each current switching circuit is connected to the output of a digital-to-analog converter circuit, and the switching circuit receives a voltage output signal from the digital-to-analog circuit. When a display signal is applied to the differential line from the pixel speed converter to the current switching circuit, a display signal is generated and the current switching circuit outputs a current output signal to the current/voltage converter. The current/voltage converter exchanges the current output signal for a drive signal consisting of voltages that drive the grid and cathode of the CRT. The display drive circuit is
Consisting of a combination of linear and resonant amplifiers, the sweep signal applied to the CRT has the advantages of controlled sweep and fast flyback operation.

[Operation of the Invention] The analog display circuit of the present invention is capable of receiving high-speed display signals provided by the digital image processing circuit and outputting drive signals at high speed, so that the raster display device can display high-resolution signals. can provide a flicker-free raster display. We also included an operator-controllable digital-to-analog converter circuit that allows the operator to control the intensity level of each channel displayed on the CRT (i.e.
characteristics) can be changed independently. for example,
If the operator wants to brighten the data of certain alpha characters, the operator can use the digital/
The intensity control signal input to the analog converter circuit can be varied so that this data is not the brightest. This type of fine tuning adjustment is useful in air traffic control work where many different types of data are displayed on the screen at the same time.
This is particularly advantageous in stations. The high speed operation of broadband amplifier circuits can therefore make high resolution displays particularly advantageous for monitoring air traffic. The circuit of the invention is also suitable for use in other types of display devices requiring high resolution images. These other applications include use in computer graphics display devices, mechanical displays (diagnostic devices), CAD/CAM devices, and complex display devices used in military operations.

[Description of Preferred Embodiments] Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a display device that can use the analog display circuit of the present invention. In particular, FIG. 1 is a block diagram of a portion of a common console 20 used to create the primary display viewed by air traffic managers. Actually, common console 2
0 includes auxiliary displays, data entry displays, keyboards, trackballs, alarms, and touch entry devices for each display.
Each air traffic control center has multiple common consoles that have a central processing unit connected to one or more central minicomputers. The central minicomputer is interconnected to the main host computer. For convenience, FIG. 1 shows that central processing unit 22 is capable of receiving image data to be displayed on the main display of common console 20; It only shows that it can be connected to a computer.

Referring to FIG. 1, central processing unit 22 provides digital image data (eg, from a central minicomputer) to digital image processing circuitry 24. Referring to FIG. In the preferred embodiment, central processing unit 22 is a Motorola MC68020 microprocessor connected to digital image processing circuitry 24 via VME bus 26. In the preferred embodiment, bus 26 is a Motorola VME bus. Central processing unit 22 is also connected to analog display circuit 28 via bus 26 to provide intensity control signals to analog display circuit 28 under the control of an operator (e.g., an air traffic controller). . The digital image processing circuit 24 is connected to the central processing unit 22.
receives image data from and outputs display signals (e.g., red, black, and green display signals) for monochrome or color displays at a rate of 210 mega-pixels per second.
occurs. Digital image processing circuit 24 also provides synchronization signals to analog display circuit 28. Analog display circuit 28
The CRT30 is used to control the red, blue and green guns used to form the display.
(This is the main display of the common console 20.)
generates three voltage output signals that are received by the Analog display circuit 28 also receives intensity control signals from central processing unit 22 to vary the intensity of selected features displayed on the screen of CRT 30 under operator control. Analog display circuit 28 also generates a sweep signal in response to a synchronization signal generated by digital image processing circuit 24, which sweep signal is used to control the horizontal sweep of CRT 30.

As mentioned above, the apparatus of FIG.
It was specifically designed as part of the Therefore, in order to meet the FAA display size (20" x 20") and resolution requirements, the circuit of one embodiment of the present invention uses a 2to1 interlaced raster, 40Hz frame ( hertz
vertical frame) and a field rate of 80Hz.
It is designed to generate screen data of 2048 pixels horizontally. The horizontal scanning frequency is 82.2KHz and the video bandwidth is 210MHz. These specifications meet all of the FAA resolution requirements,
It allows you to create color displays and eliminates the problem of background tint that occurs with other techniques.
In a preferred embodiment, as a CRT30,
It incorporates Sony Corporation's Trinitron(TM) color system, which has great advantages for use in high-resolution displays. At present, Sony Corporation has commercially available 20″ x 20″
Although we do not manufacture CRTs, we do not manufacture 30" diagonal CRTs, which can be used to create scaled-down 1792 x 1792 pixel displays measuring 18" tall and 18" wide.
Manufactures CRT). Therefore, this Sony 30'' diagonal CRT can be used in conjunction with digital image processing circuitry 24 to create a display with much higher resolution than is currently available.

2 through 7 are diagrams showing details of the digital image processing circuit 24. FIG. This digital
The image processing circuit 24 is the subject of a "Digital Image Data Processing Circuit" invention by Nelson et al., filed on the same day as the present application.

FIG. 2 is a block diagram of digital image processing circuit 24 of FIG. Digital image processing circuit 24 includes a graphics processing unit 32 that receives image data from central processing unit 22 via bus 26. The graphics processing device 32 supplies address data and write data to the display memory 34 via the graphics bus 36. The display memory 34 has a memory address of CRT.
30 screen positions. Data is displayed in memory 34
When read from the graphics processing device 3
2, display memory 34
The image data (8 bits per pixel) read from is used to address an attribute look-up table 38. Attribute index table 38
is programmable and stores in the eight bits per pixel read from display memory 34 attribute data that gives some desired meaning to the features appearing on the screen of CRT 30. For example, the attribute is
Multiple layers on one map
layer).
These layers may include a geographic map layer, a data block layer, a weather layer, a flight plan layer, etc. By selectively changing the attributes stored in the attribute index table 38, layers can be removed or
You can restore it or change its color etc. In air traffic control applications, radar aeronautical displays are used, often with text information superimposed on the same display (e.g. flight plan). Operators may want to quickly switch from a map display to a text display. I hope that
The required attributes are completely different. For example, a radar display displays weather, targets, etc. in different colors, but in a text display it is desirable to have an underlying reverse video that brightens or dims certain data. The set of attributes stored in the attribute index table includes 256 different colors on the screen, the requirement to flicker some part of the screen, an independent map,
Contains separate sets of aircraft symbols, data, weather, etc. Therefore, providing the programmable attribute index table 38 prevents the display device from being rigidly tied to a particular set of attributes. It consists of multiple pixel memory planes (pixel
This is in contrast to many conventional display devices, which have separate memory planes. For example, two planes are allocated for red pixels, 2
One plane is allocated for blue pixels, two planes for green pixels, and so on. This pre-assigned format limits the flexibility of the display. For example, if two planes are assigned one color,
The pixels will be limited to four intensity levels per color. This level is insufficient for some colors and quite sufficient for others.

Attribute index table 38 can be programmed via central processing unit 22 and can assign attributes to 256 codes if 8 bits per pixel are available. That is,
The contents of each address in the attribute index table 38 are as follows:
It is set via software from central processing unit 22 to adjust the meaning to be given to an 8-bit pixel stored in display memory 34. This allows a great deal of flexibility, making both monochrome and color modes of operation readily available. Monochrome/
In the case of mode, the attribute index table 38 is
The CRT30 can be programmed with a data set that enables it to run with a green beam only, and one pixel 8 stored in display memory to give the green beam multiple intensity levels.
Bits are used. Then, when generating a color display, it can be reloaded with different data to switch some intensity changes of the green beam to other color changes. This can be done by simply changing the data stored in the attribute index table 38 without changing the hardware.

In the preferred embodiment, 16 pixels of 8 bits each (128 bits) are read from display memory 34, and the 8-bit pixels are divided into 4 bits for each color gun (eg, red, green, and blue). are input in parallel to the attribute index table 38 which converts them into strength data. and 12 each
An attribute signal consisting of 16 pixels of bits is output by the attribute lookup table 38. The attribute signals are provided to a pixel rate converter 40 which includes a master clock oscillator operating at 210 MHz. The main clock is divided into three graphics processors.
2, provided to display memory 34 and attribute index table 38; Graphics processor 32 generates horizontal and vertical raster synchronization timing that is input to analog display circuit 28 based on a clock signal that is input to graphics processor 32.

The main functions of the pixel speed converter 40 are:
A sequence or series of pixel data at a video rate of 210 MHz, i.e., the attribute signal (e.g., pixel data) is stored in the attribute index table 3.
Widely parallel words (wide) at speeds from 8 to 13MHz
transmitted in parallel words). Pixel rate converter 40 decodes the serialized pixel data and outputs the results as a display signal to analog display circuitry 28. As will be explained in detail later, the CRT30 color
Ten possible display signals are output by pixel rate converter 40 for each of the guns. Part of the coding originating in the attribute index table is the type of pixel to be displayed (e.g., data
pixel, map pixel, background pixel, control target pixel, aviation pixel, etc.), and the types of categories or categories of pixels are distinguished. This is because each pixel type, regardless of color, needs to be able to be adjusted individually. For example, map
If a pixel is assigned green color and the operator also changes the strength of the data block, they should all change. If the attribute lookup table is loaded with information that makes map pixels blue, then the operator must be able to use the same intensity control to change the intensity of the blue map pixels. Therefore, independent intensity controls are provided for nine classes or types of pixels and background.

In the preferred embodiment, pixel rate converter 40 is housed in close proximity to a portion of analog display circuitry 28 and physically separated from the remainder of digital image processing circuitry 24. Essentially, bus data width is swapped in place of clock speed to achieve physical separation between pixel speed converter 40 and the remainder of digital image processing circuitry 24. This also allows all of the high speed digital and analog circuitry to be confined to one physical location for reduced electromagnetic interference (EMI) containment or containment.

FIG. 3 shows the graphics processing device 3 of FIG.
2 is a block diagram of FIG. Graphics processing unit 32 operates under the control of central processing unit 22 and does not control bus 26, but instead receives data from bus 26. Bus 26 provides 16 bit data, 24 bit address and control signals to bus interface 42. The two graphics data controllers 44 and 46 are
It is connected to bus interface 42.
In the preferred embodiment, the graphics data controllers 44 and 46 are NEC 7220LSI graphics display controllers. Graphics data controller 46 generates and controls symbol vectors, arc and circle pixel patterns and these inputs. The symbols and the like are written to display memory 34 via write data multiplexer 48 and first-in-first-out data buffer 50. In addition, the direct access route 52
is provided, so that the central processing unit 22
The direct access path 52 and the graphics
Via bus 36, data can be directly supplied to or received from display memory 34 or attribute lookup table 38. The central processing unit 22 also provides a display via a write data multiplexer 48, a data buffer 50, and a graphics bus 36.
Data can be provided to memory 34. If the central processing unit 22
In order to write data directly to the display 4, the graphics data controller 46
First, it must be confirmed that no data is actually being written to the memory 34. Graphics・
Because data controller 46 operates under the control of central processing unit 22, central processing unit 22 knows when graphics data controller 46 is writing data to display memory 34. Therefore, the central processing unit 22 and the graphics data controller 46 are
Share one port. If the central processing unit 22
does not provide write data via direct access path 52 or write data multiplexer 48, then command data is provided to either graphics data controller 44 or graphics data controller 46. The graphics data controller 44 is for the display on the CRT 30.
The display memory 34 is dedicated to regenerating or replenishing the screen by sending address data to the display memory 34 via the address multiplexer 45 and the graphics bus 36, so that the display memory 34 is configured to regenerate the screen. It is sequenced through its multiple storage locations. Central processing unit 2
2. Graphics data controller 44
and 46 share access or path to display memory 34 at all times. Address multiplexer 47 is used to select either graphics data controller 46 or central processing unit 22 to have access to display memory 34 and provides address data to address buffer 51. be done. Address multiplexer 45 selects either address buffer 51 or the output of graphics data controller 44 to have access to display memory 34. The timing is divided into phases so that the graphics data controller 4
4 can cause the display memory 34 to read image data to be displayed on the CRT 30. This is because the screen must always be played. Timing circuit 54 is derived from pixel speed converter 40.
It receives 13 MHz and 26 MHz clock signals and provides a synchronous timing circuit 56 timing signal. Synchronous timing circuit 56 alternately generates a first clock signal (Clock 1) and a second clock signal (Clock 2) to be input to graphics data controller 44 and graphics data controller 46, respectively. do. A first clock signal enables graphics data controller 44 to generate a read address signal for reading data from display memory 34, and a second clock signal enables graphics data controller 44 to generate a read address signal for reading data from display memory 34.
6 allows data to be written to display memory 34. The timing circuit 54 also outputs a row address signal (RAS) and a column address signal (CAS).
and read/write signals (R/W) to the display memory 34 via the graphics bus 36.
supply to.

As mentioned above, graphics processing unit 32 operates under the control of central processing unit 22. Address decoder circuit 49 is therefore configured to decode signals indicating that portions of graphics processing unit 32 (e.g., graphics data controllers 44, 46, etc.) are selected by central processing unit 22. Graphics processing device 3
It is included in 2. Address decoder circuit 49 can also provide selection signals to display memory 34 via graphics bus 36.

Figure 4 shows 8 pixel planes (8pixel
2 is a block diagram of display memory 34 consisting primarily of memory 58 containing a plurality of 256K dynamic RAMs organized in planes 1. FIG. Each side contains 64 pieces of 256K dynamic RAM with the capacity to maintain four separate images (e.g., four independent 2048 x 2048 pixel "pages") in memory 58. There is. Thus, one of several pages can be selected for display while the other three pages are written simultaneously. Address multiplexer 45 provides address data via graphics bus 36 to address multiplexer 60 and page and bank select circuit 62 to address memory 58. Each consists of 8 bits depending on the address data.
64 sequential horizontal pixels (e.g., 1 bit from every DRAM in memory 58)
8 during one read cycle determined by the timing/control input to 8. This occurs at a speed of 3.3MHz. Output buffer 64
supplies the attribute index table 38 with image data consisting of 16 pixels (128 bits) of 8 bits each.

Display memory 34 also includes an attribute register 66 for specifying the attributes of the pattern to be written on the screen. For example, data stored in attribute register 66 indicates whether the type of pixel to be written into memory is a line pixel, a character pixel, a map pixel, etc. The page and bank (within a page) in memory to be written to is selected via page and bank selection circuit 62 and selection/timing circuit 63, and planar enable mask 68 and pixel enable mask 70 are set. . Data is written to memory 58 by enabling memory 58 (E input) to store the type of data indicated by attribute register 66 until sixteen pixel planes are reached. Planar enable mask 68 ensures that only selected planes of memory 58 are written to, while pixel enable mask 70 performs a similar function with respect to the number of pixels to be written simultaneously. Central processing unit 22 and graphics data controller 46 can write to 16 different pixels (128 bits) simultaneously. Thus, pixel enablement mask 70 can be used to control the number of pixels to be written to less than 16, depending on the width of the character on a particular line, etc., for example. Central processing unit 22
operates asynchronously with respect to the display device.
Therefore, central processing unit 22 needs to monitor the output of memory 58 via data output register 72. Since a large amount of data is output from the memory 58, the central processing unit 22
A selection signal is supplied via bus 36 to output bank selection circuit 74, which selects only a portion of the data from data output register 72.

5A and 5B are flowcharts illustrating the operation of central processing unit 22 and control of graphics data controllers 44 and 46 within graphics processing unit 32. Referring to FIG. 5A, central processing unit 22 initializes the system by setting a plurality of attributes in attribute index table 38, setting plane enable mask 68, and setting pixel enable mask 70. do. After initialization, graphics processing unit 36 receives image data for display and processes graphics data.
It is determined whether the controller 44 (GDC1) is selected. Once graphics data controller 44 is selected, central processing unit 22 formats and transmits commands for graphics data controller 44 to graphics data controller 44 using the graphics command subroutine (Figure 5B).
data controller 44; If graphics data controller 44 is not selected, central processing unit 22 determines whether graphics data controller 46 (GDC2) has been selected to write data to display memory 34. If selected, central processing unit 22 selects memory access conditions for graphics data controller 46, formats commands for graphics data controller 46, and executes a transmit command subroutine. Execute. If graphics data controller 46 is not selected to access display memory 34, central processing unit 22 determines whether display memory 34 is to be accessed directly. If so, the central processing unit 22
The direct access state is selected to store data in display memory 34. The central processing unit 22 then further displays images for display.
Go back to receive data. Even if central processing unit 22 should not directly access the RHM, it will return to receive more image data for display.

In the transmit command subroutine (FIG. 5B), central processing unit 22 determines whether the selected graphics data controller (44 or 46) is dedicated or in use. If it has been used, central processing unit 22 returns and checks again. If the selected graphics data controller (44 or 46) is not in use, central processing unit 22 determines whether the command data buffer is free (i.e., there are other commands waiting to be executed). If the command data buffer is empty, the check continues until the command data buffer is empty. If the command data buffer is empty, central processing unit 22 stores the command in the internal memory of the selected graphics data controller (44 or 46) and places the parameters (e.g., data) in the parameter memory location. and return to the main program to receive further image data for display.

As mentioned above, in the preferred embodiment, graphics data controllers 44 and 46
is NEC Corporation's 7220LSI graphics
Consists of data controller. Therefore, once the central processing unit 22 provides appropriate commands and parameters to the graphics data controllers 44 and 46, the graphics data controllers 44 and 46 operate under the control of their own internal programs. and output the necessary data.

FIG. 6 is a block diagram of the attribute index table 38 of FIG. 2. Attribute index table 38 converts the 8 bits of pixel data provided by display memory 34 to 4 bits of intensity data for each of the three electron guns of CRT 30 (ie, 12 bits total). The output buffer 64 of the display memory 34 provides groups of 16 pixels (ie, 128 bits total) of 8 bits each in parallel at 13 MHz to the address multiplexer 76. The attribute index table 38 includes a red attribute index table 78, a green attribute index table 80, and a blue attribute index table 82. These three tables (7
8, 80 and 82) each have 8 RAM
It consists of up to 1K. Depending on the amount of data being output by display memory 34, each table (78, 80 and 82) may contain 16 identical sets of multiple attributes, so that display memory 34 is All 16 pixels read from can be used to address a set of attribute index tables 78, 80 and 82 at the same time. Therefore,
For each pixel, the eight bits that define the pixel are used to address one set of each of attribute index tables 78, 80 and 82. Based on the 8 bits of each pixel input to tables 78, 80 and 82, 12 bits are output to pixel rate converter 40 as attribute signals. The output data stream of attribute lookup table 38 includes 16 pixels of 12 bits each clocked at 13 MHz. In another embodiment, an 8-bit input is used for each pixel to produce an 8-bit output for each table 78, 80, and 82. In this way, better color control can be obtained if desired.

Central processing unit 22 has access to tables 78, 80 and 82 in which attributes associated with any 8-bit pixel code may be changed by software modification. address·
Multiplexer 76 and write color selection circuit 84
Address data sent by the central processing unit 22 via the address data specifies the appropriate one of the tables 78, 80, and 82 and the write line address within each table. Data buffer 86 and blue, green, and red input data circuits 88, 90, and 92 are used, and new attributes are specified within a specified one of all 16 sets of tables 78, 80, and 82. written to the address. Changes to tables 78, 80 and 82 are made only during vertical retrace, and therefore this is done immediately without breaking the display. Blue, green and red input data circuits 88, 90 and 92 are connected to tables 78, 80.
and a plurality of shadow RAMs for temporarily storing attribute data to be written to 82 and for writing new data to tables 78, 80 and 82 when the screen is not active.
In the preferred embodiment, attribute traction tables 78,8
The RAMs comprising RAMs 0 and 82 have sufficient capacity to store separate attributes coding for each of the four pages of display memory 34. This is particularly advantageous when storing different displays in display memory 34 (ie, on each of its four pages) for which different attribute tables are desired. Therefore, providing a separate code storage for the four attribute tables provides sufficient display flexibility. Additionally, additional storage facilities can be used to provide different attributes for the same display. For example, there may be a case where it is desired to change the color or the like of a certain part of the display. These sets of attributes are stored in display memory 3.
Multiple attributes can be easily changed and returned to change the colors of different features on the display. Figure 7 shows the pixel speed converter 4 in Figure 2.
6, converter 40 receives attribute signals from attribute lookup tables 78, 80, and 82 (FIG. 6). pixel speed converter 40
includes a 210MHz clock 90 and a pixel speed converter 40 as well as a graphics processing unit 3.
2, a counter 96 that provides timing to the display memory 34 and attribute index table 38; Pixel speed converter 40 converts the attribute signals to a high speed logic family.
multiple TTL/ECL converter circuits 98 (TTL to ECL converter
circuit). In a preferred embodiment,
A Fairchild 100K Family ECL integrated circuit is used as the TTL/ECL converter circuit 98. Multiple TTL/
The output of the ECL converter circuit 98 is supplied to a plurality of multiplexers 102 via a plurality of synchronization registers 100, respectively. Synchronous register 100
is provided for timing purposes; multiplexer 102 receives 64 bits and outputs 4 bits at 16 times the speed.
Speeds up the data rate by a factor of 16 by outputting bits. Multiplexer 1
The outputs of 02 are sent to the decoder 106 via the synchronization register 104, respectively. Decoder 106
decodes the 4-bit output of synchronization register 104 and provides an output (display signal) to one of each of the ten differential line outputs of decoder 106.

The output of synchronization register 104 consists of 12 bits clocked at 210MHz. Each set of 4 bits corresponds to the input of one of the three color guns in the CRT30 and is adjusted to meet display convergencb requirements.
Must be synchronized to within 0.5ns. Each set of four bits input to decoder 106 must be synchronized to 0.5 ns to ensure proper or accurate response of decoder 106 and analog display circuitry 28. Also, the edges of the pulses input to analog display circuit 28 must be faster than 1 ns to ensure accurate switching. For this reason, 100K family ECL logic circuits are used to achieve the desired performance requirements. Pixel speed converter 40 converts (i.e. serializes) a 16 pixel stream (a16pixel strram) into one pixel that is output at 16 times the speed.
do. Because of this high data rate (210MHz), the pixel rate converter 40
It should be placed as close as possible to the wideband amplifier that forms part of the display circuitry 28. By operation of the pixel speed converter 40,
The digital image processing circuit has 4
bit, delivering 210 million pixels per second. Additionally, the pixel speed converter 40 is
Since input data is received at a speed of 13 MHz, data can be processed at a slow speed until just before it is input to the analog display circuit 28.

FIG. 8 is a block diagram of the analog display circuit 28 of the present invention. The analog display circuit 28 includes a first
Second and third amplifier circuits 108, 110 and 11
2, and these amplifier circuits 108, 11
0 and 112 are provided for the red, blue and green color guns of the CRT 30, respectively. Each of the amplifier circuits 108, 110 and 112 receives a display signal output by a corresponding one of the decoders 106 within the pixel rate converter 40 (FIG. 7) and outputs a display signal corresponding to the red color of the CRT 30;
Outputs blue or green drive signal. The analog display circuit 28 receives the synchronization signal output from the digital image processing circuit 24 and
It further includes a display drive circuit 114 that supplies a sweep signal to control scanning of the CRT 30.

FIG. 9 is a block diagram of one of the plurality of amplifier circuits (amplifier circuit 108) of FIG. 8. The amplifier circuit shown in FIG. 9 is the amplifier circuit 108 in FIG.
110 and 112, respectively. The amplifier circuit 108 has a plurality of channels 11
5, and each of these channels 115 has an operator adjustable digital-to-analog converter circuit (D/A) 116 and a current switching circuit 118. Digital-to-analog converter circuit 116 is connected to bus 26 for receiving intensity control signals from central processing unit 22. Each of the digital-to-analog converter circuits 116 provides a voltage output signal to a current switching circuit 118, which is connected to receive current from a main current source 120. Each current switching circuit 118 is connected to ten differential line outputs of the decoder circuit 106, which is connected to the amplifier circuit 108. During raster scanning, one of the ten differential line outputs is selected for each pixel by the decoder circuit 106 and one display signal is generated, and one of the ten current switching circuits 118 is selected for each pixel by the decoder circuit 106. Only one is selected at any time. Each current switching circuit 11
Each of the 10 differential line inputs to 8 (and thus each of the 10 channels 115) can be used to input specific attributes of the display, such as background maps, symbols, weather information, alphanumeric characters, flight path, radar, etc. It corresponds to The display signal output from each decoder 106 selects one of ten attributes for each pixel and acts as a differential line input display signal unless the current switching circuit 118 is selected. The selected current switching circuit 118 provides a current output signal to a current/voltage converter circuit 122 which generates a drive signal for the CRT 30 (in this case the red drive signal).

FIG. 10 shows one channel 115 (i.e.
1 of digital/analog converter circuit 116
12 is a circuit diagram showing details of one of the current switching circuits 118 and 118), the connection to the main current source 120, and the current/voltage converter circuit 122. FIG. The digital/analog converter circuit 116 includes an 8-bit D/A converter 124 and an operational amplifier 126.
It is equipped with 8-bit D/A converter 12
4 receives an 8-bit digital control setting from the central processing unit 2 via the bus as an intensity control signal. D/A converter 12
Since 4 is 8 bits, 256 different values can be set, and by changing these 256 settings by the operator, the corresponding output channel can take on any one of the 256 values. .
Similarly, each of the D/A converters 124 in the other digital/analog converter circuits 116 also
It can take on any of 256 different settings. The human eye can only distinguish about 20 different levels. Therefore, the ability to provide each channel with 256 different levels for display purposes means that in effect each channel is continuously adjustable. The operator can select multiple channels 115 separately (e.g., touch entry display).
the channel 115 to be adjusted) and the central processing unit 22
transmits a new 8-bit digital intensity control setting to

The 8-bit D/A converter 124 converts the current into 8
The output to operational amplifier 126 is responsive to the digital intensity control setting of the bit. The operational amplifier 126 is
A voltage output signal is provided to current switching circuit 118. The current switching circuit 118 is a high speed
Consisting of ECL switching circuits, the voltage across emitter resistor 119 determines how much current is transferred through each current switching circuit 118. By changing the input of D/A converter 124, the output voltage of operational amplifier 126 changes and the current that can flow through current switching circuit 118 also changes. Current switching circuit 118 also has a corresponding decoder 106
one ECL line receiver 128 connected to one of the differential lines. If current switching circuit 118 in channel 115 shown in FIG.
ECL line receiver 128 generates a switching signal that causes current from main current source 120 to flow through current switching circuit 118. As a result, current switching circuit 118 provides a current output signal to current/voltage converter 122.
Note that the plurality of outputs of the current switching circuit 118 are as follows.
are tied together to provide two inputs to current/voltage converter 122. This is because only one of the plurality of current switching circuits 118 is selected at any particular time. In summary, current switching circuit 118 switches on and off in response to the differential line input from decoder circuit 106, allowing current from main current source 120 to flow into current switching circuit 118. And digital/analog converter circuit 11
The voltage output of 6 determines the amount of current that is allowed to flow and be output through current switching circuit 118. The use of current switching circuit 118 rather than voltage switches is necessary because the high resolution raster displays produced by the circuit of the present invention require high speed operation. That is, current switching circuit 1
18 must be capable of switching at a speed of 210 MHz (ie, one of the 10 channels is selected 210 million times per pixel and per pixel per second). Due to the capabilities of such devices, it is not possible to have a voltage switch perform this function.

Current/voltage converter 122 is a common base amplifier and the current output of current switching circuit 118 is applied to the emitters of transistors 130 and 132. Therefore, switching circuit 1
18 acts as a variable current source input to current/voltage converter 122. The drive signal output (essentially a voltage difference) of current/voltage converter 122 drives the grid in one direction and the cathode in a different direction. A voltage difference is thus created between the grid and the cathode. This voltage difference is converted into a brightness difference.

If intensity levels of color are used as the only attribute of a display, it is possible to have nine different brightness levels (for each color) on the screen at any time. . However, any one of these nine levels can be changed (via D/A converter 124) to take on 256 different individual levels. In the preferred embodiment, there are nine different variable levels (corresponding to channels 1 through 9) and a tenth channel, hereinafter referred to as "black." This is because the grid output of the current/voltage converter 122 is capacitively coupled, and the DC component (DC
This is because it is not possible to transport components. Therefore, diode 134 is used to provide a DC restore level to generate a "black" level. Nine channels are therefore operator adjustable and the tenth channel is a maintenance adjustment. In the preferred embodiment, nine adjustable channels provide six simultaneous display brightness levels (the brightness of each level is individually and continuously adjustable by the operator) and three adjustable tint levels ( shading levels).

In a preferred embodiment, pixel rate converter 40 and at least a portion of analog display circuitry 28 are assembled as a hybrid circuit. In particular, the output of pixel speed converter 40 and the input of current switching circuit 118 are:
Essentially it is necessary that they be brought into contact with each other. This is because the speed at which data is processed is high. Ideally, pixel speed converter 40 and amplifier circuits 108, 110 and 112 would be required to ensure the device's ability to operate at 210 MHz.
consists of a hybrid circuit. If the device were instead assembled from separate components, then the video bandwidth would be expected to be 160 to 180 MHz. Although this would still provide a significantly higher resolution display than currently available, the use of hybrid circuitry would provide the desired high resolution requirements to be achieved as described above.

FIG. 11 is a block diagram of the display driving circuit of FIG. 8. Traditional stroke lighters use linear deflection amplifiers.
An operational amplifier feedback circuit was used as the amplifier. However, this type of device requires a large amount of power to rapidly move the current through the deflection yoke. Commercial television, on the other hand, uses a capacitor deflection yoke combined with a switch that is opened and closed to obtain a fast sweeping oscillator. Although such resonant systems do not require much power, they lack the control available with the linear deflection amplifier systems used in stroke writers.

As shown in FIG. 11, the display drive circuit 114 used in the present invention consists of a combination of a linear deflection amplifier and a resonant amplifier. As shown in FIG. 11, the display drive circuit 114 includes a geometry correction amplifier 134, a switching circuit 136, and a switching circuit 13.
6 and connected to the output of shape modification amplifier 134.
Each time switching circuit 136 is closed and scanning is actually performed, display drive circuit 11
4 functions as a linear feed back amplifier;
Current is supplied to deflection yoke 140 and resistor 142
is fed back to the input of shape modification amplifier 134. When rapid feedback is required, the input synchronization signal causes switching circuit 136 to switch, causing display drive circuit 114 to become a resonant amplifier. Thus, one circuit provides the power conservation benefits of a flyback amplifier and the control benefits of a linear amplifier. To compensate for the varying distances that the electron beams must travel within CRT 30 before striking the screen, central processing unit 22 uses
A shape control signal is provided to the input of shape modification amplifier 134 . For example, an electron beam that is focused on a corner on a screen will have traveled a longer distance than a beam that strikes the center of the screen. The shape control signal provided by central processing unit 22 compensates for this so that the display provided on CRT 30 is not distorted.

The operation of analog display circuit 28 of the present invention is as follows. Amplifiers 108, 110 and 112 (FIG. 8) receive intensity control signals from central processing unit 22 and display signals output from digital image processing circuitry 24. Each amplifier circuit 108, 110 and 112 includes ten channels 115, a main current source 120 and a current/voltage converter 122 (FIG. 10). Each channel is connected to a digital image processing circuit 24.
is connected to one of the ten differential line outputs from the decoder 106 within the power supply, and is also connected to receive a strength control signal. Digital-to-analog converter circuit 116 provides a voltage output signal to current switching circuit 118 in response to the strength control signal. When a display signal is received on the differential line input to current switching circuit 118, the voltage output signal from the digital-to-analog converter circuit determines the amount of current flowing through current switching circuit 118, and Determine the channel's current output signal. The current/voltage converter 122 receives the current output signal and converts the CRT 3
Provides a corresponding color gun or gun drive signal within 0.

Although the analog-to-digital circuit of the present invention has been described in connection with a common console at an air traffic control station, the analog-to-digital circuit of the present invention is suitable for use with any type of raster display device where a high resolution display is required. can also be applied. For example, the analog display circuit of the present invention may be used in computer graphics.
It is particularly suitable for use in display systems, CAD/CAM systems, display-based medical diagnostic systems, and military surveillance systems. Furthermore, although the analog display circuit of the present invention has been described in connection with producing a color display,
Of course, the same circuit can be used to generate a monochrome display. In this case, a greater number of attributes are available for display on the CRT 30 screen.

Advantages of the Invention The analog display circuit of the present invention allows a wide video bandwidth to be obtained in high resolution raster display devices. Additionally, the ability of the operator to vary the strength of each channel within the broadband amplifier can be used to great effect when manipulating the display to highlight selected features of the display.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a display device that can use the analog display circuit of the present invention, and FIG. 2 is a block diagram of the graphics image processing circuit 24 of FIG.
3 is a block diagram of the graphics processing device 32 of FIG. 2, FIG. 4 is a block diagram of the display memory 34 of FIG. FIG. 6 is a flowchart illustrating the operation of the central processing unit 22 of FIG. 1 which controls the graphics data controllers 44 and 46 of FIG. 3 for reading data from the memory; FIG. 7 is a block diagram of the pixel rate converter 40 of FIG. 2, and FIG. 8 is a block diagram of the digital image processing circuit 24 of FIG.
9 is a block diagram of the amplifier circuit 108 of FIG. 8, and FIG. 10 is a block diagram of the analog converter circuit 116 and current switching circuit 118 of FIG. 9. , the circuit diagram of the main current source 120 and the current/voltage converter circuit 122, and the first
FIG. 1 is a circuit diagram of the display drive circuit 114 of FIG. 8. 20... common console, 22... central processing unit,
24...Digital image processing circuit, 26...
VME bus, 28...analog display circuit,
30...CRT, 40...pixel speed converter,
106...Decoder circuit, 108, 110, 112
...Amplification circuit, 114...Display drive circuit, 1
15... Channel, 116... Digital/analog converter circuit, 118... Switching circuit, 120... Main current source, 122... Current/voltage converter circuit, 124... D/A converter, 126
...Operation amplifier.

Claims (1)

Claims: 1. In an analog display circuit for driving a CRT of a raster display device connected to receive a display signal for each pixel of an image to be displayed: a plurality of intensity controls; an intensity control signal generating means for generating a signal, the intensity signal generating means and the CRT being connected to receive the display signal, the intensity control signal generating means being connected to the CRT and receiving the display signal; amplifying means for generating a drive signal to drive the CRT in response; said amplifying means being connected to said intensity signal generating means and connected to receive said display signal; and a plurality of channels for generating a current output signal in response to one of the intensity control signals, connected to the channel and the CRT;
a current/voltage converter circuit that generates the drive signal in response to the current output signal, each of the plurality of channels having a differential line input, and the number of channels is equal to or less than the number of channels.
Corresponding to the number of different pixel categories that can be displayed on a CRT screen,
The display signal for each pixel is input only to the differential line input of a selected one of the plurality of channels according to the pixel category to be displayed on the screen, An analog display circuit, wherein only the selected one channel of the analog display circuit generates the current output signal. 2. each of the plurality of channels: a digital-to-analog converter circuit connected to receive one of the intensity control signals to generate a voltage output in response to the received intensity control signal; a digital/analog converter circuit;
connected to the current/voltage converter circuit and the differential line input of the channel in response to the voltage output signal of the digital/analog converter circuit when the differential line input receives the display signal; a current switching circuit for providing the current output signal, the level of the current output signal varying in response to the intensity control signal input to the digital-to-analog converter; 2. The analog display circuit of claim 1, wherein the intensities of said plurality of pixels displayed in response to said plurality of pixels vary under control of said intensity control signal. 3. The analog display circuit according to claim 2, wherein the current switching circuit is an emitter-coupled logic circuit. 4. The current switching circuit includes: an emitter-coupled logic line receiver connected to the differential line input and generating a switching signal when the differential line input receives the display signal; and the emitter-coupled logic line receiver. a switch coupled to a receiver to provide a current signal in response to the switching signal; 4. An analog display circuit according to claim 3, further comprising a differential amplifier which, upon generation of a signal, provides said current output to said current/voltage converter circuit. 5 the intensity signal generator comprises means for varying the level of the intensity control signal, the intensity of the plurality of pixels displayed according to the pixel category of each channel being adjusted by the corresponding intensity control; An analog display circuit according to claim 1, characterized in that it can be varied independently under the control of a signal. 6. The analog display device according to claim 1, further comprising a display drive circuit connected to the CRT and connected to receive a synchronization signal to generate a sweep signal in response to the synchronization signal.
display circuit. 7. The display driving circuit includes a linear amplifier having an input terminal and an output terminal, a first terminal connected to the output terminal of the linear amplifier at a first coupling point, a second terminal and a third terminal. a capacitor having a first terminal connected to the first node and a second terminal connected to the third terminal of the transistor at a second node; a deflection yoke for generating the sweep signal, the deflection yoke having a first terminal connected to the second coupling point and a second terminal connected to the input terminal of the linear amplifier; a resistor having a first terminal connected to a terminal and a second terminal connected to a reference potential; switching means connected to the second terminal of the transistor and connected to receive the synchronization signal; The analog transistor according to claim 6, characterized in that the switching means turns on and off the transistor according to the synchronization signal.
display circuit. 8 an analog circuit for driving the first, second and third color guns of the CRT of the raster display device connected to receive three display signals for each pixel of the image to be displayed; a display circuit, comprising: intensity control signal generation means for generating a plurality of intensity control signals; and an intensity control signal generation means connected to the signal generation means and connected to receive three display signals;
first, second, and third amplifier circuits that generate first, second, and third drive signals, respectively, in response to one display signal and the intensity control signal; a third amplifier circuit is connected to a corresponding one of the first, second and third color guns of the CRT, and each amplifier circuit is connected to the intensity control signal generating means; a plurality of channels connected to receive a corresponding one of the three display signals to generate a current output signal in response to one of the display signal and the intensity control signal; a plurality of channels and said corresponding one of said first, second and third color guns of said CRT, said first, second and third color guns in response to said current output signal; a current/voltage converter circuit for generating a corresponding one of the drive signals, each of the plurality of channels having a differential line input, and the number of channels is equal to or greater than the number of channels.
Corresponding to the number of different pixel categories that can be displayed on a CRT screen,
The display signal for each pixel is input only to the differential line input of a selected one of the plurality of channels according to the pixel category to be displayed on the screen, An analog display circuit, wherein only the selected one channel of the analog display circuit generates the current output signal. 9. Each of the plurality of channels includes: a digital-to-analog converter circuit connected to receive one of the intensity control signals to generate a voltage output in response to the received intensity control signal; a digital/analog converter circuit;
connected to the current/voltage converter circuit and the differential line input of the channel in response to the voltage output signal of the digital/analog converter circuit when the differential line input receives the display signal; a current switching circuit for providing the current output signal, the level of the current output signal varying in response to the intensity control signal input to the digital-to-analog converter; 9. The analog display circuit of claim 8, wherein the intensities of said plurality of pixels displayed in response to said plurality of pixels vary under control of said intensity control signal. 10. The analog display circuit according to claim 9, wherein the current switching circuit is an emitter-coupled logic circuit. 11. The current switching circuit includes: an emitter-coupled logic line receiver connected to the differential line input and generating a switching signal when the differential line input receives the display signal; and the emitter-coupled logic line receiver. a switch coupled to a receiver to provide a current signal in response to the switching signal; 11. An analog display circuit according to claim 10, further comprising a differential amplifier which, upon generating a signal, provides said current output to said current/voltage converter circuit. 12 the intensity signal generator comprises means for varying the level of the intensity control signal, the intensity of the plurality of pixels displayed according to the pixel category of each channel being adjusted by the corresponding intensity control; 9. An analog display circuit according to claim 8, characterized in that it can be changed under the control of a signal. 13. The analog display according to claim 8, further comprising a display drive circuit connected to the CRT and connected to receive a synchronization signal to generate a sweep signal in response to the synchronization signal. circuit. 14 The display driving circuit includes a linear amplifier having an input terminal and an output terminal, a first terminal connected to the output terminal of the linear amplifier at a first coupling point, a second terminal and a third terminal. a capacitor having a first terminal connected to the first node and a second terminal connected to the third terminal of the transistor at a second node; a deflection yoke for generating the sweep signal, the deflection yoke having a first terminal connected to the second coupling point and a second terminal connected to the input terminal of the linear amplifier; a resistor having a first terminal connected to a terminal and a second terminal connected to a reference potential; switching means connected to the second terminal of the transistor and connected to receive the synchronization signal; 14. The analog display circuit according to claim 13, wherein the switching means turns on and off the transistor according to the synchronization signal. 15. Each of the plurality of channels includes: a digital-to-analog converter circuit connected to receive one of the intensity control signals to generate a voltage output in response to the received intensity control signal; a digital/analog converter circuit;
connected to the current/voltage converter circuit and the differential line input of the channel in response to the voltage output signal of the digital/analog converter circuit when the differential line input receives the display signal; a current switching circuit for providing the current output signal, the level of the current output signal varying in response to the intensity control signal input to the digital-to-analog converter; 14. The analog display circuit of claim 13, wherein the intensities of said plurality of pixels displayed according to category vary under control of said intensity control signal. 16. The analog display circuit according to claim 15, wherein the current switching circuit is an emitter-coupled logic circuit. 17. The current switching circuit includes: an emitter-coupled logic line receiver connected to the differential line input to generate a switching signal when the differential line input receives the display signal; and the emitter-coupled logic line receiver. a switch coupled to a receiver to provide a current signal in response to the switching signal; 17. An analog display circuit according to claim 16, further comprising: a differential amplifier which, upon generating a signal, provides said current output to said current/voltage converter circuit. 18 The intensity signal generator comprises means for varying the level of the intensity control signal, and the intensity of the plurality of pixels displayed according to the pixel category of each channel is controlled by the corresponding intensity control signal. The analog signal according to claim 17, characterized in that it can be changed under the control of the signal.
display circuit. 19 connected to receive a plurality of display signals corresponding to a plurality of pixels to be displayed and to display a raster image in response to said display signals;
Analog that drives the CRT of a display device
a display circuit connected to said means for providing said plurality of voltage output signals to receive said voltage output signal and said display signal, and to generate a current output signal in response to said voltage output signal and each display signal; a plurality of current switching means; the plurality of current switching means and the CRT;
and a plurality of current/voltage converter means connected to the plurality of current switching means for converting the current output signal outputted from the plurality of current switching means into a corresponding drive signal for driving the CRT. analog display circuit. 20, further comprising: means for generating a plurality of variable intensity control signals, the means for generating a plurality of voltages being connected to the means for generating a plurality of variable intensity control signals; a plurality of digital-to-analog converter means each connected to a current switching means, said plurality of digital-to-analog converter means receiving said variable strength control signal to control a corresponding one of said plurality of current switching means; one current switching means is provided with the voltage output signal, the voltage output signal varies in response to the variable intensity control signal, and the drive signal output from the plurality of current/voltage converter means is connected to the CRT. 20. An analog display circuit as claimed in claim 19, characterized in that the analog display circuitry of claim 19 changes to vary the intensity of a portion of the display on said screen. 21 each of said plurality of digital-to-analog converter means comprises a plurality of digital-to-analog converter circuits connected to said plurality of variable strength control signal generating means, said plurality of digital-to-analog converters a circuit outputs one of the voltage output signals to the digital-to-analog converter circuits in response to the variable intensity control signal, each of the digital-to-analog converter circuits being displayed on the screen of the CRT; a plurality of current switching means each having a differential line input capable of receiving a corresponding one of said display signals; current switching circuits, the plurality of current switching circuits connecting the digital/analog converter circuit to receive the voltage output signal of the digital/analog converter circuit;
21. Generating the current output signal in response to one of the current switching circuits connected to the converter circuit and receiving the display signal on the differential line input. analog display circuit. 22. The analog display of claim 21, further comprising drive means connected to receive a synchronization signal and connected to the CRT to generate a sweep signal to control scanning of the CRT. circuit. 23 The driving means includes a linear amplifier having an input terminal and an output terminal, a first terminal connected to the output terminal of the linear amplifier at a first coupling point, a second terminal and a third terminal. a capacitor having a first terminal connected to the first node and a second terminal connected to the third terminal of the transistor at the second node; a deflection yoke for generating the sweep signal, the deflection yoke having a first terminal connected to a second coupling point and a second terminal connected to the input terminal of the linear amplifier; a resistor having a first terminal connected to and a second terminal connected to a reference potential; switching means connected to the second terminal of the transistor and connected to receive the synchronization signal; 23. The analog display circuit according to claim 22, wherein the switching means turns on and off the transistor according to the synchronization signal.