JPH0250363A - Digital signal processor - Google Patents

Abstract

PURPOSE:To absorb jitters without the control of an allowable maximum phase shift quantity due to the sampling cycle of an input signal by determining the delay quantity of a delay means to operate the input digital signal with the phase shift quantity between the input digital signal and an internal clock. CONSTITUTION:A phase detector 9 detects the phase condition between an input clock signal 2 and a data latch signal 3 as the internal clock, and outputs address control signals 10 and 11 corresponding to the phase difference between them. Change-over switches 17 and 18 interposed between delay elements 14 and 15 and delay elements 15 and 16 are switched by the address control signals 10 and 11, and operate as address control circuits 19 to switch the write position of an input digital signal 1 to a delay means 13 according to the output of the phase detector 9. Consequently, the delay quantity can be determined by the phase shift quantity between the input digital signal and the internal clock. Thus, the digital signal processing which is not controlled by the sampling cycle of the input digital signal is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital signal processing device that absorbs jitter components of a signal.

2. Description of the Related Art In recent years, digital processing technology has been widely used in the fields of audio, video, and information processing. Particularly in the field of digital audio, jitter components generated in a digital signal transmission system have a very large effect on sound quality, and digital signal processing devices that absorb the jitter components are used. Figure 5 shows a conventional digital signal processing device.
The bit-parallel input digital signal 1 and the input clock signal 2 synchronized therewith contain jitter as shown in the signal waveform shown in FIG. 6 (aHb), and the period Tn (n= 0°1.2...
) vary greatly depending on the data.

If such a parallel data signal with large jitter is directly input to a D/A converter and converted into an audio signal, each signal period Tn (n=0.1.2...)
This variation causes waveform distortion in the time axis direction, which adversely affects audio characteristics. Therefore, in Fig. 5, the jitter component of input clock signal 2 is absorbed to create a data line with less jitter.
A PLL circuit 4 for creating a y-child signal 3, and an m-bit input digital signal 1 for latching the m-bit input digital signal 1 with a data latch signal 3 generated at the output of the PLL circuit 4 to output an m-bit parallel output digital signal 5. Register group 6
and is provided. FIG. 6(C) shows the data latch signal 3. Comparing FIGS. 6(b) and (C), the data latch signal 3 uses the PLL circuit 4 to absorb the jitter of the input clock signal 2. Therefore, the period is always a substantially constant value t.

Since the m-bit parallel output digital signal 5 shown in FIG. 6(d) is a signal obtained by latching the m-bit input digital signal 1 by the rising edge of the data latch signal 3, it is the same as the data latch signal 3. Since the period is almost constant, and the output digital signal 5 has a constant period, it has very little jitter and no waveform distortion in the time axis direction occurs during D/A conversion.

Problems to be Solved by the Invention In such a conventional configuration, assuming that the response frequency of the PLL circuit 4 is made very slow and the data latch signal 3 has almost no jitter, the sampling period of the m-bit input digital signal 1 is When is T, if the amount of phase shift between m-bit input digital signal 1, data latch signal 3, and m-bit output digital signal 5 exceeds ±(T/2), synchronization will occur and incorrect data will be latched. be done.

An object of the present invention is to provide a digital signal processing device in which the maximum permissible phase shift between an m-bit input digital signal and an m-bit output digital signal is not limited by the sampling period of the m-bit input digital signal.

Means for Solving the Problems The digital signal processing device of the present invention is constructed by connecting a phase detector that detects the phase state of an input signal and an internal clock signal, and a plurality of delay elements in series. It includes a delay means for successively delaying an input digital signal, and an address control circuit for switching the write position of the input digital signal to the delay means according to the output of the phase detector, and jitters the output signal of the final stage delay element. It is characterized in that it is output as an absorbed output digital signal.

Effect: According to this configuration, the amount of delay of the delay means acting on the input digital signal is switched by the phase detector and the address control circuit. Therefore, the amount of delay is determined by the amount of phase shift between the input digital signal and the internal clock signal, and the output digital signal is subjected to jitter absorption processing without becoming discontinuous.

EXAMPLE Hereinafter, an example of the present invention will be described based on FIGS. 1 to 4. Components having the same functions as those in FIG. 5 showing the conventional example will be described with the same reference numerals.

In FIG. 1, a digital signal processing device 8 of the present invention having a jitter absorption function is provided upstream of the digital filter section 7. The phase detector 9 of the digital signal processing device 8 detects the phase states of the input clock signal 2 and the data latch signal 3 as an internal clock, and outputs address control signals io and il according to the phase difference between the two. Also,
Phase detector 9 uses reset signal 12 to reset address control signals 10 and 11 to initial values. The delay means 13 for delaying the input digital signal 1 is composed of m-bit parallel delay elements 14, 15, and 16 connected in series. Changeover switches 17, 18 are interposed.

Changeover switches 17 and 18 are address control signals 10 and 11.
It functions as an address control circuit 19 that switches the writing position of the input digital signal 1 to the delay means 13 in accordance with the output of the phase detector 9. Here, delay elements 14 and 16 latch data at the falling edge of data latch signal 3, and delay element 15 latches data at the rising edge of data latch signal 3.

The digital filter section 7 is composed of m-bit parallel delay elements 20 to 23, multipliers 24 to 28, and an accumulator 29, which are used for filtering calculations. Delay elements 20-23 latch data at the rising edge of data latch signal 3.

an accumulator 29 that adds the outputs of the multipliers 24 to 28;
The calculation result 30 of the digital filter section 7 is output as ρ
Output in bits. FIG. 2 shows the timing when the address for writing the input digital signal 1 to the delay means 13 is initially reset by the reset signal 12. Immediately after the initial reset by the reset signal 12, the input data write address is set to the delay element 15. The changeover switch 17 in FIG. 1 is set to the upper side, the changeover switch 18 is set to the lower side, and the input digital signal 1 is first written to the delay element 15. After that, delay element 1
6. The second zero-order signal is sequentially shifted to the delay element 20.
From the state shown in the figure, the phase of the input clock signal 2 gradually advances the phase of the data latch signal 3, and the state in which it has advanced by more than T/2 is shown in Figure 3.As is clear from this figure, Since the delay element 15 latches the input digital signal 1 at the rising edge of the data latch signal 3,
At the timing shown in FIG. 3, if the input data write address is not changed, the m-th data Dm will not be latched and will be missed. Therefore, one cycle from the rise to the rise of the data latch signal 3 The phase detector 9 detects that the input clock signal 2 falls twice during the period A, and sets the changeover switches 17 and 18 to the lower side by the address control signal 10°11 to delay the data write address. Switching from element 15 to delay element 14 is performed. As a result, the human-powered digital signal 1 is first written to the delay element 14, and then sequentially shifted to the delay element 15, the delay element 16, and the delay elements 20 to 23. Then, by switching the input data write address as described above, the Dm without missing the delay element 20~
Transferred to 23.

When the phase of the input clock signal 2 gradually lags behind the phase of the data latch signal 3 by more than T/2 from the state shown in FIG. 2, the state shown in FIG. 4 occurs. In this case, if the data write address is left as the delay element 15, the Ω-th data D of the input digital signal 1 will be latched twice, resulting in a discontinuous data arrangement. Therefore, the phase detector 9 detects that the input clock signal 2 did not fall even once during one cycle from the rise to the rise of the data latch signal 3, and the changeover switch 1 is detected by the address control signal 11.
8 to the upper side to switch the data write address from delay element 15 to delay element 16. As a result, the input digital signal 1 is first written to the delay element 16,
The input digital signal 1 is sequentially shifted to the delay elements 20 to 23, and by switching the input data write address as described above, the input digital signal 1 is transferred to the digital filter section 7 without discontinuous data arrangement. Ru.

By repeating this operation, even if the phase shift between the input clock signal 2 and the data latch signal 3 exceeds ±T/2, the data can be transferred to the digital filter section 7 without becoming discontinuous. Ru. Inside the digital filter section 7, delay elements 20 to 23 and a multiplier 2
4 to 28, filtering calculations are performed by the accumulator 29.

In the above embodiment, the same m-bit parallel delay elements 20 to 23 used in the digital filter section 7 are used.
Bit-parallel delay elements 14 to 16 can be used to absorb jitter, and when RAM is used as a delay element to form the digital filter section 7, the remaining RAM portion of the integrated circuit can be used effectively. It can be used and configured.

In the above embodiment, a case has been described in which the number of delay elements for absorbing jitter is three, but it is possible to increase the allowable maximum phase shift amount by not increasing the number of delay elements.

The phase comparator of the above embodiment has input clock signal 2 and P
Although the data latch signal 3 generated by the LL circuit 4 was compared, the same is true when comparing the signal obtained by detecting the state of change of the input digital signal 1 with the data latch signal as an internal clock signal.

Effects of the Invention As described above, according to the present invention, the phase detector configured to detect the phase state of an input signal and an internal clock signal, and a plurality of delay elements connected in series, is configured to detect the input digital signal of the input signal. and an address control circuit that switches the writing position of the input digital signal to the delay means according to the output of the phase detector, and the output signal of the final stage delay element is outputted from a jitter-absorbed circuit. Since it is output as an output digital signal, the delay amount of the delay means that acts on the input digital signal is determined by the amount of phase shift between the input digital signal and the internal clock, and the maximum allowable phase shift amount is not limited by the sampling period of the input signal. Therefore, it is possible to perform jitter absorption over a very wide range and obtain an output data signal with very little jitter.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of the digital signal processing device of the present invention, FIGS. 2, 3, and 4 are timing charts of each signal in each state of the device, and FIG. 5 is a conventional digital signal processing device. FIG. 6 is a timing chart of the same device. 1... Input digital signal, 2... Input clock signal, 3... Data latch signal [internal clock], 5...
... Output digital signal, 9... Phase detector, 13.
...Delay means, 14-16...Delay element, 19...
Address control circuit. Agent Yoshihiro Morimoto

Claims (1)

[Claims] 1. A phase detector that detects the phase state of an input signal and an internal clock signal; a delay means that is configured by connecting a plurality of delay elements in series and sequentially delays an input digital signal among the input signals; and the phase detector. and an address control circuit that switches the writing position of the input digital signal to the delay means according to the output of the delay element, and outputs the output signal of the final stage delay element as an output digital signal with jitter absorbed.