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JPH0249651Y2 - - Google Patents

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Publication number
JPH0249651Y2
JPH0249651Y2 JP1985171626U JP17162685U JPH0249651Y2 JP H0249651 Y2 JPH0249651 Y2 JP H0249651Y2 JP 1985171626 U JP1985171626 U JP 1985171626U JP 17162685 U JP17162685 U JP 17162685U JP H0249651 Y2 JPH0249651 Y2 JP H0249651Y2
Authority
JP
Japan
Prior art keywords
layer
plating
solder
base metal
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1985171626U
Other languages
Japanese (ja)
Other versions
JPS6279368U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985171626U priority Critical patent/JPH0249651Y2/ja
Publication of JPS6279368U publication Critical patent/JPS6279368U/ja
Application granted granted Critical
Publication of JPH0249651Y2 publication Critical patent/JPH0249651Y2/ja
Expired legal-status Critical Current

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  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Description

【考案の詳細な説明】 産業上の利用分野 この考案は配線基板上の導線間の電気的接続に
用いるジヤンパーチツプに関する。
[Detailed Description of the Invention] Industrial Application Field This invention relates to a jumper chip used for electrical connection between conductive wires on a wiring board.

従来の技術 従来のジヤンパーチツプは第4図に示す構成に
ある。
Prior Art A conventional jumper chip has the configuration shown in FIG.

基板1の表面および裏面端部には銀パラジウム
の第1導体層2、第2導体層3が印刷形成されて
いる。さらに基板側面に銀パラジウムの第3導体
層4が印刷形成されている。これらの導体層はガ
ラスなどの保護膜6で覆われた部分を除き、金属
メツキ層5を介して半田層7で覆われている。
A first conductor layer 2 and a second conductor layer 3 made of silver-palladium are printed on the front and back edges of the substrate 1. Further, a third conductor layer 4 of silver palladium is printed on the side surface of the substrate. These conductor layers are covered with a solder layer 7 via a metal plating layer 5, except for the portion covered with a protective film 6 such as glass.

考案が解決しようとする問題点 しかしながら、上記構成のジヤンパーチツプは
第1導体層2、第2導体層3、第3導体層4、金
属メツキ層5、保護膜6、半田層7からなる複雑
な多層構造をしているため、厚膜の印刷、焼成の
ための工程を多く要して歩留が向上せず、また高
価な銀パラジウムの使用や焼成に光熱費が多くか
かりコストアツプを招くといつた問題を生じてい
た。
Problems to be Solved by the Invention However, the jumper chip with the above structure has a complex multilayer structure consisting of a first conductor layer 2, a second conductor layer 3, a third conductor layer 4, a metal plating layer 5, a protective film 6, and a solder layer 7. Because of the structure, many processes are required for thick film printing and firing, which does not improve yield, and also increases costs due to the use of expensive silver-palladium and high utility costs for firing. It was causing problems.

この考案はこのような問題点に鑑み、構成を簡
素化することにより歩留の向上およびコスト低減
を図ることのできるジヤンパーチツプを提供する
ことを目的としている。
In view of these problems, the object of this invention is to provide a jumper chip that can improve yield and reduce cost by simplifying the structure.

問題点を解決するための手段 この考案は、前記の目的を達成するために、絶
縁性基板の表面から裏面の両端部にかけ基体金属
層を形成し、かつその基体金属層の表面にスズま
たは半田メツキを施したことを特徴とする。
Means for Solving the Problems In order to achieve the above object, this invention forms a base metal layer from the front surface to both ends of the back surface of an insulating substrate, and coats the surface of the base metal layer with tin or solder. It is characterized by the fact that it has been plated.

作 用 本考案に係るジヤンパーチツプは基体金属層と
スズまたは半田のメツキ層からなる2層構造であ
り、前者の層はメツキ層の接着性を高めるのに寄
与する。
Function The jumper chip according to the present invention has a two-layer structure consisting of a base metal layer and a plating layer of tin or solder, and the former layer contributes to improving the adhesiveness of the plating layer.

実施例 第1図は本考案の一実施例であるジヤンパーチ
ツプの断面図である。
Embodiment FIG. 1 is a sectional view of a jumper chip which is an embodiment of the present invention.

図において、符号10はアルミナ等の絶縁性材
料からなる長方形状基板である。符号20は基板
の表面から裏面の両端部にかけ無電解メツキによ
り形成された基体金属層である。基体金属層20
の表面はスズまたは半田メツキによるメツキ層3
0で覆われている。基体金属層20はスズまたは
半田のメツキとの接着性を良好にするためのもの
であつて、該メツキとの接着強度に優れたニツケ
ル等を使用する。ニツケルは基板10との密着性
にも優れており基体金属として好ましい。基体金
属層20、メツキ層30の層厚は5〜10μmであ
る。以上のように、ニツケルやスズまたは半田の
メツキ層で構成されており、銀パラジウムの厚膜
形成に比べ材料コストが安価になる。
In the figure, reference numeral 10 is a rectangular substrate made of an insulating material such as alumina. Reference numeral 20 denotes a base metal layer formed by electroless plating from the front surface to both ends of the back surface of the substrate. Base metal layer 20
The surface is a plating layer 3 made of tin or solder plating.
Covered with 0. The base metal layer 20 is intended to have good adhesion to tin or solder plating, and is made of nickel or the like which has excellent adhesive strength to the plating. Nickel also has excellent adhesion to the substrate 10 and is preferable as the base metal. The thickness of the base metal layer 20 and the plating layer 30 is 5 to 10 μm. As described above, it is composed of a plating layer of nickel, tin, or solder, and the material cost is lower than that of forming a thick film of silver-palladium.

第3図はこのジヤンパーチツプの実装状態を示
している。51〜53は回路基板50上で交叉す
る導線である。中間の導線51を跨ぐように、対
向する導線52と53上にジヤンパーチツプを載
置し、加熱された半田60をチツプ側面に載せる
とメツキ層30のスズまたは半田と溶けあい、導
線52と53導線51と短絡することなく、基体
金属層20およびメツキ層30を介して導通す
る。
FIG. 3 shows the mounting state of this jumper chip. 51 to 53 are conducting wires that intersect on the circuit board 50. A jumper chip is placed on the opposing conductors 52 and 53 so as to straddle the middle conductor 51, and when heated solder 60 is placed on the side of the chip, it melts with the tin or solder of the plating layer 30, and the conductors 52 and 53 51, conduction is established through the base metal layer 20 and the plating layer 30.

上記構成のジヤンパーチツプの製造工程を第2
図によつて説明する。
The manufacturing process of the jumper chip with the above configuration is carried out in the second step.
This will be explained using figures.

符号70はシート状のアルミナ基板である。
まず、この基板70の裏面にエポキシ系樹脂の
レジスト40を帯状に一定間隔をもつて平行に
複数形成する(第2図a参照)。続いて、各レ
ジスト帯別にブレーキングラインMに沿つて分
割する。この分割はあらかじめ基板に形成した
スリツトからブレーキングまたはデイスクスク
ライブによるカツト処理で行う(第2図b参
照)。
Reference numeral 70 is a sheet-like alumina substrate.
First, a plurality of epoxy resin resists 40 are formed in parallel strips at regular intervals on the back surface of the substrate 70 (see FIG. 2a). Subsequently, each resist band is divided along the breaking line M. This division is performed by cutting from slits previously formed in the substrate by braking or disk scribing (see FIG. 2b).

上記分割により得た帯状体に対しフツ酸によ
る表面処理を施した後、無電解メツキを行つて
ニツケルなどの基体金属層20を形成する(第
2図c参照)。同様に帯状体のまま電解メツキ
(バレルメツキ)によりスズまたは半田のメツ
キを施す(第2図d参照)。これらの工程で帯
状体の端面にもメツキが付くので、端末処理に
より両端部分を除去する。
After the strip obtained by the above division is subjected to surface treatment with hydrofluoric acid, electroless plating is performed to form a base metal layer 20 of nickel or the like (see FIG. 2c). Similarly, the strip is plated with tin or solder by electrolytic plating (barrel plating) (see FIG. 2d). Since plating is also applied to the end surfaces of the strip in these steps, both end portions are removed by end treatment.

次に、レジスト40の剥離処理を行つた後、
チツプ幅のブレーキングラインNに沿つてチツ
プ個々に分割する(第2図d参照)。なお、こ
のときの分割もで行つたブレーキングと同様
に行う。
Next, after performing a peeling process on the resist 40,
Divide the chips into individual chips along the breaking line N of the chip width (see Figure 2d). Note that the division at this time is also performed in the same way as the braking performed in .

上記のようにレジスト40の塗布工程と、無電
解メツキおよび電解メツキの工程だけで製造でき
るので、厚膜形成のみによる場合と比べ印刷、焼
成工程を削減でき製造コストを低減できる。
As described above, since it can be manufactured using only the resist 40 coating process and the electroless plating and electrolytic plating processes, the printing and baking processes can be reduced and the manufacturing cost can be reduced compared to the case where only thick film formation is used.

考案の効果 本考案によれば、基体金属層とメツキ層の2層
構造により、材料コストを低減できるとともに、
製造工程数を削減し安価に製作することができ
る。
Effects of the invention According to the invention, the two-layer structure of the base metal layer and the plating layer reduces material costs, and
The number of manufacturing steps can be reduced and the product can be manufactured at low cost.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例であるジヤンパーチ
ツプの断面図、第2図a〜eは同ジヤンパーチツ
プの製造工程を説明するための図、第3図は同実
施例のジヤンパーチツプの使用状態を示す断面
図、第4図は従来のジヤンパーチツプの断面図で
ある。 10……絶縁性基板、20……基体金属層、3
0……(スズまたは半田の)メツキ層。
Figure 1 is a sectional view of a jumper chip that is an embodiment of the present invention, Figures 2 a to e are diagrams for explaining the manufacturing process of the jumper chip, and Figure 3 shows how the jumper chip of the embodiment is used. 4 is a cross-sectional view of a conventional jumper chip. 10... Insulating substrate, 20... Base metal layer, 3
0...Plated layer (of tin or solder).

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 絶縁性基板の表面から裏面の両端部にかけ基体
金属層を形成し、かつその基板金属層の表面にス
ズまたは半田メツキを施してなるジヤンパーチツ
プ。
A jumper chip in which a base metal layer is formed from the front surface to both ends of the back surface of an insulating substrate, and the surface of the substrate metal layer is plated with tin or solder.
JP1985171626U 1985-11-06 1985-11-06 Expired JPH0249651Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985171626U JPH0249651Y2 (en) 1985-11-06 1985-11-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985171626U JPH0249651Y2 (en) 1985-11-06 1985-11-06

Publications (2)

Publication Number Publication Date
JPS6279368U JPS6279368U (en) 1987-05-21
JPH0249651Y2 true JPH0249651Y2 (en) 1990-12-27

Family

ID=31107425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985171626U Expired JPH0249651Y2 (en) 1985-11-06 1985-11-06

Country Status (1)

Country Link
JP (1) JPH0249651Y2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0722059Y2 (en) * 1989-04-13 1995-05-17 コーア株式会社 The jumper chip
JP2545602Y2 (en) * 1989-12-14 1997-08-25 北陸電気工業株式会社 Jumper chip

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5673493A (en) * 1979-11-20 1981-06-18 Matsushita Electric Ind Co Ltd Chip part for jumber

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5673493A (en) * 1979-11-20 1981-06-18 Matsushita Electric Ind Co Ltd Chip part for jumber

Also Published As

Publication number Publication date
JPS6279368U (en) 1987-05-21

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