JPH0244151B2 - - Google Patents
Info
- Publication number
- JPH0244151B2 JPH0244151B2 JP60117049A JP11704985A JPH0244151B2 JP H0244151 B2 JPH0244151 B2 JP H0244151B2 JP 60117049 A JP60117049 A JP 60117049A JP 11704985 A JP11704985 A JP 11704985A JP H0244151 B2 JPH0244151 B2 JP H0244151B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- input
- gate
- mosfet
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 8
- 230000015556 catabolic process Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 239000000969 carrier Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electronic Switches (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体集積回路の入力保護回路に関す
るもので、特に高電圧が入力端子に入力されるお
それのある場合に、その高電圧が内部回路に印加
されないようにするための回路に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an input protection circuit for a semiconductor integrated circuit, and in particular, when there is a risk that a high voltage may be input to an input terminal, the high voltage may be applied to an internal circuit. This relates to a circuit for preventing voltage from being applied.
従来のこの種の入力保護回路は、例えば第３図
に示すように構成されていた。即ち、入力端子３
に一端が接続され、他端が集積回路の内部回路１
１，１２に接続された入力抵抗１７と、ドレイン
が入力抵抗１７の他端に接続されたｎチヤンネル
MOSFET１６とを備え、FET１６のソースおよ
び基板はアース２に接続されていた。第４図に示
すように入力端子３の電圧V3が高くなつて例え
ば＋20Vになると、FET１６の基板−ドレインに
より構成されるＰ−Ｎ接合の逆方向ブレークダウ
ンを生じさせ、節点１５の電位V15が逆方向ブレ
ークダウン電圧（図示の例では10V程度）より高
くはならないようにしていた。一方、−20Vが入
力されたときには、基板−ドレインのＰ−Ｎ接合
が順方向にバイアスされることを利用し、節点１
５の電位が略0Vとなる（正確には0Vよりも、Ｐ
−Ｎ接合の降下分だけ低い値）となるようにして
いた。しかるに、Ｐ−Ｎ接合のブレークダウン電
圧は、基板の不純物濃度に依存するが、精度良く
制御することが困難であり、上記のような入力保
護回路には、次のような欠点があつた。
A conventional input protection circuit of this type has been configured as shown in FIG. 3, for example. That is, input terminal 3
One end is connected to the internal circuit 1 of the integrated circuit, and the other end is connected to the internal circuit 1 of the integrated circuit.
1 and 12, and an n-channel whose drain is connected to the other end of the input resistor 17.
The source of the FET 16 and the substrate were connected to the ground 2. As shown in FIG. 4, when the voltage V3 at the input terminal 3 increases to, for example, +20V, a reverse breakdown of the P-N junction formed by the substrate-drain of the FET 16 occurs, and the potential V3 at the node 15 15 was made not to exceed the reverse breakdown voltage (approximately 10V in the example shown). On the other hand, when -20V is input, the node 1 is
The potential of 5 becomes approximately 0V (more precisely than 0V, P
-A value lower by the drop of the N junction). However, the breakdown voltage of the PN junction, which depends on the impurity concentration of the substrate, is difficult to control accurately, and the input protection circuit as described above has the following drawbacks.
(イ) 入力端子に正の高電圧が入力されたときに、
内部回路に印加される電圧を、電源電圧以下に
は抑えられなかつた。即ち、Ｐ−Ｎ接合の逆方
向ブレークダウン電圧が内部回路１１，１２の
動作電圧よりも高い場合には、その動作電圧よ
りも高い電圧が内部回路に加わるのを避けるこ
とができなかつた。(a) When a positive high voltage is input to the input terminal,
The voltage applied to the internal circuit could not be suppressed below the power supply voltage. That is, when the reverse breakdown voltage of the PN junction is higher than the operating voltage of the internal circuits 11 and 12, it is impossible to avoid applying a voltage higher than the operating voltage to the internal circuit.
(ロ) Ｐ−Ｎ接合の逆方向ブレークダウンを利用し
ているため、正の高電圧の印加が頻繁に起こる
場合に、装置の寿命を縮める。(b) Since the reverse breakdown of the PN junction is utilized, the life of the device will be shortened if a high positive voltage is frequently applied.
(ハ) 内部回路のMOSFET１１，１２に、そのゲ
ート酸化膜の耐圧以上の電圧が加わるおそれが
あつた。ゲート酸化膜の耐圧は、プロセスの微
細化に伴い低くなる傾向があり、ゲート長が
2μの場合、ゲート酸化膜の耐圧は7V程度であ
る。一方、FET１６の基板−ドレイン間のＰ
−Ｎ接合の逆方向ブレークダウン電圧は基板の
濃度に依存するが、精度よく制御することが難
しい。(c) There was a risk that a voltage higher than the withstand voltage of the gate oxide film would be applied to MOSFETs 11 and 12 in the internal circuit. The breakdown voltage of gate oxide films tends to decrease as the process becomes finer, and the gate length increases.
In the case of 2μ, the breakdown voltage of the gate oxide film is about 7V. On the other hand, P between the substrate and drain of FET16
The reverse breakdown voltage of the -N junction depends on the concentration of the substrate, but it is difficult to control with precision.
本発明の目的は、ゲート酸化膜の耐圧が電源電
圧に近い場合にも、内部回路を十分に保護するこ
とができ、寿命も長い入力保護回路を提供するこ
とにある。
An object of the present invention is to provide an input protection circuit that can sufficiently protect an internal circuit even when the withstand voltage of a gate oxide film is close to the power supply voltage and has a long life.
本発明の入力保護回路は、ドレインが電源に接
続され、ゲートおよびソースが前記入力抵抗に接
続された第１導電形の第１のMOSFETと、ゲー
トが電源に接続された前記第１導電形の第２の
MOSFETと、一端が電源に接続され、他端が前
記第２のMOSFETのドレイン−ソース回路を介
して前記入力抵抗に接続された負荷素子とを備
え、前記負荷素子の他端が前記内部回路に接続さ
れていることを特徴とするものである。
The input protection circuit of the present invention includes a first MOSFET of a first conductivity type whose drain is connected to a power supply, and whose gate and source are connected to the input resistor; second
MOSFET, and a load element having one end connected to a power supply and the other end connected to the input resistor via the drain-source circuit of the second MOSFET, the other end of the load element being connected to the internal circuit. It is characterized by being connected.
本発明の一実施例を第１図に示す。図示のよう
に、この実施例の入力保護回路は、入力抵抗７と
第１導電形、例えばｎ−チヤンネル形の第１およ
び第２のMOSFET８，９と負荷素子１０とを有
する。第１のMOSFET８はドレインが電源１に
接続され、ゲートおよびソースは共通接続されて
入力抵抗７を介して入力端子３に接続されてい
る。第２のMOSFET９は、ゲートが電源１に接
続されている。負荷素子１０は一端が電源１に接
続されている。第１のMOSFET８のゲートおよ
びドレインは第２のMOSFET９を介して負荷素
子１０の他端に接続されるとともに集積回路の内
部回路１１，１２に接続されている。負荷素子１
０としては、図示の実施例では第２導電形例えば
ｐ−チヤンネル形のMOSFETが用いられ、その
ゲートがアースに接続されている。
An embodiment of the present invention is shown in FIG. As shown in the figure, the input protection circuit of this embodiment includes an input resistor 7, first and second MOSFETs 8 and 9 of a first conductivity type, for example, an n-channel type, and a load element 10. The drain of the first MOSFET 8 is connected to the power supply 1, and the gate and source are commonly connected and connected to the input terminal 3 via the input resistor 7. The gate of the second MOSFET 9 is connected to the power supply 1. One end of the load element 10 is connected to the power supply 1. The gate and drain of the first MOSFET 8 are connected to the other end of the load element 10 via the second MOSFET 9, and are also connected to internal circuits 11 and 12 of the integrated circuit. Load element 1
In the illustrated embodiment, a MOSFET of a second conductivity type, for example, a p-channel type, is used as the MOSFET, and its gate is connected to ground.
上記の回路は以下のように動作する。 The above circuit operates as follows.
(イ) 入力信号の電圧V3がVCC＋VTHN8（VCCは電源
１の電圧、VTH8はFET８のしきい値電圧）よ
りも高い場合。(a) When the input signal voltage V 3 is higher than V CC + V THN8 (V CC is the voltage of power supply 1, V TH8 is the threshold voltage of FET 8).
この場合、FET８は導通状態となる。FET
８は導通状態の抵抗が入力抵抗７より十分小さ
くしてあり、このため、節点４の電圧V4は
V4≒VCC＋VTHN8
今、
VCC＝5V
VTHN8＝3V
V3＝20V
とすると、V4≒8Vとなり、FET８のゲート−
ドレイン間にはVTHN8に相当する3Vが加わるだ
けである。また、FET９のゲートはVCC＝5V
であるので、そのゲート−ドレイン間にも3V
が加わるだけである。また節点５の電圧V5は、
FET９によりVCC以下に抑えられるとともに
FET１０によりVCCにプルアツプされているの
で、VCCである。即ち、VCCよりも高くなるこ
とはない。従つて、内部回路１１，１２のゲー
トに加わる電圧もVCC＝5V以下に抑えられる。 In this case, FET8 becomes conductive. FET
8, the conductive state resistance is sufficiently smaller than the input resistance 7, so the voltage V 4 at node 4 is V 4 ≒ V CC +V THN8 Now, V CC = 5V V THN8 = 3V V 3 = 20V , V 4 ≒ 8V, and the gate of FET8 -
Only 3V corresponding to V THN8 is applied between the drains. Also, the gate of FET9 is V CC =5V
Therefore, 3V is also applied between the gate and drain.
is only added. Also, the voltage V 5 at node 5 is
FET9 suppresses the voltage below V CC and
It is pulled up to V CC by FET 10, so it is V CC . That is, it never becomes higher than V CC . Therefore, the voltage applied to the gates of internal circuits 11 and 12 is also suppressed to V CC =5V or less.
一方、負荷素子として用いられているｐチヤ
ンネルMOSFET１０はゲートがアースに接続
されているので、ゲート−ソース間の電圧も
VCC＝5V以下に抑えられる。 On the other hand, since the gate of the p-channel MOSFET 10 used as a load element is connected to ground, the voltage between the gate and source is also
V CC can be kept below 5V.
第２図には、入力端子３の電圧V3が20Vの
ときの、節点４、節点５の電圧V4，V5が示さ
れている。 FIG. 2 shows voltages V 4 and V 5 at nodes 4 and 5 when voltage V 3 at input terminal 3 is 20V.
(ロ) VCC＋VTHN8＞V3＞VCCの場合。(b) When V CC +V THN8 > V 3 > V CC .
この場合、FET８は導通しないが、節点４
の電圧V4と電源１の電圧VCCとの差はVTHN8以
下であるので、FET９のゲート−ドレイン間
の電圧はVTHN8（例えば3V）以下である。一方、
節点５の電圧V5は、(イ)の場合と同様でVCC＝
5Vよりも高くならない。 In this case, FET8 is not conductive, but node 4
Since the difference between the voltage V 4 and the voltage V CC of the power supply 1 is less than V THN8 , the voltage between the gate and drain of the FET 9 is less than V THN8 (for example, 3V). on the other hand,
The voltage V 5 at node 5 is the same as in case (a), and V CC =
It cannot go higher than 5V.
(ハ) 入力信号の電圧V3が０の場合。(c) When the input signal voltage V3 is 0.
FET１０はｐチヤンネル形で、ゲートが接
地されているので、導通状態にあり、また、
FET９はゲートに電源電圧VCCが印加されてい
るため導通状態にあるが、FET１０はFET９
に比べ導通状態における抵抗が大となるよう形
成されているため、節点５の電圧V5は略０と
なる。 FET10 is a p-channel type, and its gate is grounded, so it is in a conductive state, and
FET9 is in a conductive state because the power supply voltage V CC is applied to its gate, but FET10 is in a conductive state.
Since the resistance in the conductive state is larger than that in the conductive state, the voltage V 5 at the node 5 is approximately 0.
(ニ) 入力信号の電圧V3が負の場合。(d) When the input signal voltage V3 is negative.
この場合、FET８の基板−ソース間のＰ−
Ｎ接合、FET９の基板−ドレイン間のＰ−Ｎ
接合がともに順方向にバイアスされ、アースか
らこれらのＰ−Ｎ接合を通して、入力抵抗７、
入力端子３の経路で導通状態となり、節点４の
電圧V4はＰ−Ｎ接合の順方向降下分だけ０よ
り低い値にクランプされる。従つて、FET８
のゲート−ソース間にはＰ−Ｎ接合の順方向降
下分（通常1V以下）しか加わらず、ドレイン
−ゲート間にはＰ−Ｎ接合の順方向降下分と
VCCの和しか加わらない。このことは、V3の値
がいかに大きくてもあてはまる。第２図にはま
たV3＝−20Vの場合のV4，V5が示されている。 In this case, P- between the substrate and source of FET8
N junction, P-N between the substrate and drain of FET9
With the junctions forward biased together, an input resistor 7,
The path of the input terminal 3 becomes conductive, and the voltage V 4 at the node 4 is clamped to a value lower than 0 by the forward drop of the PN junction. Therefore, FET8
Only the forward drop of the P-N junction (usually 1 V or less) is applied between the gate and source of the circuit, and the forward drop of the P-N junction is applied between the drain and gate.
Only the sum of V CC is added. This is true no matter how large the value of V 3 is. FIG. 2 also shows V 4 and V 5 when V 3 =-20V.
以上のように本発明によれば正負いずれの高電
圧が入力端子に入力された場合にも、内部回路に
印加される電圧は電源電圧以下となる。また、入
力保護回路内のいずれのMOSFETにも、そのゲ
ート−ドレイン、ソース間にはほぼ電源電圧以下
の電圧しか加わらないようにすることができる。
従つて、ゲート酸化膜の破壊を避けることができ
る。また、Ｐ−Ｎ接合のブレークダウンを利用し
ていないので、装置の寿命を縮めることがない。
さらに、正の高電圧が入力されても、少数キヤリ
ア（ホール）が基板に注入されないため、ラツチ
アツプが生じない。
As described above, according to the present invention, even when either positive or negative high voltage is input to the input terminal, the voltage applied to the internal circuit is equal to or lower than the power supply voltage. Further, it is possible to apply only a voltage substantially less than the power supply voltage to any MOSFET in the input protection circuit between its gate, drain, and source.
Therefore, destruction of the gate oxide film can be avoided. Furthermore, since breakdown of the PN junction is not utilized, the life of the device will not be shortened.
Furthermore, even if a high positive voltage is input, no latch-up occurs because minority carriers (holes) are not injected into the substrate.
第１図は本発明の入力保護回路の一実施例を示
す回路図、第２図は第１図の回路の各節点の電圧
を示す図、第３図は従来の入力保護回路の一例を
示す回路図、第４図は第３図の回路の各節点の電
圧を示す図である。
１……電源、３……入力端子、７……入力抵
抗、８，９……ｎ−チヤンネルMOSFET、１０
……ｐ−チヤンネルMOSFET。
FIG. 1 is a circuit diagram showing an embodiment of the input protection circuit of the present invention, FIG. 2 is a diagram showing voltages at each node of the circuit in FIG. 1, and FIG. 3 is an example of a conventional input protection circuit. The circuit diagram, FIG. 4, is a diagram showing voltages at each node of the circuit of FIG. 3. 1...Power supply, 3...Input terminal, 7...Input resistance, 8, 9...n-channel MOSFET, 10
...p-channel MOSFET.
Claims (1)
スが前記抵抗の他端に接続された第１導電形の第
１のMOSFETと、 ゲートが電源に接続された前記第１導電形の第
２のMOSFETと、 一端が電源に接続され、他端が前記第２の
MOSFETのドレイン−ソース回路を介して前記
抵抗の他端に接続されると共に内部回路に接続さ
れた負荷素子とを備えた入力保護回路。 ２ 特許請求の範囲第１項記載の入力保護回路に
おいて、前記負荷素子は、ゲートがアースに接続
され、ドレインおよびソースが前記一端および他
端を構成する第２導電形のMOSFETであること
を特徴とする入力保護回路。 ３ 特許請求の範囲第１項または第２項に記載の
入力保護回路において、前記第１および第２の
MOSFETがともにｎチヤンネルMOSFETであ
り、その基板がアースに接続されていることを特
徴とする入力保護回路。[Claims] 1: an input terminal; a resistor having one end connected to the input terminal; and a first resistor of a first conductivity type having a drain connected to a power supply and a gate and a source connected to the other end of the resistor. a second MOSFET of the first conductivity type whose gate is connected to the power supply; and one end of which is connected to the power supply and the other end of which is the second MOSFET of the first conductivity type.
An input protection circuit comprising a load element connected to the other end of the resistor via a drain-source circuit of a MOSFET and also connected to an internal circuit. 2. The input protection circuit according to claim 1, wherein the load element is a second conductivity type MOSFET whose gate is connected to ground and whose drain and source constitute the one end and the other end. input protection circuit. 3. In the input protection circuit according to claim 1 or 2, the first and second
An input protection circuit characterized in that both MOSFETs are n-channel MOSFETs and their substrates are connected to ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60117049A JPS61276249A (en) | 1985-05-30 | 1985-05-30 | Input protective circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60117049A JPS61276249A (en) | 1985-05-30 | 1985-05-30 | Input protective circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61276249A JPS61276249A (en) | 1986-12-06 |
| JPH0244151B2 true JPH0244151B2 (en) | 1990-10-02 |
Family
ID=14702157
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60117049A Granted JPS61276249A (en) | 1985-05-30 | 1985-05-30 | Input protective circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61276249A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6439118A (en) * | 1987-08-04 | 1989-02-09 | Nec Corp | Gaas semiconductor integrated circuit |
| JPH0329361A (en) * | 1989-06-26 | 1991-02-07 | Nec Corp | Semiconductor device |
| JPH05267658A (en) * | 1992-02-19 | 1993-10-15 | Nec Corp | Cmos semiconductor integrated circuit |
| ATE240587T1 (en) * | 1994-02-03 | 2003-05-15 | Infineon Technologies Ag | PROTECTION APPARATUS FOR A SERIAL-CONNECTED MOSFET |
| DE69938434T2 (en) * | 1999-06-29 | 2008-09-18 | Cochlear Ltd., Lane Cove | PROTECTION AGAINST HIGH VOLTAGE FOR STANDARD CMOS PROCESS |
| JP2002076282A (en) * | 2000-08-30 | 2002-03-15 | Nec Corp | Semiconductor ic device and method of designing the same |
-
1985
- 1985-05-30 JP JP60117049A patent/JPS61276249A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61276249A (en) | 1986-12-06 |
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