JPH0240233B2 - - Google Patents
Info
- Publication number
- JPH0240233B2 JPH0240233B2 JP61248429A JP24842986A JPH0240233B2 JP H0240233 B2 JPH0240233 B2 JP H0240233B2 JP 61248429 A JP61248429 A JP 61248429A JP 24842986 A JP24842986 A JP 24842986A JP H0240233 B2 JPH0240233 B2 JP H0240233B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- layer
- wiring
- etching
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004020 conductor Substances 0.000 claims description 39
- 238000007747 plating Methods 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 11
- 239000004642 Polyimide Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 10
- 229920001721 polyimide Polymers 0.000 claims description 10
- 239000012212 insulator Substances 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims 1
- 239000010409 thin film Substances 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000003486 chemical etching Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 3
- 239000011295 pitch Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229910017813 Cu—Cr Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000002241 glass-ceramic Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、一般電子機器に用いられる多層配線
基板の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a multilayer wiring board used in general electronic equipment.
(従来の技術)
多層配線基板は、各絶縁基板の表裏両面に形成
した配線回路導体の両者を、スルーホールを導通
化することによつて電気的に接続するものであ
り、その製造方法としては従来から種々の方法が
実施されている。一般には下側導体配線層(以
下、下層配線と略記する)上にポリイミド層を形
成し、あとでスルーホール部のエツチングを行な
い、その後上側導体配線層(以下、上層配線と略
記する)を形成することでスルーホールを介した
上下層の導通を得る。また、場合によつてはスル
ーホールを形成したポリイミド上に全面に薄膜を
形成しスルーホール部に選択めつきを行なつてス
ルーホール内を導体で充填した後、上層配線を形
成する方法もとられている。(Prior Art) A multilayer wiring board electrically connects wiring circuit conductors formed on both the front and back surfaces of each insulating board by making through holes conductive. Various methods have been practiced in the past. Generally, a polyimide layer is formed on the lower conductor wiring layer (hereinafter abbreviated as lower layer wiring), the through hole portion is etched later, and then the upper conductor wiring layer (hereinafter abbreviated as upper layer wiring) is formed. By doing so, conduction between the upper and lower layers is obtained via the through hole. In some cases, a method is also available in which a thin film is formed over the entire surface of polyimide with through holes formed, selective plating is performed on the through holes, and the through holes are filled with a conductor, and then upper layer wiring is formed. It is being
(発明が解決しようとする問題点)
従来のスルーホール形成を化学エツチングによ
り行う場合は、オーバーエツチングやアンダエツ
チングなどの不良を生じやすく、スルーホール部
の下層配線上に薄い酸化膜のバリヤ層が残り上下
層配線に高抵抗の発生原因となつたり、スルーホ
ールにより生じた段差部に上層配線を形成する場
合、スルーホールの側壁・開口角部で断線等の不
良が生じやすい。また、新たに全面薄膜を形成し
てスルーホール内をめつきで充填する方法は工程
が繁雑であるので工程の簡略化が望まれる。(Problems to be Solved by the Invention) When through-holes are conventionally formed by chemical etching, defects such as over-etching and under-etching are likely to occur, and a thin oxide barrier layer is formed on the lower wiring of the through-hole. This may cause high resistance in the remaining upper and lower layer interconnects, and when upper layer interconnects are formed in the stepped portion caused by the through hole, defects such as disconnections are likely to occur at the side walls and opening corners of the through hole. In addition, since the process of forming a new thin film over the entire surface and filling the inside of the through hole with plating is complicated, it is desirable to simplify the process.
(発明が解決するための手段)
本発明は上記の如き実状に鑑みなされたもの
で、絶縁体にスルーホールを設けてのちスルーホ
ールをめつき等によつて上層及び下層の配線を接
続する方法をとらず、上層及び下層の配線を接続
する導体柱を先に形成してのち絶縁体にスルーホ
ールが形成される方法をとりスルーホールが導体
にて充填された構造となるようにするものであ
る。すなわち、下層配線を選択めつきで形成する
際に用いる全面薄膜とレジストを除去せず、その
上に更に導体柱選択めつき用レジストを形成して
選択めつきにて導体柱を形成し、次いでレジスト
及び不要部薄膜を除去してのちポリイミドあるい
はガラスセラミツクスの絶縁層を設けて、この表
面を研磨して平坦化させ、更にエツチングにより
導体柱の頭頂面を露出させて、この上に選択めつ
きにて導体柱上を充填するとともに上層配線を形
成して、導体柱により下層配線と上層配線とを接
続し、順次上記の操作を繰り返すことによつて多
層配線基板を製造する方法を提供するものであ
る。(Means for Solving the Invention) The present invention has been made in view of the above-mentioned circumstances, and is a method of providing through holes in an insulator and then connecting upper and lower layer wiring by plating the through holes or the like. Instead, a conductor pillar is first formed to connect the upper and lower layer wiring, and then a through hole is formed in the insulator, resulting in a structure in which the through hole is filled with a conductor. be. That is, without removing the entire thin film and resist used when forming the lower layer wiring by selective plating, a resist for selective plating of conductor pillars is further formed on top of it, conductor pillars are formed by selective plating, and then the conductor pillars are formed by selective plating. After removing the resist and unnecessary thin film, an insulating layer of polyimide or glass ceramics is provided, this surface is polished to make it flat, the top surface of the conductor pillar is exposed by etching, and selective plating is applied on top of this. To provide a method for manufacturing a multilayer wiring board by filling the top of a conductor column with a conductor column, forming an upper layer wiring, connecting the lower layer wiring and the upper layer wiring by the conductor column, and sequentially repeating the above operations. It is.
(作 用)
上記の如く下層配線の選択電解めつき用薄膜を
そのまま導体柱電解めつき用に併用でき繁雑な化
学エツチング工程を選択めつき及び研磨に置きか
えられるので製造工程が簡素化される。また、絶
縁層が厚い場合でも化学エツチングを必要とする
厚みが導体柱の高さ分減少するためエツチングが
容易になり、テーパ状断面の上部開口径を小さく
抑えることができるため、小径、小ピツチのスル
ーホール形成ができる。また、スルーホールが大
部分が導体で充填されるため接続抵抗が小さくな
るとともに、上層配線形成時にスルーホール部に
段差がないか、あるいは段差が小さいため接続の
信頼性が高い。(Function) As described above, the thin film for selective electrolytic plating of lower layer wiring can be used as is for electrolytic plating of conductor columns, and the complicated chemical etching process can be replaced with selective plating and polishing, thereby simplifying the manufacturing process. In addition, even if the insulating layer is thick, the thickness that requires chemical etching is reduced by the height of the conductor pillars, making etching easier, and the upper opening diameter of the tapered cross section can be kept small, allowing for small diameter and small pitch. Through holes can be formed. Furthermore, since most of the through-hole is filled with a conductor, the connection resistance is reduced, and the reliability of the connection is high because there is no step or only a small step in the through-hole when forming the upper layer wiring.
(実施例)
第1図は本発明による多層配線基板の製造方法
の実施例であり、第1図1はセラミツク基板1の
上にCu―Cr薄膜2をスパツターで形成し、第1
図2に示す如くCu―Cr薄膜2上にフオトリソグ
ラフイーによるフオトレジスト3で線幅20〜
50μm、ピツチ50〜100μmのレジストパターンを
形成し、第1図3に示す如く電解Cuめつきによ
り下層配線4を8μmの厚さに選択めつきし、更
に、第1図4に示す如くフオトリソグラフイーに
よるフオトレジスト5で径20〜50μmのスルーホ
ール用レジストパターンを形成し、第1図5に示
す如く電解Cuめつきにより高さ20μmの導体柱6
を選択めつきして形成し、第1図6に示す如くフ
オトレジスト3、フオトレジスト5及びCu―Cr
薄膜2の不要部分非パターン部を除去し、第1図
7に示す如く導体柱6が埋没するよう導体柱端面
よりの厚さ20μmにポリイミドワニスを全面塗布
してのち硬化させてポリイミド絶縁層7を形成す
る。次いで第1図8に示す如くポリイミド絶縁層
7の表面を研磨して平坦にする。続いて第1図9
に示す如く平坦化されたポリイミド絶縁層7の表
面にプラズマエツチング用マスクとしてアルミ薄
膜11をスパツタリングして形成し、第1図10
に示す如くフオトリソグラフイーによるフオトレ
ジスト12で径20〜50μmのスルーホール用レジ
ストパターンを形成し、次いで第1図11に示す
如くアルミ薄膜11のスルーホール部の不要部分
を通常の化学エツチングにより除去する。続いて
第1図12に示す如くフオトレジスト12及びポ
リイミド絶縁層7をO2プラズマエツチングして
導体柱6の頭頂面を露出させ、次いで第1図13
に示す如くアルミ薄膜11を除去し、ポリイミド
絶縁層7及び導体柱6上に上記配線用Cu―Cr薄
膜8をスパツタリングで形成し、更に上層配線1
0を形成し、上記の工程を繰り返し実施して多層
配線基板を得る。(Example) FIG. 1 shows an example of the method for manufacturing a multilayer wiring board according to the present invention. In FIG.
As shown in Figure 2, a photoresist 3 with a line width of 20 ~
A resist pattern of 50 μm and a pitch of 50 to 100 μm was formed, and the lower layer wiring 4 was selectively plated to a thickness of 8 μm by electrolytic Cu plating as shown in FIG. 1. A resist pattern for through-holes with a diameter of 20 to 50 μm is formed using photoresist 5 made by E, and conductor columns 6 with a height of 20 μm are formed by electrolytic copper plating as shown in FIG.
As shown in FIG. 1, photoresist 3, photoresist 5 and Cu-Cr
Unnecessary non-patterned parts of the thin film 2 are removed, and polyimide varnish is coated on the entire surface to a thickness of 20 μm from the end face of the conductor column so that the conductor column 6 is buried as shown in FIG. form. Next, as shown in FIG. 1, the surface of the polyimide insulating layer 7 is polished to make it flat. Next, Figure 1 9
As shown in FIG. 1, a thin aluminum film 11 is formed by sputtering on the surface of the flattened polyimide insulating layer 7 as a mask for plasma etching.
As shown in FIG. 1, a resist pattern for through holes with a diameter of 20 to 50 μm is formed using photoresist 12 using photolithography, and then, as shown in FIG. do. Subsequently, as shown in FIG. 12, the photoresist 12 and the polyimide insulating layer 7 are O 2 plasma etched to expose the top surface of the conductor column 6, and then, as shown in FIG.
As shown in the figure, the aluminum thin film 11 is removed, the above-mentioned wiring Cu-Cr thin film 8 is formed on the polyimide insulating layer 7 and the conductor pillars 6 by sputtering, and then the upper layer wiring 1 is formed.
0 is formed, and the above steps are repeated to obtain a multilayer wiring board.
なお、ポリイミド絶縁層7の代わりにガラスセ
ラミツクスを用いる場合は乾燥後表面を研磨し、
その後焼成して導体柱の頭頂面を露出させる。 Note that when glass ceramics is used instead of the polyimide insulating layer 7, the surface is polished after drying.
After that, it is fired to expose the top surface of the conductor column.
(発明の効果)
従来のスルーホール形成を化学エツチングによ
り行う場合は、オーバーエツチやアンダエツチな
どの不良を生じやすく、スルーホールに薄い酸化
膜のバリヤ層が残り上下層間配線に高抵抗の発生
原因となつたり、上層配線形成時にスルーホール
部に段差を生じたりの不具合があるが、本発明に
よる製造方法によればスルーホールが大部分を導
体柱で充填され、研磨によつて段差もなくなり上
記の如き問題が解決され信頼性が大きく向上す
る。(Effects of the invention) When conventional through-hole formation is performed by chemical etching, defects such as over-etching and under-etching tend to occur, and a thin oxide barrier layer remains in the through-hole, causing high resistance in the wiring between the upper and lower layers. However, according to the manufacturing method of the present invention, most of the through holes are filled with conductor pillars, and polishing eliminates the steps. Problems such as these will be solved and reliability will be greatly improved.
更に、絶縁層が薄くてよい場合は比較的繁雑な
エツチングに代えて導体柱の選択めつき及び絶縁
層の表面研磨という簡単な方法でφ20μm×厚
20μmの微細スルーホールをもつ多層構造が得ら
れる。また、絶縁層の所要厚さが大なる場合は従
来の製造方法におけるエツチングではその断面が
テーパー状になるため不具合であつたが、本発明
の製造方法では従来の化学エツチングあるいはプ
ラズマエツチングを併用するとはいえエツチング
する厚みが導体柱の高さだけ減少するのでエツチ
ングが容易となり断面がテーパー状になることな
く上部部分も小さくできるので大径、小ピツチの
スルーホール形成が可能となる。 Furthermore, if the insulating layer needs to be thin, instead of relatively complicated etching, a simple method of selectively plating the conductor pillars and polishing the surface of the insulating layer can be used to reduce the thickness by φ20 μm.
A multilayer structure with fine through holes of 20 μm can be obtained. In addition, when the required thickness of the insulating layer is large, etching in the conventional manufacturing method results in a tapered cross section, which is a problem, but in the manufacturing method of the present invention, if conventional chemical etching or plasma etching is used in combination, However, since the thickness to be etched is reduced by the height of the conductor pillar, etching becomes easier and the upper part can be made smaller without the cross section becoming tapered, making it possible to form through holes with large diameters and small pitches.
第1図は本発明の実施例における多層配線基板
の製造方法を説明するための主要製造工程におけ
る基板の要部断面図である。
1:セラミツク基板、4:下側導体配線層、
6:導体柱、7:絶縁体、10:上側導体配線
層。
FIG. 1 is a sectional view of a main part of a board in main manufacturing steps for explaining a method of manufacturing a multilayer wiring board in an embodiment of the present invention. 1: Ceramic substrate, 4: Lower conductor wiring layer,
6: conductor pillar, 7: insulator, 10: upper conductor wiring layer.
Claims (1)
置するポリイミドまたは結晶化ガラス絶縁層とか
らなる多層配線基板の製造方法において、上記各
層の絶縁層に対して下側導体配線層を選択めつき
にて形成し、さらに所要位置に選択めつきにて導
体柱を形成し、これら下側導体配線層及び導体柱
を上記絶縁体にて蔽いその表面を研磨して表面平
坦化し、更にエツチングにより導体柱頭頂面を露
出させ、この上に選択めつきにて導体柱上部を充
填するとともに上側導体配線層を形成して導体柱
により下側導体配線層と上側導体配線層とを接続
し、順次上記の操作を繰り返して多層配線基板と
することを特徴とする多層配線基板の製造方法。1. In a method for manufacturing a multilayer wiring board consisting of a plurality of conductor wiring layers and a polyimide or crystallized glass insulating layer located between the conductor wiring layers, the lower conductor wiring layer is selectively plated for each of the above-mentioned insulating layers. The lower conductor wiring layer and the conductor pillars are covered with the insulator, the surface is polished to make the surface flat, and the conductor pillars are formed by etching. The top surface of the column capital is exposed, and the upper part of the conductor column is filled with selective plating, and an upper conductor wiring layer is formed, and the lower conductor wiring layer and the upper conductor wiring layer are connected by the conductor column, and the above-mentioned 1. A method for manufacturing a multilayer wiring board, comprising repeating the above operations to obtain a multilayer wiring board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24842986A JPS63104398A (en) | 1986-10-21 | 1986-10-21 | Manufacture of multilayer interconnection board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24842986A JPS63104398A (en) | 1986-10-21 | 1986-10-21 | Manufacture of multilayer interconnection board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63104398A JPS63104398A (en) | 1988-05-09 |
JPH0240233B2 true JPH0240233B2 (en) | 1990-09-10 |
Family
ID=17177991
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24842986A Granted JPS63104398A (en) | 1986-10-21 | 1986-10-21 | Manufacture of multilayer interconnection board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63104398A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0636443U (en) * | 1992-10-26 | 1994-05-17 | 正士 神志那 | Chair with double seat |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0286193A (en) * | 1988-09-22 | 1990-03-27 | Fujitsu Ltd | Manufacture of thin film multilayer circuit board |
JP2773366B2 (en) * | 1990-03-19 | 1998-07-09 | 富士通株式会社 | Method of forming multilayer wiring board |
JP2881270B2 (en) * | 1990-08-28 | 1999-04-12 | 日本特殊陶業株式会社 | Method for manufacturing multilayer wiring board |
JP2749461B2 (en) * | 1991-05-29 | 1998-05-13 | 京セラ株式会社 | Multilayer circuit board and method of manufacturing the same |
JP2000340905A (en) * | 1999-05-28 | 2000-12-08 | Toppan Printing Co Ltd | Optical/electric wiring board, manufacture thereof and mounting board |
JP2001007529A (en) * | 1999-06-23 | 2001-01-12 | Ibiden Co Ltd | Multilayer printed wiring board and its manufacture, and semiconductor chip and its manufacture |
US8008188B2 (en) * | 2007-06-11 | 2011-08-30 | Ppg Industries Ohio, Inc. | Method of forming solid blind vias through the dielectric coating on high density interconnect substrate materials |
JP6065359B2 (en) * | 2011-11-24 | 2017-01-25 | 凸版印刷株式会社 | Manufacturing method of wiring substrate with through electrode |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60134497A (en) * | 1983-12-23 | 1985-07-17 | 株式会社日立製作所 | Circuit board and method of producing same |
-
1986
- 1986-10-21 JP JP24842986A patent/JPS63104398A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60134497A (en) * | 1983-12-23 | 1985-07-17 | 株式会社日立製作所 | Circuit board and method of producing same |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0636443U (en) * | 1992-10-26 | 1994-05-17 | 正士 神志那 | Chair with double seat |
Also Published As
Publication number | Publication date |
---|---|
JPS63104398A (en) | 1988-05-09 |
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