JPH0239130A - Liquid crystal display device - Google Patents
Liquid crystal display deviceInfo
- Publication number
- JPH0239130A JPH0239130A JP63191167A JP19116788A JPH0239130A JP H0239130 A JPH0239130 A JP H0239130A JP 63191167 A JP63191167 A JP 63191167A JP 19116788 A JP19116788 A JP 19116788A JP H0239130 A JPH0239130 A JP H0239130A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- insulating film
- liquid crystal
- bus line
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 17
- 239000010408 film Substances 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000010409 thin film Substances 0.000 claims abstract description 5
- 230000003071 parasitic effect Effects 0.000 claims abstract 2
- 239000011159 matrix material Substances 0.000 claims description 5
- 210000002858 crystal cell Anatomy 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 7
- 229910004205 SiNX Inorganic materials 0.000 abstract description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 3
- 229910003437 indium oxide Inorganic materials 0.000 abstract description 3
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract description 3
- 210000004027 cell Anatomy 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229920002472 Starch Polymers 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 235000019698 starch Nutrition 0.000 description 1
- 239000008107 starch Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、半導体膜にアモルファス・シリコンhゝ
を用いた逆スタフー型の薄膜トランジスタ(以下、“T
PT”と称する)と付加容量電極及び絵素電極をマトリ
ックス状に配列してなる液晶セル基板を有する液晶表示
素子に関するものである。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an inverted starch type thin film transistor (hereinafter referred to as "T") using amorphous silicon as a semiconductor film.
The present invention relates to a liquid crystal display element having a liquid crystal cell substrate formed by arranging an additional capacitance electrode (referred to as "PT"), an additional capacitance electrode, and a picture element electrode in a matrix.
〈従来の技術〉
TPTをアドレス素子として用いマトリックス表示する
液晶表示装置の一例を第4図、第5図及び第6図に示す
。この液晶表示装置は、絶縁性基板1の上にゲート電極
2.ゲート絶縁膜3.アモルファス・シリコン(a −
5i ]I!’ 4 、絶Rf’A 51 n”−a−
3i膜6.ソース・ドレイン電極7.絵素電極8.保護
膜9を順次積層することにより形成されている。ここで
絵素電極電位保持特性改善の為、液晶容量に並列となる
付加容量(以下、R(sI+と称する)を形成するC8
電極10が絵素電極10直下に設けられている。<Prior Art> An example of a liquid crystal display device that uses TPT as an address element to perform matrix display is shown in FIGS. 4, 5, and 6. This liquid crystal display device has a gate electrode 2 on an insulating substrate 1. Gate insulating film 3. Amorphous silicon (a-
5i ] I! '4, absolutely Rf'A 51 n"-a-
3i membrane6. Source/drain electrode7. Picture element electrode 8. It is formed by sequentially laminating protective films 9. Here, in order to improve the picture element electrode potential retention characteristic, C8 is formed to form an additional capacitor (hereinafter referred to as R (sI+)) in parallel with the liquid crystal capacitor.
An electrode 10 is provided directly below the picture element electrode 10.
従来の構造では、絵素電位保持特性の改善の為に液晶容
量に並列となるCSを形成しているが、このC5電極と
ソースバスライン間に生じる容量の為に、ソース信号の
変動が生じクロストークが発生する。これを改善する為
には、ゲート絶縁膜の膜厚を大きくするか、ゲート絶縁
膜の材料を透電率の小さなものにする方法があるが、そ
の場合は、C5電極と絵素電極間の容量が小さくなりC
5として充分作用しなくなる。In the conventional structure, a CS is formed in parallel with the liquid crystal capacitor in order to improve the pixel potential retention characteristics, but the capacitance generated between the C5 electrode and the source bus line causes fluctuations in the source signal. Crosstalk occurs. In order to improve this, there is a method to increase the thickness of the gate insulating film or to use a material with low conductivity for the gate insulating film, but in that case, the gap between the C5 electrode and the pixel electrode is Capacity becomes smallerC
5, it no longer functions sufficiently.
く問題点を解決するための手段〉
本発明は、C5電極とTFTのソース電極に連結された
ソースバスラインの交差部分のみに更に絶縁膜を付加す
ることにより、C8電極と絵素電極間で形成されるC5
の容量を低減させることなくC5電極とソースバスライ
ンの交差部分に発生する容量の低減を可能としたTET
駆動型液晶セル基板を有することを特徴とする液晶表示
装置である。Means for Solving the Problems> The present invention further provides an insulation film between the C8 electrode and the pixel electrode by adding an insulating film only to the intersection of the source bus line connected to the C5 electrode and the source electrode of the TFT. C5 formed
TET that makes it possible to reduce the capacitance generated at the intersection of the C5 electrode and the source bus line without reducing the capacitance of
This is a liquid crystal display device characterized by having a drive type liquid crystal cell substrate.
〈作用〉
上記構造によりC5電極とソースバスラインとの交差部
分に於いて発生する容量が低減され、ソース信号の変動
が抑止される結果、クロストークの発生を防止すること
ができる。<Operation> The above structure reduces the capacitance generated at the intersection between the C5 electrode and the source bus line, suppresses fluctuations in the source signal, and thereby prevents crosstalk from occurring.
〈実施例〉
第1図、第2図及び第3図を用いて本発明の一実施例を
説明する。第1図はTPTの配列構造を示す構成図、第
2図は第1図のA−A断面図、第3図は第1図のB−B
断面図である。ガラスからなる絶縁性基板1上にスパッ
タリングによりTi。<Example> An example of the present invention will be described using FIGS. 1, 2, and 3. Fig. 1 is a configuration diagram showing the arrangement structure of TPT, Fig. 2 is a sectional view taken along line AA in Fig. 1, and Fig. 3 is a sectional view taken along line B-B in Fig. 1.
FIG. Ti is deposited on an insulating substrate 1 made of glass by sputtering.
Mo、W、Ta等を形成しこれをフォト、−エツチング
によりパターン化してゲート電極2を形成する。Mo, W, Ta, etc. are formed and patterned by photo-etching to form the gate electrode 2.
次にスパッタリングあるいは電子ビーム蒸着により酸化
インジウムを主成分とする透明電導膜を形成しこれをフ
ォト・エツチングにてパターン化してC8電極10を形
成する。次にプラズマCVDによりSiNxからなるゲ
ート絶縁膜3を形成し更に連続してa−3iからなる半
導体膜を、更にSiNxからなる絶縁膜を形成しこれを
フォトΦエツチングにてパターン化することにより半導
体膜4.絶縁膜5及びCs?[極1oとソースバスライ
ンとの交差部分に容量低減用の絶縁膜11を形成する。Next, a transparent conductive film containing indium oxide as a main component is formed by sputtering or electron beam evaporation, and this is patterned by photo etching to form a C8 electrode 10. Next, a gate insulating film 3 made of SiNx is formed by plasma CVD, and then a semiconductor film made of a-3i and an insulating film made of SiNx are formed and patterned by photo-Φ etching. Membrane 4. Insulating film 5 and Cs? [An insulating film 11 for capacitance reduction is formed at the intersection of the pole 1o and the source bus line.
次にプラズマCVDによりn”−a−5iからなる半導
体膜を形成しフォト・エツチングにてパターン化するこ
とにより半導体膜6を形成する。次にスパッタリングに
よりTi、Mo、W等を形成しフォト番エッチンクニヨ
リパターン化しンース拳ドレイン電極7を形成する。次
にスパッタリング又は電子ビーム蒸着により酸化インジ
ウムを主成分とする透明電導膜を形成しこれをフォ)−
エツチングにてパターン化することにより略々矩形の絵
素電極8を形成する。次にプラズマCVDによりS i
Nxからなる保護膜9を形成する。絵素電極8は絶縁性
基板1上にマトリックス状に配列し、各絵素室(iBに
対応してTPTが配置される。TPTのドレイン電極は
絵素電極8の一端で接続され、ソース電極とゲートに極
2はそれぞれソースバスライン、ゲートパスラインに連
結される。以上の様にして、c8i極とソースバスライ
ンの交差部分に容量低減用の絶縁膜11を形成した液晶
表示セル用TPT基板が作製される。尚、本実施例では
C3電極10を透明導電膜により形成しているが、ゲー
ト電極2形成時にゲート電極2と同一材料を用いて形成
しても良い。Next, a semiconductor film 6 is formed by forming an n''-a-5i semiconductor film by plasma CVD and patterning it by photo-etching.Next, Ti, Mo, W, etc. are formed by sputtering and photonumbered. A transparent conductive film containing indium oxide as a main component is formed by sputtering or electron beam evaporation.
A substantially rectangular picture element electrode 8 is formed by patterning by etching. Next, Si
A protective film 9 made of Nx is formed. The picture element electrodes 8 are arranged in a matrix on the insulating substrate 1, and a TPT is arranged corresponding to each picture element chamber (iB).The drain electrode of the TPT is connected to one end of the picture element electrode 8, and the source electrode and the gate pole 2 are connected to the source bus line and the gate pass line, respectively.As described above, the TPT substrate for a liquid crystal display cell has the insulating film 11 for capacitance reduction formed at the intersection of the c8i pole and the source bus line. Incidentally, in this embodiment, the C3 electrode 10 is formed of a transparent conductive film, but it may be formed using the same material as the gate electrode 2 when forming the gate electrode 2.
上記TPT基板と他方の対向電極を形成したセル基板を
重ねて一体化しその空隙に液晶材料を封入することによ
り、マトリックス表示型の液晶表示装置が得られる。A matrix display type liquid crystal display device can be obtained by stacking and integrating the TPT substrate and the cell substrate on which the other counter electrode is formed, and filling the gap with a liquid crystal material.
CS電極10とソースバスライン7 の間にはゲート絶
縁膜3のSiNx層と容量低減用の絶縁膜11の2層構
造が介設されることになる。従って、C8電極10は絵
素電極8との間で付加容量用電極として作用するが、ソ
ースバスライン7′との間では容量性結合をせず、ソー
スバスライン7′の信号に影響を与えることもない。A two-layer structure consisting of the SiNx layer of the gate insulating film 3 and the insulating film 11 for capacitance reduction is interposed between the CS electrode 10 and the source bus line 7. Therefore, the C8 electrode 10 acts as an electrode for additional capacitance with the picture element electrode 8, but does not capacitively couple with the source bus line 7', and does not affect the signal on the source bus line 7'. Not at all.
〈発明の効果〉
以上によりC5電極とソースバスラインとの交差部分に
のみ新たに付設された絶縁膜の介在によりC8?iE極
と絵素電極間の付加容量を変化させることなくcsi極
とソースバスライン間の容量によるソース信号の変動を
抑え、クロストークの発生を防ぐことができる。<Effects of the Invention> As described above, the C8? Fluctuations in the source signal due to the capacitance between the CSI pole and the source bus line can be suppressed without changing the additional capacitance between the iE pole and the picture element electrode, and crosstalk can be prevented from occurring.
【図面の簡単な説明】
第1図は本発明の一実施例の説明に供する液晶表示セル
基板の平面図、第2図は第1図のA−X断面図。第3図
は第1図のB−X断面図。第4図は、従来例を示す液晶
表示セル基板の平面図。第5図は第4図のX−X断面図
。第6図は第4図のY−Y’断面図を示す。
1・・・絶縁性基板、2・・・ゲート電極、3゜・・絶
縁膜、4,6・・・半導体膜、7・・・ソースイン電極
、8・・・絵素電極、9・・・保護膜、1電極。
、11
ドレ
0・・・C5
代理人 弁理士 杉 山 毅 至(他1名)も2?コ
鷹3図
$1図
11!4図BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a liquid crystal display cell substrate for explaining an embodiment of the present invention, and FIG. 2 is a sectional view taken along line A-X in FIG. 1. FIG. 3 is a sectional view taken along line B-X in FIG. FIG. 4 is a plan view of a conventional liquid crystal display cell substrate. FIG. 5 is a sectional view taken along line XX in FIG. 4. FIG. 6 shows a YY' cross-sectional view of FIG. 4. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Gate electrode, 3°... Insulating film, 4, 6... Semiconductor film, 7... Source-in electrode, 8... Picture element electrode, 9...・Protective film, 1 electrode. , 11 Dore 0...C5 Agent Patent Attorney Takeshi Sugiyama (and 1 other person) also 2? Kotaka 3 figure $1 figure 11!4 figure
Claims (1)
ジスタのドレイン電極と連結された絵素電極及び該絵素
電極との間で付加容量を形成する付加容量電極をマトリ
ックス状に配列してなる液晶表示装置において、前記付
加容量電極と前記薄膜トランジスタのソース電極と連結
されたソースバスラインの交差部分に寄生容量低減用の
絶縁膜が介在していることを特徴とする液晶表示装置。1. In a liquid crystal display device in which a thin film transistor, a picture element electrode connected to the drain electrode of the thin film transistor, and an additional capacitance electrode forming an additional capacitance between the picture element electrode are arranged in a matrix on a liquid crystal cell substrate. . A liquid crystal display device, wherein an insulating film for reducing parasitic capacitance is interposed at the intersection of the additional capacitance electrode and the source bus line connected to the source electrode of the thin film transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63191167A JPH0239130A (en) | 1988-07-29 | 1988-07-29 | Liquid crystal display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63191167A JPH0239130A (en) | 1988-07-29 | 1988-07-29 | Liquid crystal display device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0239130A true JPH0239130A (en) | 1990-02-08 |
Family
ID=16270015
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63191167A Pending JPH0239130A (en) | 1988-07-29 | 1988-07-29 | Liquid crystal display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0239130A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6567145B1 (en) * | 1999-03-26 | 2003-05-20 | Hitachi, Ltd. | Liquid crystal display device having conductive lines formed with amorphous oxide conductive layer on metal layer and method of fabrication thereof |
CN105161049A (en) * | 2015-06-30 | 2015-12-16 | 上海天马有机发光显示技术有限公司 | Organic light-emitting display panel and electronic equipment |
TWI669558B (en) * | 2017-01-10 | 2019-08-21 | 友達光電股份有限公司 | Pixel structure and pixel structure manufacturing method |
-
1988
- 1988-07-29 JP JP63191167A patent/JPH0239130A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6567145B1 (en) * | 1999-03-26 | 2003-05-20 | Hitachi, Ltd. | Liquid crystal display device having conductive lines formed with amorphous oxide conductive layer on metal layer and method of fabrication thereof |
CN105161049A (en) * | 2015-06-30 | 2015-12-16 | 上海天马有机发光显示技术有限公司 | Organic light-emitting display panel and electronic equipment |
TWI669558B (en) * | 2017-01-10 | 2019-08-21 | 友達光電股份有限公司 | Pixel structure and pixel structure manufacturing method |
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