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JPH0235710A - Forming method for thin film semiconductor layer - Google Patents

Forming method for thin film semiconductor layer

Info

Publication number
JPH0235710A
JPH0235710A JP18606188A JP18606188A JPH0235710A JP H0235710 A JPH0235710 A JP H0235710A JP 18606188 A JP18606188 A JP 18606188A JP 18606188 A JP18606188 A JP 18606188A JP H0235710 A JPH0235710 A JP H0235710A
Authority
JP
Japan
Prior art keywords
layer
semiconductor layer
thin film
film
oxidation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18606188A
Other languages
Japanese (ja)
Other versions
JP2718074B2 (en
Inventor
Hisao Hayashi
久雄 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
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Filing date
Publication date
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Priority to JP18606188A priority Critical patent/JP2718074B2/en
Publication of JPH0235710A publication Critical patent/JPH0235710A/en
Application granted granted Critical
Publication of JP2718074B2 publication Critical patent/JP2718074B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To simplify a process and form a selective oxide film free from bird's beak by simultaneously performing the crystal growth of an active layer and the formation of the selective oxide layer for element isolation. CONSTITUTION:On an insulative substrate 1, a polycrystalline or amorphous non-single crystalline thin film semiconductor layer 2 is formed; an oxidation resistant film 4 like Si3N4, is formed selectively on the semiconductor layer 2; then by projecting an energy beam, like excimer laser, on the whole surface in an oxidizing atmosphere, the exposed semiconductor layer 2 is selectively oxidized, and the semiconductor layer 2 under the oxidation resistant film 4 is subjected to thermal treatment. Hence a region, where the oxidation resistant film 4 of the non-single crystalline thin film semiconductor layer 2 being an active layer is not formed, is selectively oxidized; and in this part, a selective oxide layer 6 turning to an element isolation region is formed; at the same time, the non-single crystalline thin film layer 2 turning to the active layer under the oxidation resistant film 4 is subjected to solid growth in the simultaneous processing. In the above solid growth, the oxidation resistant film 4 acts as a capping layer, so that the forming process of capping layer can be omitted. Further, bird's beak phenomenon is controlled, and the selective oxide layer 6 free from bird's beak is formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、薄II?半導体調の形成方法に関するもので
ある。
[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to thin II? The present invention relates to a semiconductor-like forming method.

〔発明の概要〕[Summary of the invention]

本発明は薄映半導体層の形成方法において、絶縁性基板
上に非単結晶薄膜半導体層を形成し、該半導体lW4上
に選択的に耐酸化膜を形成する。その後、酸化性雰囲気
中で全面にエネルギービームを照射して露出している半
導体j−を酸化すると共に、制酸化膜下の半導体層を熱
処理することにより、活性J@となる半導体層の固相成
長と同時に素子骨+1011領域となる選択酸化(LO
GO3’)層の形成を可能にし、且つバースビークのな
い選択酸化層形成を−り能にしたものである。
The present invention is a method for forming a thin film semiconductor layer, in which a non-single crystal thin film semiconductor layer is formed on an insulating substrate, and an oxidation-resistant film is selectively formed on the semiconductor IW4. After that, the entire surface is irradiated with an energy beam in an oxidizing atmosphere to oxidize the exposed semiconductor j-, and the semiconductor layer under the anti-oxidation film is heat-treated to form a solid phase of the semiconductor layer that becomes active J@. Selective oxidation (LO
This makes it possible to form a GO3') layer and to form a selective oxidation layer without birthmarks.

〔従来の技術〕[Conventional technology]

一般に、半導体装置、特に薄膜半導体装置を形成する場
合、ゲート絶縁物として、また容量としであるいは素子
分離時の耐酸化マスクとしてSi3N2股が用いられて
いる。このS+3N4膜は誘電率が大きく耐酸化性、耐
薬品性に優れ、上記用途として通している。また、ゲー
ト絶縁物を容量として使う場合、S iJ 4 Cは単
独としては使われず5iO2SijN4Sif2のサン
ドイッチ構造にする場合が多い。
Generally, when forming a semiconductor device, especially a thin film semiconductor device, Si3N bifurcated material is used as a gate insulator, a capacitor, or an oxidation-resistant mask during element isolation. This S+3N4 film has a large dielectric constant and excellent oxidation resistance and chemical resistance, and is accepted for the above-mentioned applications. Furthermore, when using the gate insulator as a capacitor, S iJ 4 C is not used alone, but a sandwich structure of 5iO2SijN4Sif2 is often used.

また、半導体築槓回路における素子分離の寸法として、
SS102Si3N4を耐酸化マスクとじて用い素子部
以外を熱酸化するいわゆるLocus法(選択酸化法)
が主流になっている。
In addition, as the dimension of element separation in a semiconductor construction circuit,
The so-called Locus method (selective oxidation method) uses SS102Si3N4 as an oxidation-resistant mask to thermally oxidize areas other than the element part.
has become mainstream.

また、薄膜半導体装置等の多結晶シリコンによる活性r
−を結晶改善する方法としてエキシマレーザを照4・j
シて結晶成長させるという方法も知られている。
In addition, the activation of polycrystalline silicon in thin film semiconductor devices
Excimer laser light is used as a method to improve the crystallization of -4.j
A method of growing crystals by cutting is also known.

(発明が解決しようとする課題〕 ところで、半導体装置において、上記SiSi3N4を
ゲート絶縁膜や容着として使う場合、上述のように5i
O2Si3N+   5i02のサントイツナ構造にし
ているが、この上部の5i(b 1%jはSisN4M
!Q表面を約1100℃で熱酸化して形成される。この
熱酸化処理は通常、塩気炉内において行なっていたため
、この熱酸化時に活性JfJである単結晶シリコンノル
仮中に欠陥が生じたり、不純物が拡散する等の不都合が
あった。
(Problems to be Solved by the Invention) By the way, when using the above-mentioned SiSi3N4 as a gate insulating film or adhesive in a semiconductor device, the 5i
The structure is O2Si3N+ 5i02, but the upper 5i (b 1%j is SisN4M
! It is formed by thermally oxidizing the Q surface at about 1100°C. Since this thermal oxidation treatment is usually carried out in a salt air furnace, there are disadvantages such as defects occurring in the monocrystalline silicon precipitate, which is active JfJ, and impurities diffusing during this thermal oxidation.

一方、1、ocos法による素子分離においては、所謂
バーズビークの問題があり、バーズビークのない選択酸
化層の形成が望まれている。
On the other hand, in element isolation using the 1. ocos method, there is a problem of so-called bird's beak, and it is desired to form a selective oxidation layer without bird's beak.

また、エキシマレーザ照射による活性層の結晶成長につ
いては、照射時に活性層の多結晶シリコン上を5i(b
欣等でキャンピングする必要がある。
Regarding crystal growth of the active layer by excimer laser irradiation, 5i (b
It is necessary to camp in Shin etc.

本発明は、このような点に鑑み成されたもので、その目
的とすることころは活性層の結晶成長と素子分離のため
の選択酸化層の形を同時に行なってし程の簡略化を図る
と共に、バーズビークのない選択酸化j脅の形成を可能
にした薄膜半導体層の形成方法を提供することにある。
The present invention has been made in view of these points, and its purpose is to simultaneously grow the crystals of the active layer and form the selective oxidation layer for element isolation, thereby simplifying the process. Another object of the present invention is to provide a method for forming a thin film semiconductor layer that enables selective oxidation formation without bird's beaks.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の1WIIW半導体層の形成方法は、絶縁性基板
(1)上に多結晶又は非晶質の非単結晶薄膜半導体In
 +21を形成し、該ス導体層(2)上に選択的にS 
i )N 4等の耐酸化膜(4)を形成する。その後、
酸化性雰囲気中で全面にエキシマレーザ−等の工フルギ
ービームを照射して露出している半導体層(2)を選択
酸化Jると共に、耐酸化99+41下の半導体1m (
21を熱処理するようにしたものである。
The method for forming a 1WIIW semiconductor layer of the present invention is to form a polycrystalline or amorphous non-single crystal thin film semiconductor In on an insulating substrate (1).
+21 and selectively S on the S conductor layer (2).
i) Form an oxidation-resistant film (4) such as N4. after that,
In an oxidizing atmosphere, the exposed semiconductor layer (2) is selectively oxidized by irradiating the entire surface with a mechanical beam such as an excimer laser.
21 was heat-treated.

〔作用〕[Effect]

上述の本発明の形成方法によれば、酸化性雰囲気中でエ
ネルギービームを高温・短時間照射するので、活性層で
ある非単結晶薄膜半導体rf4(21の耐酸化膜(4)
が形成されない領域が選択酸化され、ここに素子分離領
域となる選択酸化層(61が形成されると共に、同時工
程で耐酸化膜(4)下の活性層となる非単結晶薄膜半導
体層(2)が固相成従する。この面相成長に際しては、
耐酸化膜(4)がキャンピング(−として作用するので
、キャツピング層の形成工程が省略される。
According to the above-described formation method of the present invention, since the energy beam is irradiated at high temperature and for a short time in an oxidizing atmosphere, the non-single crystal thin film semiconductor rf4 (oxidation-resistant film (4) of 21) which is the active layer
The regions where the oxidation-resistant film (4) is not formed are selectively oxidized, and a selective oxidation layer (61) which becomes an element isolation region is formed therein, and at the same time, a non-single crystal thin film semiconductor layer (2) which becomes an active layer under the oxidation-resistant film (4) is formed. ) becomes a solid phase.During this phase growth,
Since the oxidation-resistant film (4) acts as a camper (-), the step of forming a capping layer is omitted.

また、エネルギービームは直進して照射され、その照射
された部分のみが酸化されるため、バーズビーク現象が
制御され、バーズビークのない選択酸化層(6)が形成
される。
In addition, since the energy beam is irradiated in a straight line and only the irradiated portion is oxidized, the bird's beak phenomenon is controlled and a selective oxidation layer (6) without bird's beak is formed.

〔実施例〕〔Example〕

以下、第1図を参照しながら本発明の詳細な説明する。 Hereinafter, the present invention will be explained in detail with reference to FIG.

第1図は、本実施例に係る薄膜半導体装置の形成方法を
示す土程図である。以L mを追ってその工程を説明す
る。
FIG. 1 is a stage diagram showing a method for forming a thin film semiconductor device according to this embodiment. The process will be explained below.

面、本例はPチャンネル型薄膜トランジスタについて述
べるが、nチャンネル型薄膜トランジスタにも通用でき
る。
On the other hand, although this example describes a P-channel thin film transistor, the present invention can also be applied to an N-channel thin film transistor.

まず、同図Aに不すように、5i02からなる絶縁物(
1)上に例えばP型を呈した多結晶シリコン清秋(2)
を例えばCVD法等で成長させる。
First, as shown in Figure A, an insulator made of 5i02 (
1) Polycrystalline silicon Kiyoaki with, for example, P-type on top (2)
is grown by, for example, the CVD method.

次に、同図Bに示すように、多結晶シリコン薄膜(2)
の表面に熱酸化を施してゲート用の5t02viI化膜
(3)を形成する。その後、該5i02酸化股(3)上
ニ同様ニケ)J’lJノSiaN4MII9!’+41
をCVD法等で成長させる。
Next, as shown in Figure B, a polycrystalline silicon thin film (2) is formed.
A 5t02viI film (3) for a gate is formed by thermally oxidizing the surface. After that, the 5i02 oxidized crotch (3) (same as above) J'lJノSiaN4MII9! '+41
is grown by CVD method or the like.

次に、素子分離のため、同図Cに示すように、Si3N
4薄膜(4)及び5i02酸化股(3)の一部をホトリ
ソグラフィー技術を用いてエツチング除去し、下層に存
していた多結晶シリコン’a MIj!+2)の一部(
2A)を露出させる。
Next, for element isolation, Si3N
4 thin film (4) and a part of the 5i02 oxide layer (3) were etched away using photolithography technology, and the polycrystalline silicon 'a MIj! that existed in the underlying layer was removed. +2) part (
2A) Expose.

次に、同図りに示すように、酸化性雰囲気中、例えば0
2或は03雰囲気中でSi3N4薄膜(4)及び露出さ
れた多結晶シリコン部分(2^)を含む全面にエキシマ
レーザ(5)を照射して高温・短時間の熱処理を施し、
多結晶シリコン部分(2A)を熱酸化することにより絶
縁物+1+に達する5i02のフィールド絶縁層(6)
に変えるとともに、Si3N4薄膜(4)の表面を同時
熱酸化して5t(h酸化膜(7)を形成する。
Next, as shown in the same figure, in an oxidizing atmosphere, for example, 0
2 or 03 atmosphere, the entire surface including the Si3N4 thin film (4) and the exposed polycrystalline silicon portion (2^) is irradiated with an excimer laser (5) to perform heat treatment at high temperature and for a short time.
Field insulation layer (6) of 5i02 reaching insulation +1+ by thermal oxidation of polycrystalline silicon part (2A)
At the same time, the surface of the Si3N4 thin film (4) is simultaneously thermally oxidized to form a 5T(h oxide film (7)).

このフィールド絶縁層(6)が素子分離領域となる。This field insulating layer (6) becomes an element isolation region.

また、このエキシマレーザ(5)の照射によって同時に
、Si3N4薄梗(4)ドの活性層となる多結晶シリコ
ン@ 膜(2)が結晶成長する。この場合、5iiN+
 M膜(4)が活性1i! (2)のエキシマレーザ(
5)の照射に対する一種のキャンピング作用を果たして
いる。
Further, at the same time, the irradiation with the excimer laser (5) causes crystal growth of the polycrystalline silicon film (2) which becomes the active layer of the Si3N4 thin layer (4). In this case, 5iiN+
M membrane (4) is active 1i! (2) excimer laser (
5) It plays a kind of camping effect against the irradiation.

一方、フィールド絶縁層(6)では、エキシマレーザ(
5)の直進照射及び短時間照射により、照射された多結
晶シリコン部分(2A)のみ熱酸化され、活性7m +
21側に熱酸化が進行しないため、いわゆるバースビー
ク現象が発生しない。
On the other hand, in the field insulating layer (6), the excimer laser (
By direct irradiation and short-time irradiation in 5), only the irradiated polycrystalline silicon portion (2A) is thermally oxidized, resulting in an active area of 7m +
Since thermal oxidation does not proceed to the 21 side, the so-called birthbeak phenomenon does not occur.

次に、同図Eに示すように、全面にゲート電極となる不
純物(例えばn型不純物)をドープした多結晶シリコン
層(8)をCVD法等で成長させ、次いで同図ドに示ず
ように、多結晶シリコン層(8)、5i(h酸化1i+
71. Si3N+ *膜(4)及び5i02酸化膜(
3)を順次選択エツチングして多結晶シリコン屓(8)
よりなるゲート電極(9)及び5t(h酸化膜(3)と
5itN+薄躾(4)と5i02酸化11!J (71
からなるゲート絶縁膜(10)を形成すると共に、活性
J* (21の表面部のうり、ゲート部以外の■$分を
露出させる。
Next, as shown in Figure E, a polycrystalline silicon layer (8) doped with an impurity (for example, an n-type impurity) that will become the gate electrode is grown on the entire surface by CVD, and then as shown in Figure D. , polycrystalline silicon layer (8), 5i (h oxidation 1i+
71. Si3N+ *film (4) and 5i02 oxide film (
3) is sequentially selectively etched to form a polycrystalline silicon layer (8).
Gate electrode (9) and 5t (h oxide film (3), 5itN + thin film (4) and 5i02 oxide 11!J (71
At the same time, a gate insulating film (10) consisting of the active J* (21) is formed, and the surface area of the active J* (21) and the area other than the gate area are exposed.

その後、同図Gに示すように、フィールド絶縁1m (
61及びゲート電極(9)をマスクとして活性層(2)
にP型の不純物(13)をイオン注入してソース領域(
11)及びドレイン領域(12)を形成してPチャンネ
ル型の薄膜トランジスタを形成する。
After that, as shown in figure G, field insulation 1m (
Active layer (2) using 61 and gate electrode (9) as a mask.
P-type impurity (13) is ion-implanted into the source region (
11) and a drain region (12) to form a P-channel thin film transistor.

向、上記実施例では活性1iJ (21を多結晶シリコ
ンにて形成したが、その他罪晶質シリコンで形成しても
よい。
In the above embodiment, the active layer 1iJ (21) was formed of polycrystalline silicon, but it may be formed of other polycrystalline silicon.

また、上潮では5i(b酸化11J +31とSi3N
+股(4)と5i(h酸化膜(7)にてゲート絶縁膜(
10)を構成したが、その他、第1図りの工程後、これ
らIll (31(41(7)を除去して、改めて5i
(hによるゲート絶縁膜を形成することも口J能である
In addition, in the upper tide, 5i (b oxidation 11J +31 and Si3N
+ crotch (4) and 5i (h oxide film (7) to gate insulation film (
10), but after the process of the first drawing, these Ill (31(41(7)) were removed and 5i
(It is also possible to form a gate insulating film using H.

上述の薄膜トランジスタの形成方法によれは、多結晶シ
リコン薄膜(2)上に5i02酸化股(3)を介しζ選
択的にS i =N 4薄膜(4)を形成した後、エキ
シマレーザ照射による熱処理を施すことにより、フィー
ルド絶縁層(6)を形成する選択酸化と、5izN+薄
膜(4)下の活性層となる多結晶シリコン層(2)の結
晶化とが同時に行なわれる。そして、この場合、選択酸
化時の耐酸化マスクとなるSi3N4のS膜(4)が多
結晶シリコン薄膜(2)の結晶成長の際のキャッピング
j−を兼ねるので、新たにキャッピング工程を追加する
必要がない。
According to the method for forming a thin film transistor described above, after forming an S i =N 4 thin film (4) selectively on the polycrystalline silicon thin film (2) via a 5i02 oxide layer (3), heat treatment is performed by excimer laser irradiation. By applying this, selective oxidation to form the field insulating layer (6) and crystallization of the polycrystalline silicon layer (2) which will become the active layer under the 5izN+ thin film (4) are performed simultaneously. In this case, the Si3N4 S film (4), which serves as an oxidation-resistant mask during selective oxidation, also serves as a capping layer during crystal growth of the polycrystalline silicon thin film (2), so it is necessary to add a new capping process. There is no.

さらにエキシマレーザ(5)の照射により、5iJ4薄
欣(4)の表面が熱酸化され5i(h酸化膜(7)を形
成することができ、ゲート絶縁膜(10)  (或は他
の合縁を構成する場合の誘電物質)とし”ζ5iO2−
Si)N4Si(hのサンドイッチ構造を同時に形成す
ることができる。従って、薄膜トランジスタの製造上程
の簡略化を図ることができる。
Further, by irradiation with the excimer laser (5), the surface of the 5iJ4 thin film (4) is thermally oxidized to form a 5i(h oxide film (7)), and a gate insulating film (10) (or other bonding film) can be formed. ζ5iO2−
A sandwich structure of Si)N4Si(h) can be formed at the same time. Therefore, the manufacturing process of the thin film transistor can be simplified.

一方、選択酸化によってフィールド絶縁層(6)を形成
する際に、従来の1100℃、長時間の熱酸化とは異な
り、エキシマレーザ照射による高温、短時間の熱処理で
行なわれ、且つしかもエキシマレーザ(5)は直進して
照射されその照射された部分(2A)のみが熱酸化され
るためにバーズビークの発生が抑制され、バースビーク
のないフィールド絶縁層(6)を形成することができ、
素子の高密度化を図ることができる。
On the other hand, when forming the field insulating layer (6) by selective oxidation, unlike the conventional thermal oxidation at 1100°C for a long time, heat treatment is performed at a high temperature and for a short time by excimer laser irradiation. 5) is irradiated straight ahead and only the irradiated portion (2A) is thermally oxidized, so the generation of bird's beak is suppressed and a field insulating layer (6) without bird's beak can be formed;
It is possible to increase the density of elements.

〔発明の効果〕〔Effect of the invention〕

本発明に係る清秋半導体装置の形成方法は、絶縁性基板
上に非単結晶薄膜半導体層を形成し、該半導体1舗上に
選択的に耐酸化膜を形成する。その後、酸化性雰囲気中
で全面にエネルギービームを照射して露出している半導
体を−を酸化すると共に、耐酸化股下の半導体層を熱処
理するようにしたので、素子分1iSli領域となる選
択酸化1−の形成と、耐酸化股下の活性層となる半導体
層の結晶改善を同時に行なうことができ、また選択酸化
時におけるバーズビーク現象の発生を抑制できると共に
、ビーム照射の際のli性層へのキャッピング工程を省
(ことができる。従って、製造」二枚を簡略化すること
ができると共に、半導体素子の高集積化を図ることがで
きる。
In the method for forming a semiconductor device according to the present invention, a non-single crystal thin film semiconductor layer is formed on an insulating substrate, and an oxidation-resistant film is selectively formed on the semiconductor layer. After that, we irradiated the entire surface with an energy beam in an oxidizing atmosphere to oxidize the exposed semiconductor, and also heat-treated the semiconductor layer under the oxidation-resistant crotch, so that the selective oxidation 1 which becomes the 1iSli region for each element - can be formed at the same time as the crystalline improvement of the semiconductor layer which becomes the active layer of the oxidation-resistant crotch, and can suppress the occurrence of bird's beak phenomenon during selective oxidation, as well as capping the lithium layer during beam irradiation. Therefore, the manufacturing process can be simplified, and the semiconductor device can be highly integrated.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本実施例に係る薄膜半導体装置の形成方法を
示す土程図である。 (1)は5i02絶縁物、(2)は多結晶シリコン層(
活性層) 、f3)ハS+02v化膜、!4) ハS 
i、+N 4薄膜、(5)はエキシマレーザ、(6)は
フィールド絶縁層、(7)は5i(h酸化膜、(8)は
多結晶シリコン層、(9)はゲート電極、(10)はゲ
ート絶縁膜、(11)はソース領域、(12)はドレイ
ン領域である。
FIG. 1 is a stage diagram showing a method for forming a thin film semiconductor device according to this embodiment. (1) is a 5i02 insulator, (2) is a polycrystalline silicon layer (
Active layer), f3) HaS+02v film,! 4) HaS
i, +N 4 thin films, (5) is excimer laser, (6) is field insulating layer, (7) is 5i (h oxide film, (8) is polycrystalline silicon layer, (9) is gate electrode, (10) is a gate insulating film, (11) is a source region, and (12) is a drain region.

Claims (1)

【特許請求の範囲】 絶縁性基板上に非単結晶薄膜半導体層を形成する工程、 該半導体層上に選択的に耐酸化膜を形成する工程、 酸化性雰囲気中で全面にエネルギービームを照射して露
出している上記半導体層を酸化すると共に、耐酸化膜下
の上記半導体層を熱処理する工程とを有する薄膜半導体
層の形成方法。
[Claims] A step of forming a non-single crystal thin film semiconductor layer on an insulating substrate, a step of selectively forming an oxidation-resistant film on the semiconductor layer, and a step of irradiating the entire surface with an energy beam in an oxidizing atmosphere. A method for forming a thin film semiconductor layer, comprising the steps of oxidizing the exposed semiconductor layer and heat-treating the semiconductor layer under the oxidation-resistant film.
JP18606188A 1988-07-26 1988-07-26 Method of forming thin film semiconductor layer Expired - Fee Related JP2718074B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18606188A JP2718074B2 (en) 1988-07-26 1988-07-26 Method of forming thin film semiconductor layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18606188A JP2718074B2 (en) 1988-07-26 1988-07-26 Method of forming thin film semiconductor layer

Publications (2)

Publication Number Publication Date
JPH0235710A true JPH0235710A (en) 1990-02-06
JP2718074B2 JP2718074B2 (en) 1998-02-25

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ID=16181707

Family Applications (1)

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Country Status (1)

Country Link
JP (1) JP2718074B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5175123A (en) * 1990-11-13 1992-12-29 Motorola, Inc. High-pressure polysilicon encapsulated localized oxidation of silicon
US5580815A (en) * 1993-08-12 1996-12-03 Motorola Inc. Process for forming field isolation and a structure over a semiconductor substrate
US6083810A (en) * 1993-11-15 2000-07-04 Lucent Technologies Integrated circuit fabrication process
US7259053B2 (en) * 2003-09-22 2007-08-21 Dongbu Electronics Co., Ltd. Methods for forming a device isolation structure in a semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5175123A (en) * 1990-11-13 1992-12-29 Motorola, Inc. High-pressure polysilicon encapsulated localized oxidation of silicon
USRE35294E (en) * 1990-11-13 1996-07-09 Motorola, Inc. Polysilicon encapsulated localized oxidation of silicon
US5580815A (en) * 1993-08-12 1996-12-03 Motorola Inc. Process for forming field isolation and a structure over a semiconductor substrate
US5707889A (en) * 1993-08-12 1998-01-13 Motorola Inc. Process for forming field isolation
US6083810A (en) * 1993-11-15 2000-07-04 Lucent Technologies Integrated circuit fabrication process
US7259053B2 (en) * 2003-09-22 2007-08-21 Dongbu Electronics Co., Ltd. Methods for forming a device isolation structure in a semiconductor device

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