JPH0234185B2 - - Google Patents
Info
- Publication number
- JPH0234185B2 JPH0234185B2 JP56099695A JP9969581A JPH0234185B2 JP H0234185 B2 JPH0234185 B2 JP H0234185B2 JP 56099695 A JP56099695 A JP 56099695A JP 9969581 A JP9969581 A JP 9969581A JP H0234185 B2 JPH0234185 B2 JP H0234185B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- chip
- lands
- connection
- finger
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 10
- 239000011295 pitch Substances 0.000 description 7
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical group [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明はフイルムキヤリアにより複数のICチ
ツプを基板に実装する構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure for mounting a plurality of IC chips on a substrate using a film carrier.
従来におけるICチツプの基板への実装構造を
第1図により説明する。 A conventional mounting structure of an IC chip on a board will be explained with reference to FIG.
図において1はICチツプ、2はこのICチツプ
1に形成された複数の接続ランド、3はフインガ
ーリード、4は基板上に平行かつ蛇行状に形成さ
れた複数本の配線、5は各配線4の一端に設けら
れた端子引出線である。 In the figure, 1 is an IC chip, 2 is a plurality of connection lands formed on this IC chip 1, 3 is a finger lead, 4 is a plurality of wires formed in parallel and meandering on the substrate, and 5 is each wire. This is a terminal lead wire provided at one end of 4.
前記ICチツプ1に形成された各接続ランド2
とフインガーリード3は位置合わせしてインナボ
ンデイングにより接続され、また各フインガーリ
ード3と基板上の対応する配線4は位置合わせし
てアウタボンデイングにより接続されており、こ
れにより複数のICチツプ1が配線4上の所定の
位置に実質的に直線状に配置されて各々実装され
ている。 Each connection land 2 formed on the IC chip 1
and the finger leads 3 are aligned and connected by inner bonding, and each finger lead 3 and the corresponding wiring 4 on the board are aligned and connected by outer bonding. are arranged substantially linearly and mounted at predetermined positions on the wiring 4, respectively.
なお、図中6はフインガーリード3と基板上の
配線4との接続点を示している。 Note that 6 in the figure indicates a connection point between the finger lead 3 and the wiring 4 on the board.
しかし、一般に基板上に形成される配線のピツ
チは、ICチツプに形成される接続ランドのピツ
チよりも粗いので、上述した従来の実装構造では
1個のICチツプに対する接続点数が多い程、基
板上の配線の占める面積が大きくなるという問題
があり、また端子引出線を任意の位置から引き出
すことができないので、そのピツチが小さくかつ
線長が長くなるという問題も有している。 However, in general, the pitch of wiring formed on a board is rougher than the pitch of connection lands formed on an IC chip, so in the conventional mounting structure described above, the more connections there are for one IC chip, the more There is a problem that the area occupied by the wiring becomes large, and since the terminal lead wire cannot be drawn out from any arbitrary position, there is also a problem that the pitch is small and the wire length becomes long.
本発明は基板上の配線を最小面積に抑えられる
と共に、複数のICチツプに対しての共通配線が
可能で、かつ端子引出線を大きなピツチで短く引
き出すことのできる実装構造を得ることを目的と
する。 The object of the present invention is to obtain a mounting structure in which the area of wiring on a board can be kept to a minimum, common wiring is possible for multiple IC chips, and terminal lead-out lines can be drawn out in short lengths with a large pitch. do.
そのため、本発明は、複数のICチツプを各々
基板上の配線に接続して実装するためのICチツ
プの実装構造において、前記複数のICチツプが
実質的に直線状に並ぶように配置される基板上の
領域に、各ICチツプに設けられる少なくとも1
種類の複数の接続ランドと対応する複数本の配線
から成るコの字形の複数の配線ブロツクを形成
し、かつ前記複数の配線と前記ICチツプの複数
の接続ランドとに対応するコの字形の複数のフイ
ンガーリードを有するフイルムキヤリアを備え、
各ICチツプの複数の接続ランドをフイルムキヤ
リアのフインガーリードを介して対応する配線ブ
ロツクの配線に各々接続すると共に、このフイン
ガーリードにより隣合う配線ブロツクを直列に接
続したことを特徴とする。 Therefore, the present invention provides an IC chip mounting structure for mounting a plurality of IC chips by connecting them to wiring on a board, in which the plurality of IC chips are arranged substantially in a straight line. In the upper area, at least one
A plurality of U-shaped wiring blocks are formed by a plurality of connection lands of a different type and a plurality of corresponding wirings, and a plurality of U-shaped wiring blocks corresponding to the plurality of wirings and a plurality of connection lands of the IC chip are formed. Equipped with a film carrier with finger leads,
It is characterized in that a plurality of connection lands of each IC chip are connected to the wiring of the corresponding wiring block through the finger leads of the film carrier, and that adjacent wiring blocks are connected in series by the finger leads.
そして、前記基板に形成された複数本の配線
は、端子引出線を有するものとする。 The plurality of wires formed on the substrate have terminal lead lines.
また、前記ICチツプの接続用ランドは複数の
真の接続用ランドのみを有し、該接続用ランドを
フイルムキヤリアのフインガーリードを介して対
応する配線ブロツクの配線に接続するか、または
ICチツプの接続用ランドは複数の真の接続用ラ
ンドと複数のダミーの接続用ランドを有し、真の
接続用ランドをフイルムキヤリアのフインガーリ
ードを介して対応する配線ブロツクの配線に接続
すると共に、該配線ブロツクに隣接する配線ブロ
ツクの配線にダミーの接続用ランドを前記フイン
ガーリードを介して接続したことを特徴とする。 Further, the connection lands of the IC chip have only a plurality of true connection lands, and the connection lands are connected to the wiring of the corresponding wiring block via the finger leads of the film carrier, or
The connecting land of the IC chip has multiple true connecting lands and multiple dummy connecting lands, and the true connecting lands are connected to the wiring of the corresponding wiring block via the finger leads of the film carrier. In addition, a dummy connection land is connected to the wiring of a wiring block adjacent to the wiring block via the finger lead.
以下本発明の実施例を図面により説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第2図は本発明の第1の実施例を示す一部分平
面図で、図において7はICチツプ、8はこのIC
チツプ7に形成した複数の接続ランド、9はフイ
ルム、10はフイルム9上に形成した平面形状が
コの字形等の複数のフインガーリードであり、こ
のフイルム9とフインガーリード10は本実施例
で使用するフイルムキヤリアを成す。 FIG. 2 is a partial plan view showing the first embodiment of the present invention. In the figure, 7 is an IC chip, and 8 is this IC chip.
A plurality of connection lands are formed on the chip 7, 9 is a film, and 10 is a plurality of finger leads formed on the film 9 and having a U-shaped planar shape. Forms the film carrier used in
11は基板上に形成した各々コの字形の複数の
配線ブロツクで、各配線ブロツク11は前記フイ
ンガーリード10と対応する複数本の配線12か
ら成り、これらのうちの任意の配線12から端子
引出線13が引き出してある。 Reference numeral 11 denotes a plurality of U-shaped wiring blocks formed on the board, each wiring block 11 consisting of a plurality of wires 12 corresponding to the finger leads 10, and a terminal drawn out from any one of these wires 12. Line 13 is drawn out.
そこで、本実施例はICチツプ7の各接続ラン
ド8とフイルム9上のフインガーリード10とを
位置合わせして両者をインナボンデイングにより
接続し、そして各ICチツプ7を基板上に実質的
に直線状に並ぶように各配線ブロツク11上に配
置すると共に、フインガーリード10と配線ブロ
ツク11の配線12とが蛇行状を成すように位置
合わせして、通常の整列順序でアウタボンデイン
グによる接続を行う以外に、逆の順序にも接続を
行つて、各々のICチツプ7を基板状に実装する
と共に、隣接する配線ブロツク11の配線12を
フインガーリード10により直列に結線したもの
である。 Therefore, in this embodiment, each connection land 8 of the IC chip 7 and the finger lead 10 on the film 9 are aligned and connected by inner bonding, and each IC chip 7 is placed substantially straight on the substrate. The finger leads 10 and the wiring 12 of the wiring block 11 are arranged in a meandering pattern on each wiring block 11, and connections are made by outer bonding in the normal arrangement order. In addition, connections are made in the reverse order, and each IC chip 7 is mounted on a substrate, and the wirings 12 of adjacent wiring blocks 11 are connected in series by finger leads 10.
なお、図中14はフインガーリード10と配線
12との接続点を示している。 Note that 14 in the figure indicates a connection point between the finger lead 10 and the wiring 12.
以上説明したように第1の実施例では、ICチ
ツプの接続ランドにフイルム上に形成したフイン
ガーリードを接続し、基板上には複数本の短い配
線から成る配線ブロツクを形成しておき、このフ
インガーリードと配線とが蛇行状を成すように接
続しているため、基板上の配線を最小面積に抑え
ることができると共に複数のICチツプに対して
共通配線が可能となり、また端子引出線を任意の
位置から引き出して形成することができるため、
端子引出線の線長を短くすることができると共に
ピツチを大きくとることができる。 As explained above, in the first embodiment, the finger leads formed on the film are connected to the connection lands of the IC chip, and a wiring block consisting of a plurality of short wirings is formed on the substrate. Since the finger leads and the wiring are connected in a meandering manner, the wiring on the board can be kept to a minimum area, and common wiring can be used for multiple IC chips. Because it can be pulled out and formed from any position,
The length of the terminal lead-out wire can be shortened and the pitch can be increased.
また、フインガーリードと配線との接続点の列
がチツプ上の接続ランドとフインガーリードとの
接続点の列と並行であるため、接続のための位置
合わせの際、y軸方向のずれを余り考慮しなくて
済み、従つて接続点のピツチをことさら大きくと
る必要がないという利点もある。 In addition, since the row of connection points between the finger leads and the wiring is parallel to the row of connection points between the connection lands on the chip and the finger leads, it is possible to avoid misalignment in the y-axis direction when aligning for connection. There is also the advantage that there is no need to take much consideration and therefore there is no need to make the pitch of the connection points particularly large.
次に本発明の第2の実施例を第3図により説明
する。 Next, a second embodiment of the present invention will be described with reference to FIG.
第3図は第2の実施例を示す一部分平面図で、
図において15はICチツプ、16はこのICチツ
プ15に形成した複数の接続ランド、17は同じ
くICチツプ15に形成したダミーの接続ランド、
18はフイルム、19はフイルム18上に形成し
た平面形状コの字形等の複数のフインガーリー
ド、20は基板上に形成された平面形状コの字形
等の複数配線ブロツク、21は各配線ブロツク2
0を構成する配線、22は端子引出線である。 FIG. 3 is a partial plan view showing the second embodiment,
In the figure, 15 is an IC chip, 16 is a plurality of connection lands formed on this IC chip 15, 17 is a dummy connection land also formed on the IC chip 15,
18 is a film; 19 is a plurality of finger leads formed on the film 18 and having a U-shaped planar shape; 20 is a plurality of wiring blocks formed on a substrate and has a U-shaped planar shape; and 21 is each wiring block 2.
Wires 0 and 22 are terminal lead lines.
この実施例では、インナボンデイング時にIC
チツプ15の接続ランド16の一部または全部を
フイルム18上に形成したフインガーリード19
によりダミーの接続ランド17と結線し、このよ
うにしたデバイスを、各ICチツプ15が配線ブ
ロツク20上に位置するように基板上に実質的に
直線状に並べて配置し、第1の実施例と同様にア
ウタボンデイングにより接続して、ICチツプ1
5を基板上に実装したものである。 In this example, the IC is
Finger leads 19 in which part or all of the connection lands 16 of the chip 15 are formed on the film 18.
The device is connected to the dummy connection land 17 using the method shown in FIG. Similarly, connect the IC chip 1 using outer bonding.
5 is mounted on a board.
以上説明した第2の実施例は、チツプサイズな
かんずくICチツプの幅に対して比較的接続ラン
ドの数が少ない場合に有効な方法であり、第1の
実施例と同様の効果が得られる他、フインガーリ
ードの整列が乱れにくいので、アウタボンデイン
グを行う際の作業性がよいという利点がある。 The second embodiment described above is an effective method when the number of connection lands is relatively small compared to the chip size, especially the width of the IC chip, and in addition to obtaining the same effects as the first embodiment, Since the alignment of the finger leads is less likely to be disturbed, there is an advantage that workability when performing outer bonding is good.
以上各実施例を示して述べた如く、本発明は複
数のICチツプに対して最小限の面積で共通配線
が得られ、また必要に応じて任意の位置から多数
の端子引出線を大きなピツチでかつ短く引き出せ
るので、例えばデイスプレイの駆動回路等におけ
るICチツプの実装構造として有効である。 As described above with reference to each of the embodiments, the present invention enables common wiring to be obtained for multiple IC chips in a minimum area, and also enables a large number of terminal lead-out lines to be connected from arbitrary positions at large pitches as needed. Moreover, since it can be pulled out in a short length, it is effective as a mounting structure for IC chips in display drive circuits, etc., for example.
第1図は従来のICチツプの実装構造を示す一
部分平面図、第2図は本発明によるICチツプの
実装構造の一実施例を示す一部分平面図、第3図
は本発明の他の実施例を示す一部分平面図であ
る。
7,15……ICチツプ、8,16……接続ラ
ンド、9,18……フイルム、10,19……フ
インガーリード、11,20……配線ブロツク、
12,21……配線、13,22……端子引出
線、14……接続点、17……ダミーの接続ラン
ド。
FIG. 1 is a partial plan view showing a conventional IC chip mounting structure, FIG. 2 is a partial plan view showing an embodiment of the IC chip mounting structure according to the present invention, and FIG. 3 is a partial plan view showing another embodiment of the IC chip mounting structure according to the present invention. FIG. 7,15...IC chip, 8,16...Connection land, 9,18...Film, 10,19...Finger lead, 11,20...Wiring block,
12, 21... Wiring, 13, 22... Terminal lead wire, 14... Connection point, 17... Dummy connection land.
Claims (1)
して実装するためのICチツプの実装構造におい
て、 前記複数のICチツプが実質的に直線状に並ぶ
ように配置される基板上の領域に、各ICチツプ
に設けられる少なくとも1種類の複数の接続ラン
ドと対応する複数本の配線から成るコの字形の複
数の配線ブロツクを形成し、 かつ前記複数の配線と前記ICチツプの複数の
接続ランドとに対応するコの字形の複数のフイン
ガーリードを有するフイルムキヤリアを備え、 各ICチツプの複数の接続ランドをフイルムキ
ヤリアのフインガーリードを介して対応する配線
ブロツクの配線に各々接続すると共に、このフイ
ンガーリードにより隣合う配線ブロツクを直列に
接続したことを特徴とするICチツプの実装構造。 2 基板上に形成された複数本の配線は、端子引
出線を有することを特徴とする特許請求の範囲第
1項記載のICチツプの実装構造。 3 前記ICチツプの接続用ランドは複数の真の
接続用ランドのみを有し、該接続用ランドをフイ
ルムキヤリアのフインガーリードを介して対応す
る配線ブロツクの配線に接続したことを特徴とす
る特許請求の範囲第1項記載のICチツプの実装
構造。 4 前記ICチツプの接続用ランドは複数の真の
接続用ランドと複数のダミーの接続用ランドを有
し、真の接続用ランドをフイルムキヤリアのフイ
ンガーリードを介して対応する配線ブロツクの配
線に接続すると共に、該配線ブロツクに隣接する
配線ブロツクの配線にダミーの接続用ランドを前
記フインガーリードを介して接続したことを特徴
とする特許請求の範囲第1項記載のICチツプの
実装構造。[Scope of Claims] 1. In an IC chip mounting structure for mounting a plurality of IC chips by connecting each to wiring on a substrate, the plurality of IC chips are arranged so as to be substantially lined up in a straight line. A plurality of U-shaped wiring blocks each formed of a plurality of wirings corresponding to a plurality of connection lands of at least one type provided on each IC chip are formed in an area on the substrate, and the wiring blocks are connected to the plurality of wirings and the IC chip. A film carrier is provided with a plurality of U-shaped finger leads corresponding to a plurality of connection lands of each IC chip, and the plurality of connection lands of each IC chip are connected to the wiring of the corresponding wiring block via the finger leads of the film carrier. An IC chip mounting structure characterized in that adjacent wiring blocks are connected in series through these finger leads. 2. The IC chip mounting structure according to claim 1, wherein the plurality of wirings formed on the substrate have terminal lead lines. 3. A patent characterized in that the connecting lands of the IC chip have only a plurality of true connecting lands, and the connecting lands are connected to the wiring of the corresponding wiring block via the finger leads of the film carrier. A mounting structure for an IC chip according to claim 1. 4 The connection land of the IC chip has a plurality of true connection lands and a plurality of dummy connection lands, and the true connection land is connected to the wiring of the corresponding wiring block via the finger lead of the film carrier. 2. The IC chip mounting structure according to claim 1, wherein a dummy connection land is connected to the wiring of a wiring block adjacent to the wiring block via the finger lead.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9969581A JPS582037A (en) | 1981-06-29 | 1981-06-29 | Mounting method for ic and the like |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9969581A JPS582037A (en) | 1981-06-29 | 1981-06-29 | Mounting method for ic and the like |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS582037A JPS582037A (en) | 1983-01-07 |
JPH0234185B2 true JPH0234185B2 (en) | 1990-08-01 |
Family
ID=14254178
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9969581A Granted JPS582037A (en) | 1981-06-29 | 1981-06-29 | Mounting method for ic and the like |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS582037A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6034023A (en) * | 1983-08-04 | 1985-02-21 | Oki Electric Ind Co Ltd | Mounting of semiconductor chip on substrate |
JPH01201989A (en) * | 1988-02-05 | 1989-08-14 | Semiconductor Energy Lab Co Ltd | Wiring construction on glass substrate |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5628110B2 (en) * | 1971-12-28 | 1981-06-29 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6023853Y2 (en) * | 1979-08-10 | 1985-07-16 | 松下電器産業株式会社 | jumper cable |
-
1981
- 1981-06-29 JP JP9969581A patent/JPS582037A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5628110B2 (en) * | 1971-12-28 | 1981-06-29 |
Also Published As
Publication number | Publication date |
---|---|
JPS582037A (en) | 1983-01-07 |
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