JPH0234822A - Semiconductor optical switch and its manufacture - Google Patents

Abstract

PURPOSE:To improve low-loss characteristics and to obtain a semiconductor optical switch which has no wavelength dependency by implanting carriers in a part of a waveguide layer through an area with relatively low resistance in a clad layer other than a high-resistance area with a voltage applied between 1st and 2nd electrodes. CONSTITUTION:The semiconductor optical switch is constituted in double heterostructure by sandwiching the waveguide layer 6 between a semiconductor substrate 2 of a 1st conduction type having a forbidden band larger than its forbidden band and the clad layer 8 of a 2nd conduction type from above and below. Consequently, the low-resistance area is formed at a part of the waveguide layer 6 by plasma effect. Then incident light is reflected totally at a boundary without depending upon its wavelength. Further, the entire surface of the waveguide 6 is a low-carrier layer sandwiched between the semiconductor substrate 2 which has high carrier density and clad layer 8 and then the loss is reduced. Consequently, optical switching is carried out at a high extinction ratio with reduced transmission loss.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor optical switch and a method for manufacturing the same, and particularly to a semiconductor optical switch that is composed of a semiconductor optical waveguide layer and that switches optical paths essential for optical communication and optical information processing. Related to semiconductor optical switches.

[Conventional technology]

Conventional optical switches include those that use polarization of light due to the acousto-optic effect of the optical transmission medium, those that use polarization of light due to the electro-optic effect of the medium, and those that use the electro-optic effect to change the coupling coefficient of a directional coupler. There are also devices that combine a directional coupler and an optical phase modulator. However, none of these waveguides satisfy all the basic characteristics of a waveguide switch, such as low loss characteristics, low crosstalk characteristics, and high speed. As a solution to these problems, proposals have been made to inject carriers into the waveguide layer to lower its refractive index and to utilize this change in refractive index for optical switches.

For example, in the semiconductor optical switch shown in Japanese Patent Application Laid-Open No. 60-173519, non-doped InGaAsP
The leading waveguide layer has a so-called double heterostructure sandwiched between an n-type 1nP substrate with a larger forbidden band and a p-type 1nP grading layer, and current flows in the forward direction in the p-n junction of this double heterostructure. is used to inject carriers into the InGaAs optical waveguide layer. And this 1nGa
The refractive index is lowered by the plasma effect in the As optical waveguide layer. However, the above-mentioned Japanese Patent Application Laid-Open No. 60-17351
In the semiconductor optical switch No. 9, the cladding layer is formed only in a part of the waveguide layer, and the other part of the waveguide layer is in contact with air, so the light passing through the waveguide layer is confined in the vertical direction. Therefore, the loss has not yet been sufficiently improved and the applications have been limited.

Furthermore, for example, in the semiconductor optical switch shown in Japanese Patent Application Laid-open No. 60-134219, an InP substrate and this 1nP
InGaAs P layer and InP layered in order on the substrate
It has a superlattice layer consisting of layers and an InP grading layer on the superlattice layer, and carriers are injected by passing a current through the superlattice layer. Then, the absorption edge wavelength of light is shifted by the band filling effect in this superlattice layer. Thus, Kramers φ Kronitz (Kr
aiers-Kronig) relationship, the refractive index near the absorption edge wavelength is lowered. However, the above-mentioned Japanese Patent Application Publication No. 6
In the semiconductor optical switch of No. 0-134219, the loss has not yet been sufficiently improved, and furthermore, the wavelength dependence that the applicable wavelength of light is limited to approximately match the bandgap energy Eg of the semiconductor is a problem. Yes, and its uses were limited.

[Problem to be solved by the invention]

As described above, conventional semiconductor optical switches do not fully satisfy low loss characteristics, and some have wavelength dependence, among other problems.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor optical switch with improved low loss characteristics and no wavelength dependence, and a manufacturing method thereof with high yield.

[Means to solve the problem]

A semiconductor optical switch according to the present invention includes a semiconductor substrate of a first conductivity type having a first electrode formed on one surface, and a semiconductor substrate formed on the other surface of the semiconductor substrate, and has a forbidden band smaller than that of the semiconductor substrate and a carrier concentration. a ridge-shaped waveguide layer with a low waveguide layer; a cladding layer of a second conductivity type formed on the ridge portion of this waveguide layer and having a forbidden band smaller than that of the waveguide layer and a higher carrier concentration; A high resistance region is formed in a part of the cladding layer, and a second electrode is formed on the cladding layer. It is characterized by injecting carriers into a part of the waveguide layer through a region other than the region having relatively low resistance.

Here, the high resistance region may be omitted by further forming the cladding layer into a ridge shape.

Further, the method for manufacturing a semiconductor optical switch according to the present invention includes a first step of growing a first epitaxial layer having a forbidden band smaller than that of the semiconductor substrate and a lower carrier concentration on the semiconductor substrate of the first conductivity type; a second step of growing a second epitaxial layer of a second conductivity type having a bandgap smaller than that of the first epitaxial layer and a higher carrier concentration on the first epitaxial layer; A third step of selectively etching the layers to form a waveguide layer consisting of a ridge-shaped first epitaxial layer and a cladding layer consisting of a second epitaxial layer; The method is characterized by comprising a fourth step of forming a resistance region, and a fifth step of forming a first electrode on the cladding layer and a second electrode on the bottom surface of the semiconductor substrate. Here, in the fifth step, the portion corresponding to the high resistance region may be removed.

[Effect]

In the semiconductor optical switch of the present invention, the waveguide layer has a double heterostructure in which the waveguide layer is sandwiched from above and below between a semiconductor substrate of a first conductivity type and a cladding layer of a second conductivity type, which has a forbidden band larger than that of the waveguide layer. As a result, a low refraction region is created in a part of the waveguide layer due to the plasma effect, and incident light is totally reflected at the boundary thereof, regardless of its wavelength. Furthermore, since the entire waveguide layer is a low carrier layer sandwiched between a semiconductor substrate with a high carrier concentration and a cladding layer, loss is reduced. As a result, optical switching with a high extinction ratio and reduced transmission loss is performed.

Further, in the manufacturing method of the present invention, the semiconductor optical switch as described above can be manufactured with a high yield through a combination of simple steps.

〔Example〕

Hereinafter, the present invention will be specifically described based on illustrated embodiments.

FIG. 1 is a perspective view showing a semiconductor optical switch according to a first embodiment of the present invention, FIG. 2 is a plan view thereof, and FIG. 3 is a sectional view taken along line A-A in FIG. FIG. 4 is a sectional view taken along the line B--B in FIG. 2.

For example, an n-type InP lower cladding layer 4 with a high carrier concentration is formed on an n+-type 1nP substrate 2 with a high carrier concentration. On this n-type 1nP lower cladding layer 4, a low carrier concentration n-type InGaAs composed of quaternary elements is formed.
The P waveguide layer 6 is formed in a ridge shape. A p+ type InP cladding layer 8 with a high carrier concentration is formed on the ridge portion of the n-type InGaAsP waveguide layer 6. Furthermore, on this p+ type InP cladding layer 8, a p type InGaAsP cap layer 1 with a high carrier concentration is formed.
0 is formed.

As shown in FIGS. 1, 2, and 4, the two waveguides 12 and 14 with a waveguide width W have p+ type InG at the top and bottom.
It consists of a ridge-shaped n-type InGaAsP waveguide layer 6 sandwiched between an upper 0p+-type InP cladding layer 8 and an n-InP lower cladding layer 4, which intersect at an intersection angle of 2θ. are doing. And waveguide 1
2 has an input boat 16 and an output port 18, and the waveguide 14 has an input boat 20 and an output port 22. Further, as shown in FIGS. 1, 2, and 3, a switch section 24 is provided in an intersection region where these two waveguide layers 12, 14 intersect. Similar to the waveguide layer 12 and 14, this switch section 24 is constructed by connecting the upper and lower portions of the ridge portion of the low-type single-hole GaAsP waveguide layer 6 to the p + -type InGaAsP cap layer 10 and the p + -type InP cladding layer 8 . InP lower cladding layer 4
However, at this time, the n'''' type InGaAsP waveguide layer 6 with a small forbidden band is the p+ type with a larger forbidden band! nP cladding layer 8 and n
It is important that the structure is sandwiched from above and below by the 1nP type lower cladding layer 4, forming a so-called double heterostructure.

In this switch section 24, p+ type 1nGaAs P
An n-type electrode (not shown) is formed on the cap layer 10, and an n-type electrode (not shown) is formed on the bottom surface of the n-type InP substrate 2. Furthermore, in this switch section 24, silicon (S+), for example, is added to both sides of the p+ type 1nP cladding layer 8 formed on the ridge portion of the n-type InGaAs P waveguide layer 6 to increase the resistance. High resistance regions 26 and 28 are formed. Then, as shown in FIG. 2, two waveguide layers 12.1
4 is a high resistance region 2 in the p-type InP cladding layer 8
6.28 and other regions of relatively low resistance, they intersect in opposite directions at crossing angles θ.

Next, the operation of the apparatus of the first embodiment will be explained.

A predetermined voltage is applied between the n-type electrode and the n-type electrode to form a p+ type 1nP cladding layer 8 and an n-type 1nGaAsP waveguide layer 6.
, and an n-type InP lower cladding layer 4, when current is passed in the forward direction through the pn junction of the double heterostructure, carriers are injected. However, n+ type 1nP cladding layer 8
Since high-resistance regions 26.28 are formed on both sides of the n-type InGaAsP waveguide 6, the waveguide 6 passes through relatively low-resistance regions other than these high-resistance regions 25.26. This carrier injection is made only in the central region.

Therefore, carriers are not injected into both sides of the ridge portion of the n-type InGaAsP waveguide layer 6 located below the high resistance regions 26,28. That is, p-type InP cladding layer 8
The high-resistance regions 26 and 28 formed in the above region limit carrier injection to a predetermined region, and this restriction increases carrier injection efficiency. In this way, carriers are injected only into the central part of the n-type 1nGaAsP waveguide layer 6 and are confined there, so that the dielectric constant of that part decreases due to the plasma effect, and the refractive index decreases. Therefore, the n-type 1nGaAsP waveguide layer 6 is divided into three regions having different refractive indexes.

Now, the light incident from the input boat 16 of the waveguide 12 and the light incident from the input boat 20 of the waveguide 14 are divided into two beams if no voltage is applied between the p-type electrode and the n-type electrode. The output boat 18 of the waveguide 12 and the waveguide 14 pass through the n-type InGaAsP waveguide layer 6 of the switch section 24, where the waveguide layers 12 and 14 of the waveguide 12 and the waveguide 14 intersect, respectively.
It advances to the exit port 22 of. However, when a predetermined voltage is applied between the p-type electrode and the n-type electrode, the n-type InGa
When the refractive index at the center of the AsP waveguide layer 6 ridge portion decreases, the rate of change in refractive index is determined by Δn1 waveguide 12.1
The refractive index of n5n-type InGaAsP waveguide layer 6 and the waveguide 12.1 have a refractive index of 4.
Let θ be the intersection angle with The light is totally reflected at the boundary between regions of the waveguide layer 6 having different refractive indexes and travels to the output boat 22 of the waveguide 14, and similarly, the light incident from the input boat 20 of the waveguide 14 is transmitted to the waveguide 1.
Proceed to the second launch boat 18. In this way, the first
The semiconductor optical switch according to the embodiment performs a switching action on incident light, but here it is a so-called bidirectional switch that performs a switching action on incident light from two directions.

In the semiconductor optical switch according to the first embodiment, the entire surface of the ridge portion of the n-type 1nGa, AsP waveguide layer 6 is covered with the p+ pear-shaped 1nP rad layer 8. The light passing through the ridge portion of the P waveguide layer 6 is well confined in the vertical direction. Furthermore, since the carrier concentration of the n-type InGaAsP waveguide layer 6 is low, free carrier absorption is suppressed to a low level, and loss due to light absorption is small.

In addition, since the carrier concentration of the p+ pear-shaped 1nP rad layer 8 is high, the carrier-injected n-type InGaAsP
A plasma effect occurs throughout the waveguide layer 6, and the refractive index decreases more rapidly in a portion of the n-type InGaAsP waveguide layer 6 into which carriers are injected. and p-type In
Even if the P cladding layer 8 has a high carrier content, it does not allow much light to enter, so there is little loss due to light absorption.

Furthermore, since the plasma effect in which the refractive index is lowered by carrier injection is used, the change in the refractive index is large, and therefore low voltage driving is possible. Also, n-type InGa A
Since the switching action can be performed over a wide range of light having an energy smaller than the forbidden band width of the sP waveguide layer 6, wavelength dependence is eliminated within that range, and wavelength multiplexing becomes possible.

In the first embodiment, the waveguide layer is made of InGaAs.
Since P is used, it can be used for light with a wavelength longer than the forbidden wavelength of 1.2 μm, and it can cover the 1 to 3 μm band normally used in optical communications. Ga instead of Ga As P
If As is used, it can be used for a wider range of light having wavelengths longer than the forbidden band wavelength of 0.9 μm.

In the first embodiment, the waveguide layer 6 is formed of n-type InGaAsP with a low carrier concentration, but its conductivity type is not limited to the n-type. It may be formed from p'' type In Ga As P or non-doped i type In Ga As P.

However, since holes absorb more light than electrons, p-
n-type is more desirable than type.

An n+ type 1nP lower cladding layer 4 and a p+ pear-shaped 1n sandwiching an n-type 1nGaAsP waveguide layer 6 in a double heterostructure.
Each of the P rad layers 8 has a combination of n+ type and p+ type, but these conductivity types are swapped, and p
It may be a combination of an InP type lower cladding layer and an n+ type InP cladding layer. Of course, in this case, the substrate 2
becomes a p-type InP substrate. Furthermore, in the first embodiment, In P s I n Ga As
Although P semiconductor is used, for example, GaAs,
m-v group compound semiconductors such as Ga Sb sGa AN AS Sb may be used, and furthermore, Cd 5SCd S
e SZe S.

II-Vl group compound semiconductors such as ZeSe can also be used similarly.

Next, a semiconductor optical switch according to a second embodiment of the present invention will be described.

FIG. 5 is a plan view of a semiconductor optical switch according to the second embodiment, FIG. 6 is a cross-sectional view taken along line A-A in FIG. 5, and FIG. 7 is a cross-sectional view taken along line B-B in FIG. FIG.

For example, a p-type InP lower cladding layer 34 with a high carrier concentration is formed on a p-type 1nP substrate 32 with a high carrier concentration. On this p+ type InP lower cladding layer 34, low type InGaA with a low carrier concentration made of quaternary elements is formed.
The sP waveguide layer 36 is formed in a ridge shape. An n+ pear-shaped 1nP rad layer 38 with a high carrier concentration is formed on the ridge portion of the n-type InGaAsP waveguide layer 36. Furthermore, this n-type InP cladding layer 3
On layer 8, n+ type InGaAsP with high carrier concentration
A cap layer 40 is formed.

As shown in FIGS. 5 and 7, 2 of the waveguide width W
The main waveguides 42 and 44 are formed with an n-type InGaAsP cap layer 40 and an n-type InP cladding layer 38 on the top and bottom.
The ridge-shaped n- layer sandwiched between the lnP lower cladding layer 34
It consists of InGaAsP type waveguide layers 36, which intersect at a crossing angle of 2θ. The waveguide 42 has an input boat 46 and an output boat 48, and the waveguide 42 has an input boat 46 and an output boat 48.
4 has an entrance boat 50 and an exit boat 52. Further, as shown in FIGS. 5 and 6, a switch section 54 is provided in an intersection area where these two waveguide layers 42 and 44 intersect. This switch section 5
4 is n-type InGa similar to the waveguide layers 42 and 44.
The top and bottom of the ridge part of the AsP waveguide layer 36 are n+ type 1n.
The structure is sandwiched between the GaAsP cap layer 40, the n+ pear-shaped 1nP rad layer 38, and the p''lnP lower cladding layer 34, but at this time, the n-type I
It is important that the nGaAsP waveguide layer 36 has a so-called double heterostructure sandwiched between the n+ pear-shaped 1nP rad layer 38, which has a larger forbidden band, and the p+ type InP lower cladding layer 34. .

Furthermore, in this switch section 54, n-type InG
An n-type electrode (not shown) is formed on the aAsP cap layer 40, and an n-type electrode (not shown) is formed on the bottom surface of the p-type 1nP substrate 32.
A mold electrode (not shown) is formed. Furthermore, in this switch section 54, a part of the n+ type InP cladding layer 38 formed on the ridge part of the n type InGaAsP waveguide layer 36 is doped with, for example, zinc (Zn) to increase the resistance. A high resistance region 56 is formed.

Then, as shown in FIG. 5, two waveguide layers 42.
44 intersect the boundary between the high resistance region 56 and other relatively low resistance regions in the n-type 1nP cladding layer 38 in opposite directions at a crossing angle θ.

Next, the operation of the apparatus of the second embodiment will be explained.

The operation of this second embodiment is almost the same as that of the first embodiment, except that a predetermined voltage is applied between the n-type electrodes and the n+pear-shaped 1nP rad layer 38, n ″″
type 1nGaAsP waveguide layer 36, and p+pear type 1nP
When a current is passed in the forward direction through the p-n junction of the double heterostructure made of the lower cladding layer 34, a high resistance region 56 is formed in one half of the n+ type In.22991 layer 38.
The carriers pass through a relatively low resistance region other than the n-high resistance region 56 in the n-type 1nP cladding layer 38, and pass through the n-type 1nP cladding layer 38.
Only one half of the type InGaAsP waveguide 46 is implanted. Therefore, the n-type I that is not located below the high resistance region 56
No carriers are injected into the other half of the n GaAs P waveguide layer 46 .

That is, the high resistance region 56 formed in the n+ type InP cladding layer 38 limits carrier injection to a predetermined region, and this restriction increases carrier injection efficiency.

In this way, carriers are injected into only one half of the n-type InGaAsP waveguide layer 36 and confined there, so that the dielectric constant of that part decreases due to the plasma effect, and the refractive index decreases.

Therefore, the n-type InGaAsP waveguide layer 36 is
It is divided into two regions with different refractive indexes.

Now, as shown in FIG. 5, if no voltage is applied between the n-type electrodes, the light incident from the input port 46 of the waveguide 42 will pass through the n-type InGaAs.
It travels through the P waveguide layer 36 to the output port 48 of the waveguide 42 . However, if a predetermined voltage is applied between the n-type electrodes and the refractive index of one half of the n-type InGaAsP waveguide layer 36 decreases, the waveguide 42
The light incident from the input boat 46 is an n″″ type In G
The light is totally reflected at the boundary between two regions of the a As P waveguide layer 36 having different refractive indexes, and travels to the output boat 52 of the waveguide 44 .

In this way, the semiconductor switch according to the second embodiment performs a switching action on incident light, whereas the semiconductor switch according to the first embodiment performs a switching action on incident light from two directions, a so-called bidirectional switch. In contrast to the switch, this second embodiment is a so-called one-way switch that performs a switching action only on incident light from one direction. All of the various effects of the first embodiment described above are also present in the second embodiment.

In the second embodiment, the waveguide layer 36 is formed of n-type InGaAsP with a low carrier concentration, but its conductivity type is not limited to the n-type. p-type 1nGaAsP or non-doped 1
It may be formed from type InGaAsP. However, since holes absorb more light than electrons, n-type is more desirable than p-type.

Furthermore, the p-type 1nP lower cladding layer 44 and the n-type InP cladding layer 48, which sandwich the n-type InGaAsP waveguide layer 46 in a double heterostructure, are a combination of p+ type and n+ type, respectively. These conductivity types are exchanged, and the n+ type InP lower cladding layer and the p
It may also be a combination of type 1nP cladding layers. Of course, in this case, the substrate 32 will be an n-type InP substrate. Furthermore, in the second embodiment, In P, In
Although GaAs P semiconductor is used, for example, GaAsP semiconductor is used.
m-v group compound semiconductors such as As sGa Sb and Ga AN As Sb may be used, and furthermore, Cd
5SCdSe.

II-Vl group compound semiconductors such as Ze S and Ze Se can also be used similarly.

Next, a semiconductor optical switch according to a third embodiment of the present invention will be described.

FIG. 8 is a sectional view showing a cross section of a switch section of a semiconductor optical switch according to a third embodiment of the present invention.
Similarly to the embodiment, for example, n+ type 1n with high carrier concentration
An n+ pear-shaped 1nP lower cladding layer 64 with a high carrier concentration is formed on the P substrate 62. On this n-type InP lower cladding layer 64, a ridge-shaped n-type InGaAsP waveguide layer 66 with a low carrier concentration made of a quaternary element is formed. And this n-type InGaAs
On the ridge portion of the P waveguide layer 66, there is a p layer with a high carrier concentration.
An InP type cladding layer 68 is formed in a ridge shape. Further, on the ridge portion of this p-type 1nP cladding layer 8, a p+-type 1nGaAsP cap layer 70 with a high carrier concentration is formed. That is, the waveguide has a width W,
Two waveguide layers intersecting at a crossing angle of 2θ (not shown)
In the switch section 72 provided in the intersection area of the n-type InGaAsP waveguide layer 66 with a small forbidden band,
is a p-type InP cladding layer 6 whose forbidden band is larger than this.
8 and an n-type 1nP lower cladding layer 64, forming a so-called double heterostructure.

In this switch section 72, p+ type 1nGaAs P
An n-type electrode (not shown) is formed on the cap layer 70, and an n-type electrode (not shown) is formed on the bottom surface of the n+ type InP substrate 62. As described above, the semiconductor optical switching according to the third embodiment is performed in the high resistance regions 26 and 27 formed at both ends of the p+ type InP cladding layer 8 of the first embodiment shown in FIG. For example, the corresponding portion is removed by etching to form a ridge-shaped p+ type InP.
A cladding layer 68 is formed, and a p+ type InGaAs P cap layer 70 is further formed on the ridge portion of this p+ type InP cladding layer 8.

Next, the operation of the apparatus of the third embodiment will be explained.

The operation of the third embodiment is similar to that of the first embodiment, by applying a predetermined voltage between the p-type electrode and the n-type electrode, and forming the p+ type 1nP cladding layer 68, the n-type 1nGaAsP
Waveguide layer 66 and n+ type 1nP lower cladding layer 64
When a current flows in the forward direction through the p-n junction of the double heterostructure consisting of
is injected only into the center of the body. Therefore, the n- type InGa that is not located below the ridge of the n+-type InP cladding layer 68
No carriers are injected into both sides of the AsP waveguide layer 46.

In this way, carriers are injected only into the central portion of the low-type In Ga As P waveguide layer 66 and are confined there, so that the dielectric constant of that portion decreases due to the plasma effect, and the refractive index decreases.

Therefore, the n-type InGaAsP waveguide layer 66 is
It is divided into three regions with different refractive indexes. Therefore, the light incident from the two waveguides is totally reflected at the boundaries between regions of the n-type 1nGaAs P waveguide layer 66 that have mutually different refractive indexes, that is, at the boundaries from the high refractive index region to the low refractive index region. , change its course.

In this way, the semiconductor optical switch according to the third embodiment performs a switching action on incident light, but similarly to the first embodiment, it performs a switching action on incident light from two directions, so-called. It is a two-way switch. The third embodiment also has all of the various effects of the first embodiment described above.

Next, a semiconductor optical switch according to a fourth embodiment of the present invention will be described.

FIG. 9 is a sectional view showing a cross section of a switch portion of a semiconductor optical switch according to a fourth embodiment of the present invention. In this semiconductor optical switch, a p-type InP lower cladding layer 84 with a high carrier concentration is formed on a p+-type InP substrate 82 with a high carrier concentration, for example, as in the second embodiment. On this p + -type InP lower cladding layer 84 , an n - -type InGaAsP waveguide layer 86 made of a quaternary layer and having a low carrier concentration is formed in a ridge shape. And this n
On the ridge portion of the −-type InGaAsP waveguide layer 86, an n+-type InP cladding layer 88 with a high carrier concentration is formed in the shape of a ridge on one side.

Further, on the ridge portion of this n+ pear-shaped 1nP rad layer 88, an n-type InGaAsP cap layer 90 with a high carrier concentration is formed. That is, in the switch section 92 provided in the intersection region of two waveguide layers (not shown) that have a waveguide width W and intersect at an intersection angle of 2θ,
N-type InGaAsP waveguide layer 86 with small forbidden band
is the n+ pear-shaped 1nP rad layer 8 whose forbidden band is larger than this.
8 and a p+ type InP lower cladding layer 84, forming a so-called double heterostructure.

In this switch section 92, an n-type electrode (not shown) is formed on the n-type 1nGaAsP cap layer 90,
Further, a p-type electrode (not shown) is formed on the bottom surface of the p-type 1nP substrate 82. In this way, the semiconductor optical switching according to the fourth embodiment is similar to the second embodiment shown in FIG.
In the n+ type 1nP cladding layer 38 of the embodiment, a portion corresponding to the high resistance region 56 formed in the negative half thereof is removed by etching, for example, to form a one-sided ridge-shaped n+ type InP cladding layer 88. On the ridge portion of the n+ type InP cladding layer 88, an n type InGaAs layer is formed.
It has a structure in which a P cap layer 90 is formed.

Next, the operation of the apparatus of the fourth embodiment will be explained.

The operation of the fourth embodiment is similar to that of the second embodiment, by applying a predetermined voltage between the p-type electrode and the n-type electrode, and forming the n+ type InP cladding layer 88 and the n''' type InP cladding layer 88. Ga
When a current is passed in the forward direction through the p-n junction of the double hetero-concave structure consisting of the AsP waveguide layer 86 and the p+ type InP lower cladding layer 84, carriers pass through the ridge portion of the n+ pear-shaped 1nP rad layer 88, Only one half of the n-type 1nGaAsP waveguide 86 is implanted. Therefore, n+ type InP
n-type In which is not located below the ridge of the cladding layer 88
No carriers are injected into the other half of the GaAsP waveguide layer 46.

In this way, carriers are injected into only one half of the n-type 1nGaAsP waveguide layer 86 and confined there, so that the dielectric constant of that part decreases due to the plasma effect, and the refractive index decreases.

Therefore, the n-type InGaAsP waveguide layer 66 is
It is divided into two regions with different refractive indexes. Therefore, the light incident from the waveguide is totally reflected at the boundaries between regions of the n-type InGaAsP waveguide layer 66 having different refractive indexes, that is, at the boundaries where the high refractive index region transitions from the low refractive index region, and the light travels along its path. change.

In this way, the semiconductor optical switch according to the fourth embodiment performs a switching action on incident light, but similarly to the second embodiment, it performs a switching action on incident light from one direction, so-called. It is a one-way switch. The third embodiment also has all of the various effects of the first embodiment described above.

Next, a method for manufacturing a semiconductor front switch according to a first embodiment of the present invention will be sequentially explained using FIG. 10.

As a semiconductor substrate, for example, n++1nP with high carrier concentration
An n+ type InP lower cladding layer 4 having a high carrier concentration is grown on the substrate 2 with lattice matching. And this n+ type I
On the nP lower cladding layer 4, for example, an MBE (molecular beam epitaxial) method is used to grow an n-type InGaAsP epitaxial layer consisting of quaternary elements with a low carrier concentration in a lattice-matched manner. The epitaxial layer is selectively etched into two waveguide layer patterns intersecting each other with a waveguide width W and an intersection angle 2θ to form a ridge-shaped n-type InGaAsP waveguide layer 6 (10th waveguide layer 6). (See figure (a)).

Next, a p++InP cladding layer 8 with a high carrier concentration is formed on the ridge portion of the n-type InGaAsP waveguide layer 6.
is grown with lattice matching. Further, on this p+ type 1nP cladding layer 8, p++InGa with a high carrier concentration is formed.
Grow the AsP carapace layer 10 (FIG. 10(b))
reference).

Next, after depositing a mask material 102 on the entire surface, p++InGaAs is deposited on the intersection region where the two waveguides intersect.
The mask material 102 on the P cap layer 10 is selectively removed leaving only the central portion. For example, while the minimum width of the intersection region is approximately 20 μm, the width of the central portion where the mask material 102 remains is approximately 8 μm. Using the thus patterned mask material 102 as a mask, silicon is diffused. This silicon diffusion is performed at the p+ type opening 0229 0.4 μm above the top surface of the n-type InGaAs P waveguide layer 6.
Make sure it reaches the middle of the 8th layer of 11th layer.

The reason for preventing silicon diffusion from reaching the upper surface of the n'' type 1nGaAsP waveguide layer 6 in this way is to prevent silicon from being diffused into the n-type 1nGaAsP waveguide layer 6 during heat treatment in a later step. This is to do so. In this way, high resistance regions 26 and 28 having relatively high resistance due to the addition of silicon S1 are formed on both sides of the p++InP cladding layer 8 (see FIG. 10(c)).

Next, the p+ type 1n of the intersection region where the two waveguides intersect
A p-type electrode 104 is formed on the GaA3'P cap layer 10. In addition, an n-type electrode 1 is also placed on the bottom surface of the n+ type 1nP substrate 2.
06 (see FIG. 10(d)).

Finally, the end face is folded to a length of 5 mm, and a waveguide chip is cut out. In this way, the bidirectional semiconductor optical switch according to the first embodiment is manufactured.

In addition, in the above manufacturing method, the ridge type n''' type I
After forming the n GaAsP waveguide layer 6, this n
A p+pear shape 1 is formed on the ridge part of the nGaAsP waveguide layer 6.
An nP rad layer 8 and a p-type InGaAs P layer cap layer 10 are sequentially formed, but an n-type InGaAs P epitaxial layer and a p+ pear-type 1nP epitaxial layer are formed on the n+-type 1nP lower cladding layer 4. , and a p+ type InGaAsP epitaxial layer, selective etching is performed on each of these layers to form a ridge-shaped n-' type 1nGaAsP waveguide layer 6 and this n-type InGaAsP waveguide layer 6.
A p+ type InP clad layer 8 on the ridge portion of the GaA/P waveguide layer 6 and a p+ type InGaAs P layer cap layer 10 on the p+ pear-shaped 1nP rad layer 8 are formed at once. Good too. Furthermore, although silicon is diffused into both sides of the p+ type InP cladding layer 8 to form the high resistance regions 26 and 28, ion implantation of protons (H+), for example, may be used instead of silicon diffusion.

Further, on the n+ type InP substrate 2, an n+ type 1nP dome cladding layer 4, a low type In Ga As P waveguide layer 6, and a p
+ pear-shaped 1nP rad layer 8, and p+ type In Ga A
s P layer cap layer 10 is formed respectively, or n-type InGaAsP is formed instead of such a combination.
The conductivity types of the substrates and each layer sandwiching the waveguide layer 6 are exchanged, and a p+ type 1nP lower cladding layer, an n-type InGaAsP waveguide layer 6, and an n+ pear-type 1 are formed on the p+ type InP substrate.
nP rad layer and n+ type! It may also be formed in combination with an nGaAsP cap layer. However, in this case, the impurity implanted to form a high resistance region in a part of the n'' type 1nP cladding layer is, for example, zinc (Zn
), beryllium (Be), or protons. In either case, the conductivity type of the n-type 1nGaAsP waveguide layer 6 is not limited to the n-type.
For example, p-type GaAs or i-type Ga with low carrier concentration.
It may also be As. However, since holes absorb more light than electrons, n-type is more desirable than p-type.

Furthermore, in patterning the mask material 102,
Instead of selectively removing the mask material 102 on the p+ type 1n GaAs P cab 1 layer 10 in the intersection area where two waveguides intersect as described above, leaving only the central part, the p+ type in the intersection area is removed. One half of the masking material 102 on the InGaAsP cab 1 layer 10 is left and only the other half is selectively removed, and silicon is diffused using the thus patterned masking material 102 as a mask to form a p+p layer. By forming a high resistance region in one half of the type 1nP rad layer 8, a structure similar to that of the second embodiment can be obtained, and a unidirectional semiconductor optical switch can be manufactured.

Further, using the mask material 102 patterned so as to selectively remove the mask material 102 on the p+ type InGaAsP cap layer 10 in the intersection region leaving only the central portion as a mask, etching treatment is performed instead of silicon diffusion. A portion corresponding to a high resistance region formed by silicon diffusion may be removed by etching. As a result, a structure similar to that of the third embodiment described above is formed, and a bidirectional semiconductor optical switch can be manufactured.

Similarly, p+ type InGa A in the intersection region
Using the mask material 102 patterned so as to leave one half of the mask material 102 on the P cab 1 layer 10 and selectively remove the other half as a mask, etching treatment is performed instead of silicon diffusion. Alternatively, a portion corresponding to a high resistance region formed by silicon diffusion may be removed by etching. As a result, a structure similar to that of the fourth embodiment described above is formed, and a unidirectional semiconductor optical switch can be manufactured.

〔Effect of the invention〕

As described above in detail, according to the present invention, the waveguide layer is sandwiched from above and below between the semiconductor substrate of the first conductivity type and the cladding layer of the second conductivity type, which has a forbidden band larger than the forbidden band of the waveguide layer. Due to the double heterostructure, a low refraction region is generated in a part of the waveguide layer due to the plasma effect, and the incident light is totally reflected at the boundary without depending on its wavelength. Furthermore, since the entire waveguide layer is a low carrier layer sandwiched between a semiconductor substrate with a high carrier concentration and a cladding layer, loss is reduced. by this,
Since optical switching is performed with a high extinction ratio and reduced transmission loss, it has excellent low loss characteristics, can be driven at low voltage, and can perform optical switching over a wide range of wavelengths. .

Furthermore, according to the present invention 1'7) TA method, the above-mentioned 1'-conductor tip switch can be manufactured with a high yield by using a simple L combination.

[Brief explanation of the drawing]

Fig. 1: 4 is a perspective view showing a semiconductor optical switch according to the first embodiment of the present invention. Fig. 2 is a plan view of the semiconductor optical switch according to the first embodiment of the present invention. , FIGS. 3 and 4 are respectively according to the first embodiment of the present invention.
, a sectional view of the conductor tip switch, FIG. 6 and 7 are respectively cross-sectional views of a semiconductor optical switch according to a second embodiment of the present invention, and FIGS. 8 and 9 are respectively cross-sectional views of a semiconductor optical switch according to a second embodiment of the present invention. FIG. 10, which is a sectional view of the semiconductor optical switch according to the third and fourth embodiments, is a process diagram showing a method of manufacturing the semiconductor optical switch according to the first embodiment of the present invention. 2.62-n+ type 1nP substrate, 464...n'' type InP lower cladding layer, 6 36,
66, 86---n-type InGaAsP waveguide layer, 8.68-p+ type InP cladding layer, 10.7O-=p+ type 1nGaAsP core layer, 1
2.14.42□44...Waveguide, 16.20,46
,50. ...Incidence boat, 18.22, 48.5
2... Launch boat, 24.54.72, 9.2...
Switch section, 26.28.56...High resistance region, 32.82-p+ type InP substrate, 34.84...p+ type 1nP lower cladding layer, 38.
88=-n+ pear-shaped 1nP rad layer, 40 90...n+
Type InGa ASP cap layer, 102...mask material, 104...n-type electrode, 106...n-type electrode. Figure 3 Figure 4 Figure 2

Claims (1)

[Scope of Claims] 1. A semiconductor substrate of a first conductivity type having a first electrode formed on one surface; a ridge-shaped waveguide layer having a low concentration; a cladding layer of a second conductivity type formed on the ridge portion of the waveguide layer, having a forbidden band larger than that of the waveguide layer and having a high carrier concentration; a high resistance region formed in a part of the layer; and a second electrode formed on the cladding layer; and a voltage applied between the first electrode and the second electrode. A semiconductor optical switch characterized in that carriers are injected into a part of the waveguide layer through a relatively low resistance region other than the high resistance region in the cladding layer. 2. The semiconductor optical switch according to claim 1, wherein the high resistance region is formed on both sides of the cladding layer. 3. The semiconductor optical switch according to claim 1, wherein the high resistance region is formed in one half of the cladding layer. 4. A first conductivity type semiconductor substrate with a first electrode formed on one surface, and a ridge-shaped semiconductor substrate formed on the other surface of the semiconductor substrate, with a forbidden band smaller than that of the semiconductor substrate and a lower carrier concentration. a waveguide layer; a ridge-shaped second conductivity type cladding layer formed on the ridge portion of the waveguide layer and having a forbidden band larger than that of the waveguide layer and a higher carrier concentration; and a ridge of the cladding layer. a second electrode formed on the cladding layer, the ridge portion of the cladding layer being formed in the center of the cladding layer, and an electric voltage applied between the first electrode and the second electrode. A semiconductor optical switch characterized in that carriers are injected into a central portion of the waveguide layer through a ridge portion of the cladding layer by a voltage applied to the semiconductor optical switch. 5. A ridge portion of the cladding layer is formed in one half of the cladding layer, and a voltage applied between the first electrode and the second electrode causes the ridge portion of the cladding layer to pass through the ridge portion. 5. The semiconductor optical switch according to claim 4, wherein carriers are injected into one half of the waveguide layer. 6. A ridge-shaped waveguide layer having a forbidden band smaller than that of the semiconductor substrate and having a lower carrier concentration on a semiconductor substrate of a first conductivity type, and a forbidden band above the ridge portion of the waveguide layer; The second one is larger than that of the second one and has a higher carrier concentration.
a first step of forming a conductive type cladding layer; a second step of forming a high resistance region in a part of the cladding layer; forming a first electrode on the cladding layer; A method for manufacturing a semiconductor optical switch, comprising a third step of forming a second electrode on the bottom surface of the substrate. 7. The method of manufacturing a semiconductor optical switch according to claim 6, wherein the high resistance region is formed on both sides of the cladding layer. 8. The method of manufacturing a semiconductor optical switch according to claim 6, wherein the high resistance region is formed in one half of the cladding layer. 9. A ridge-shaped waveguide layer having a forbidden band smaller than that of the semiconductor substrate and having a lower carrier concentration on a semiconductor substrate of a first conductivity type, and a forbidden band above the ridge portion of the waveguide layer; a first step of forming a ridge-shaped second conductivity type cladding layer that is larger than that of the semiconductor substrate and has a higher carrier concentration; forming a first electrode on the ridge portion of the cladding layer; A method for manufacturing a semiconductor optical switch, comprising: a second step of forming a second electrode on the bottom surface. 10. The method of manufacturing a semiconductor optical switch according to claim 9, wherein the ridge portion of the cladding layer has a one-sided ridge shape. 11. The method of manufacturing a semiconductor optical switch according to claim 9, wherein the ridge portion of the cladding layer is formed in a central portion of the cladding layer.