JPH02312097A - Sense amplifier driving system - Google Patents

Abstract

PURPOSE:To improve the sensitivity by operating the N channel type flip-flop and P channel type flip-flop of a sense amplifier at the same time and canceling bit-line capacity imbalance. CONSTITUTION:A signal is read out of a memory cell to a bit line BL0 or BL1 which is precharged to an intermediate level between a source voltage level and a ground level. When the signal is amplified by the sense amplifier, the sense amplifier P channel type transistor(TR) common source and sense amplifier N channel type TR common source SAN of a sense amplifier flip-flop circuit are operated almost at the same time. Consequently, the improvement quantity of the sense sensitivity as a result of a decrease in the additional capacity of the sense amplifier because of a latch type sense system compensates the decrease quantity of the sensitivity due to a coupling noise to realize high- sensitivity data sensing operation.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention provides a driving method for a sense amplifier in an LSI memory. (Prior Art) FIG. This shows a sense circuit in which memory cells are modeled using capacitors.

In the figure, the transistors forming the dynamic flip-flop are Ql, Q2. , Ql, Q2 conductance constants and threshold voltages are 131, 132 ., respectively. VTHI
.

VTH2 and bit line capacitance are expressed as CI and C2. The table hole representing the sensitivity ΔVSA of this sense amplifier is ΔV
SA=-v'? Saeni ■ (Δ13/D+ΔC/C) +
2ΔVTH, (1). Here, α,
are constants, conductance constant p, bit line capacitance C1 threshold voltage VTR and their unbalance component Δ
p, ΔC2ΔVTH satisfy the following: 131 = f3 −Δp 132 = 1 + Δp C1= C+ΔC C2: C−ΔC VTH1= VTH+ΔVTH VTH2= VTH−ΔVTH. Regarding the derivation of the sense amplifier sensitivity formula (1), see, for example, IEICE Transactions, 1978, 6
This is described in detail in the paper "Analysis of Sense Amplifier Sensitivity of Dynamic MO8RAM" on pages 399 to 401 of Monthly Issue, Vol. J61-C, No. 6.

As can be seen from equation (1), sensing sensitivity can be improved by reducing the bit line capacitance C during data sensing, and there is a sensing method called latch type sensing to achieve this. 1989 International Solid State Circuits Conference (Inte
rnational 5olid-8tate C1r
Digest of Technical Conference (15SCC)
Papers) A 55ns 16Mb DRAM published on pages 246 to 247
Based on J, we will discuss the latch type sensing method.

FIG. 3 is an example of a circuit in which the latch type sensing method is applied to a dynamic random access memory (DRAM). In FIG. 3, the memory cell is a normal one-transistor, one-capacitor type memory cell, in which a switching transistor QS is interposed between a charge storage capacitor C8 and bit lines BLO and BLI. When reading data from memory cells (in the figure, n memory cells are attached to one bit line), word lines WLOI to WLOI connected to the gate of QS are used.
By selecting one of LOn, WLII to Wlln and raising it to high level, QS is made conductive, and the charge stored in C8 is read out to the bit line. Thereafter, the sense amplifier circuit amplifies the signal read from the memory cell. In the figure, the sense amplifier includes P-channel transistors PL, P2, and N-channel transistor Nl.
, N2 0MO8 type flip-flops. Here, the common sources of the P-channel type and N-channel type transistors of the sense amplifier are SAP and SAN, respectively.
shall be. Further, the common drains of the P-channel type and N-channel type of the sense amplifier are SAO and SAI, and the bit lines are BLO and BLI. In a normal sense type circuit, SAO, SAI and BLO, BLI are connected directly, but when using a latch type sense type circuit, SA
O.

A feature of the circuit is that transfer gates QTGO and QTGI controlled by a signal TG are inserted between SAI and BLO and BLI. Although an N-channel transistor is used as the transfer gate in FIG. 3, a P-channel transistor may also be used. Capacitors CBLO, CBLI, CSAO, and CSAI represent parasitic capacitances of nodes BLO, BLI, SAO, and SAI, respectively.

FIG. 4 shows a latch sense clock timing chart when a memory cell connected to the word line WLOI is selected. Using this diagram, a data read operation using the latch type sensing method when a low level is stored in a memory cell will be described.

In Figure 4, GND is ground level (low level), VCC
represents the power supply voltage level (high level). Vpre is a certain intermediate potential that satisfies GND≦Vpre≦vCC.

First, during standby, nodes BLO, BLI, SAO,
S.A.I.

SAP and SAN are precharged to Vpre. Especially in recent DRAMs, usually Vpre = V C
Cl2 is often used. In addition, TG is kept at a high level, and BLO, 5AO1BLI, and SAI are kept conductive. All word lines are at low level and the switching transistors of the memory cells remain closed.

To read data from the selected memory cell, W
The LOI is raised to high level (the other word lines remain at low level), the switching transistor QS of the selected memory cell is made conductive, and the BLO and SAO data are read. Specifically, since the selected memory cell has a low level, when QS becomes conductive, the potentials of BLO and SAO drop slightly from Vpre. The potential of this drop is Δ
When expressed as V, the potential of BLO and SAO is (Vpre−Δ
V). This ΔV will be referred to as a read voltage or a read signal from the memory cell. On the other hand, B.L.I.
, SAI remains at the Vpre level, which becomes the reference voltage level. The above corresponds to the period (■) in FIG.

Next, lower TG to low level and transfer gate Q.
Make TGO and QTGI non-conductive and connect BL from the sense amplifier.
O, disconnect BLI. This is an operational feature of the latch type sensing method. This corresponds to the period shown in Figure 4 (■).

After that, SAN is lowered to low level, SAP is raised to high level to activate the sense amplifier, and the read voltage ΔV
amplify. In the conventional sense method, the SAN was changed before the SAP. This amplification operation ultimately results in S
This is performed until AO and SAI reach low and high levels, respectively. This corresponds to the period shown in Figure 4 (■).

By the way, the bit line BLO is separated by TG.

Data rewriting to BLI is performed at the reset of the read cycle.

By performing the sense amplification operation according to the procedure described above, the bit line capacitance during sensing is reduced and sensitivity is improved.

(Problem to be solved by the invention) However, in the conventional latch type sensing method,
There is a problem in that the readout signal Δ■ becomes effectively small due to the coupling noise of QTGO and QTGI when the TG is made non-conductive. In other words, Q
Insertion of TGO and QTGI actually decreased the sense sensitivity.

Let's examine the reduction in sensitivity due to the coupling noise in more detail. To make it easier to understand the operation at this time,
FIG. 5 shows a sense amplifier circuit consisting only of N-channel transistors. FIG. 5 is the same as FIG. 3 except that there is no P-channel flip-flop. Here, the worst case of capacity imbalance when reading SAO low is as follows: CBLO: CBL+ΔCBL CBLI =: CBL-ΔCBL C8AO= C8A+ΔC8A , , , , , (2
)C8AI=C3A-ΔC8A. In fact, since there are variations in LSI manufacturing, an unbalance of 5% to 10% at most must be taken into consideration.

At this time, assume that the potential of SAO is ΔvO1 and the potential of SAI is decreased by Δv1 due to coupling noise of TG.

Under the above condition (2), since CSAO>CSAI, there is a relationship of ΔvO<Δv1.

Therefore, when calculating the effective readout signal ΔVeff read out to the sense amplifier (ΔV is the readout signal when there is no coupling noise), ΔVeff = (Vp
re-ΔVl)-(Vpre-ΔV-ΔVO)=ΔV
−(ΔVI−ΔVO)<ΔV (from AVO<AVI)
In other words, the above equation indicates that the readout signal decreases due to coupling noise.

An object of the present invention is to provide a highly sensitive sensing method that suppresses the influence of the coupling noise.

(Means for Solving the Problems) The present invention provides a first differential amplifier circuit in which the drains and gates of first and second P-channel MISFETs are cross-connected, and first and second N-channel MISFETs. a second differential amplifier circuit whose drains and gates are cross-connected, the first and second differential amplifier circuits connected to the first and second P
A sense amplifier connected to each drain of the channel type MISFET and each drain of the first and second N-channel type MISFETs, a bit line connecting a plurality of memory cells, and a P-channel type MISFET of the sense amplifier.
Using a circuit in which a transfer gate made of a MISFET is inserted between the common drain of an N-channel MISFET and the bit line, a memory cell is connected to a bit line precharged to an intermediate level between the power supply voltage level and the ground level. When a signal is read from the memory cell and amplified by the sense amplifier, after a signal voltage appears on the bit line from the memory cell, the transfer gate is made non-conductive, and then the first differential signal of the sense amplifier is This is a sense amplifier driving method characterized by operating an amplifier circuit and a second differential amplifier circuit almost simultaneously to perform signal amplification.

(Function) In the present invention, the P-channel transistor and the N-channel transistor of the sense amplifier flip-flop circuit are activated almost simultaneously, thereby canceling out the imbalance in the load capacitance of the sense circuit. As a result, the amount of improvement in sensing sensitivity due to the reduction in the additional capacitance of the sense amplifier due to the latch-type sensing method compensates for the amount of reduction in sensitivity due to coupling noise, realizing highly sensitive data sensing.

(Example) Next, one embodiment of the present invention will be described using FIG.

FIG. 1 shows an operation clock timing chart when the method of the present invention is used. The circuit may be any type of so-called latch-type sense amplifier circuit in which a transfer gate is provided between the bit line and the sense amplifier, and here we will explain the circuit using the circuit shown in Figure 3 as an example. .

TG is the period marked ■ in the figure when data is read from memory cells.
(The period marked ■ in the figure in which the transfer gate is closed by the i signal is exactly the same as the conventional latch type sense system. The difference between the present invention and the conventional method is that when sense amplification is performed, that is, the SAP during the period marked ■ in the figure , is the timing of SAN change. Specifically, it is important to change SAP and SAN at the same time.

The reason why sense sensitivity is improved by changing SAP and SAN simultaneously will be explained with reference to FIGS. 5 and 6. In contrast to FIG. 5, FIG. 6 shows a flip-flop sense amplifier consisting only of P-channel transistors. Other capacities, etc. are the same as in FIG. 3.

The worst condition for capacitance imbalance when it is assumed that row data is read from the memory cells connected to WLOI is as follows: CBLO: CBL-ΔCBL CBLL = CBL+ΔCBL C8AO= C3A-ΔC8A , , , , , , (3
)C8AI=C8A+ΔC8A It should be noted that the relationship in size between CSAO and OSAI is opposite to the condition in (2). In other words, in the present invention, the worst capacitance imbalance condition (2) for an N-channel flip-flop of the sense amplifier and the worst capacitance imbalance condition (3) for a P-channel flip-flop
) is in an inverse relationship, and by operating both flip-flops simultaneously, the capacity imbalance is canceled out.

Up to this point, the explanation has been made assuming low data reading, but it can be seen that the effects of the present invention can be obtained by similar considerations in the case of high data reading.

(Effects of the Invention) As described above, in the present invention, the N-channel type flip-flop and the P-channel type flip-flop of the sense amplifier are operated simultaneously to cancel the bit line capacitance unbalance. The amount of sensitivity improvement due to the smaller bit line capacitance during sensing is
It is possible to compensate for signal loss due to transfer gate coupling and realize a highly sensitive sensing method. Of course, by increasing the sensitivity of the sense amplifier, the memory operation speed can be further increased.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a clock timing chart during the operation of a sense amplifier showing one embodiment of the present invention, FIG. 2 is a sense system circuit diagram in which the sense amplifier is modeled using an N-channel dynamic flip-flop, and FIG. The figure shows an example of a conventional latch type sense amplifier circuit, Figure 4 is a clock timing chart when driving the conventional sense amplifier circuit of Figure 3, and Figures 5 and 6 each show an N channel. FIG. 3 is a sense system circuit diagram using a P-channel dynamic flip-flop sense amplifier.

In the figure, Q, C2... N-channel transistor constituting a dyno-sized flip-flop, C1°C
2-...Bit line capacitance, 131, 132. V THI
, V TH2・Nf conductance constant and threshold voltage of Janel type transistor, WLOI~WLOn,
WLII~WL1n-...Word line, BLO, BLI...
...Bit line, SAO, SAI...Drain node in sense amplifier, SAP...Sense amplifier N-channel transistor common source, SAN...Sense amplifier N
Channel type transistor common source, TG-...transfer gate control signal, QTGO, QTGI...transfer gate, CBLO, CBLL, CSAO
, CSAI...BLO.

BLI, SAO, SAI parasitic capacitance, QS...Memory cell switch jig transistor, C8...Memory cell charge storage capacity, PO, PL...P channel type transistor that constitutes the sense amplifier, No, Nl... - N-channel transistor that constitutes the sense amplifier.

Figure 1

Claims (1)

[Claims] A first differential amplifier circuit in which the drains and gates of the first and second P-channel MISFETs are cross-connected, and a second differential amplifier circuit in which the drains and gates of the first and second N-channel MISFETs are cross-connected, respectively. a dynamic amplifier circuit, and the first and second differential amplifier circuits are interconnected by each drain of the first and second P-channel type MISFET and each drain of the first and second N-channel type MISFET. a sense amplifier, a bit line connecting a plurality of memory cells, and a transfer gate made of a MISFET inserted between the common drain of a P-channel MISFET and an N-channel MISFET of the sense amplifier and the bit line. When a signal is read from a memory cell to a bit line precharged to an intermediate level between the power supply voltage level and the ground level, and the signal is amplified by the sense amplifier, the signal voltage is applied to the bit line from the memory cell. after the transfer gate has appeared, the transfer gate is rendered non-conductive;
Next, a sense amplifier driving method characterized in that the first differential amplifier circuit and the second differential amplifier circuit of the sense amplifier are operated almost simultaneously to perform signal amplification.