JPH02311013A - Duty correction circuit for clock signal - Google Patents

Abstract

PURPOSE:To obtain a duty correction circuit with a high speed clock signal by providing means of frequency division, delay, storage and synthesis and outputting a clock signal whose duty is corrected. CONSTITUTION:A clock signal whose duty is to be corrected is inputted to a frequency divider means 10 and a delay means 20 and a frequency divider output 11 and a delay output 21 are generated. The output 11 is inputted to a synthesis means 40 and also to a storage means 30 and stored and becomes a storage output 31 with the delay output 21 as the output. The synthesis means 40 executes exclusive OR of the outputs 31 and 11 to generate an output signal 41. The pulse width of the signal 41, that is, the duty depends on the phase difference between the outputs 11 and 31 and on the delay of the delay means 20. Thus, the duty of the signal 41 is corrected to a proper value by optimizing the delay of the delay means 20.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock signal duty correction circuit, and more particularly to a clock signal duty correction circuit used in a logic circuit device.

[Conventional technology]

The configuration of a typical conventional lock signal duty correction circuit is shown in the block diagram of FIG.

In the same figure, clock signal 5 to be subjected to duty correction
1 is made into a differentiated signal 61 by the differentiating circuit 60, and set -
A reset flip-flop (hereinafter referred to as 5-RFP) is set, and the differential signal 61 is input to the delay circuit 70.
A delayed differential signal 71 is created by delaying . Next, the 5-RFF 80 is reset by the delayed differential signal 71, and the 5-RFF
The configuration was such that a duty-corrected clock signal was generated as the output signal 81 of 80.

[Problem to be solved by the invention]

The conventional clock signal duty correction circuit described above is
As shown in FIG. 2, a differentiation circuit is essential, and a strong differentiation signal 61 with an extremely narrow pulse width and high frequency spectrum must be delayed using a delay circuit 70 with a relatively narrow band. There is a limit to how narrow the pulse width can be, and this poses a problem in that it becomes a major hindrance when performing duty correction for a high-speed lock signal.

[Means to solve the problem]

The clock signal duty correction circuit of the present invention includes a frequency dividing means for dividing the frequency of a clock signal to be subjected to duty correction, a delay means for delaying the clock signal, and a frequency division output of the frequency dividing means. A storage means for outputting the delayed output of the delay means, and a synthesis means for performing an exclusive OR operation of the output of the storage means and the frequency division output of the frequency division means, and a duty signal as the output of the synthesis means. It has the function of outputting a corrected clock signal.

〔Example〕

FIG. 1(a) is a block diagram of an embodiment of the present invention, and FIG. 1(b) is a time chart of each signal shown in FIG. 1(a).

In FIGS. 1(a) and 1(b), a clock signal 1 whose duty is to be corrected is input to a frequency dividing means 10 and a delay means 20, and a frequency divided output 11 and a delayed output 21 are created. . The frequency-divided output 11 is input to the synthesis means 40, and is also input to and stored in the storage means 30, and the delayed output 2
1 is output as the memory output 31. Synthesis means 40
performs an exclusive OR operation on both the storage output 31 and the frequency-divided output 11, and generates an output signal 41. Output signal 4
It is obvious that the duty during the pulse of 1 depends on the phase difference between the frequency-divided output 11 and the storage output 31, and it is also obvious that it depends on the amount of delay of the delay means 20. Therefore, by optimizing the delay amount of the delay means 20, the output signal 4
1 can be corrected to an appropriate value.

〔Effect of the invention〕

As described above, the present invention can be realized without using a differentiation circuit which is essential in the prior art, and therefore has the effect of realizing a high-speed lock signal duty correction circuit.

[Brief explanation of drawings]

FIG. 1(a) is a block diagram of an embodiment of the present invention, FIG. 1(b) is a time chart of each signal in FIG. 1(a), and FIG. 2 is a conventional clock signal duty correction circuit. FIG. 1... Clock signal, 10... Frequency division means, 11... Frequency division output, 20... Delay means, 21... Delay Output, 30...Storage means, 31...Storage output, 40...
Synthesizing means, 41... Output signal. Agent Lawyer Susumu Uchihara, 11th Takumi, is asking for a lie? prisoner

Claims (1)

[Claims] Frequency dividing means for dividing the frequency of a clock signal to be duty-corrected, delay means for delaying the clock signal, and storage means for storing the divided output of the frequency dividing means and outputting it as a delayed output of the delay means. and a synthesizing means for performing an exclusive OR operation on the output of the storage means and the frequency-divided output of the frequency dividing means, and outputs a clock signal with a duty corrected as an output of the synthesizing means. Duty correction circuit for clock signal.