JPH02310956A - High-density mounting semiconductor package - Google Patents
High-density mounting semiconductor packageInfo
- Publication number
- JPH02310956A JPH02310956A JP13137489A JP13137489A JPH02310956A JP H02310956 A JPH02310956 A JP H02310956A JP 13137489 A JP13137489 A JP 13137489A JP 13137489 A JP13137489 A JP 13137489A JP H02310956 A JPH02310956 A JP H02310956A
- Authority
- JP
- Japan
- Prior art keywords
- material layer
- conductive material
- chip
- electrode
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 239000004020 conductor Substances 0.000 claims abstract description 89
- 239000000463 material Substances 0.000 claims abstract description 8
- 239000011810 insulating material Substances 0.000 abstract description 21
- 229910000679 solder Inorganic materials 0.000 abstract description 17
- 238000000034 method Methods 0.000 abstract description 6
- 229920005989 resin Polymers 0.000 abstract description 6
- 239000011347 resin Substances 0.000 abstract description 6
- 239000004593 Epoxy Substances 0.000 abstract description 4
- 238000000465 moulding Methods 0.000 abstract description 4
- 239000010408 film Substances 0.000 abstract 1
- 239000010409 thin film Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 103
- 238000004806 packaging method and process Methods 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 235000010575 Pueraria lobata Nutrition 0.000 description 1
- 241000219781 Pueraria montana var. lobata Species 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野゛〕
本発明は半導体パッケージ、特に半導体チップの外表面
に設けられ元電極に、前記電極と外部端子との導通を図
る目的であらかじめ製作された導電材層を電気的に接続
して構成される半導体パッケージにおいて、高密度実装
を達成する多ピン化パッケージに関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to a semiconductor package, in particular, to an original electrode provided on the outer surface of a semiconductor chip. The present invention relates to a multi-pin package that achieves high-density packaging in a semiconductor package configured by electrically connecting conductive material layers.
高密度実装に対応した従来の多ビン化パッケージ構造の
半導体装置は、特開昭５９−９８５４３号公報に記載の
ように、半導体チップの電極と外部端子との導通を図る
リード部を、ポリイミド、ポリアミド、トリアジン或い
はガラスエポキシ系の樹脂フィルム等の絶縁材層で分離
された複数の導電材層、例えば銅フィルム等で構成した
多層構造をとっていた。特に、前記リード各層のうち下
層、すなわちチップ寄りの導電材層は、その上側の絶縁
材層の内端よりも内側で終端し、従って前記リードの内
端は階段状の形状を有し、これら各層の段部とチップの
電極部がワイヤにてボンディングされていた。In a conventional semiconductor device with a multi-bin package structure compatible with high-density packaging, as described in Japanese Patent Laid-Open No. 59-98543, the lead portion for electrical connection between the electrodes of the semiconductor chip and external terminals is made of polyimide, It has a multilayer structure consisting of a plurality of conductive material layers, such as copper films, separated by insulating material layers such as polyamide, triazine, or glass epoxy resin films. In particular, the lower layer of each lead layer, that is, the conductive material layer closer to the chip, terminates inside the inner end of the upper insulating material layer, and therefore the inner end of the lead has a stepped shape. The stepped portions of each layer and the electrode portions of the chip were bonded with wires.
このため上記従来装置ではチップ表面の電極上にリード
部を重ねることはできず、チップを支持する板材（タブ
）の代わりにリード部をチップに貼り合わせた構造の半
導体装置では、チップ表面の１１！極をリード部と重な
らない様に配置するか、或いは電極部をさけてリードを
ひき回す等の配慮が必要であった。しかも、最近、チッ
プ表面の電極配置が信号処理の高速化を支配する重要な
因子であることが知られ、このため、上記制約によりチ
ップ表面の電極を自由に配置できないことが、素子の特
性を確保する上で、特に大きな障害となる可能性がでて
きた。For this reason, in the conventional device described above, it is not possible to overlap the lead portions on the electrodes on the chip surface. ! Care must be taken to arrange the poles so that they do not overlap with the lead parts, or to route the leads around the electrode parts. Furthermore, it has recently become known that the arrangement of electrodes on the chip surface is an important factor governing the speeding up of signal processing, and for this reason, the above constraints prevent the electrodes on the chip surface from being freely arranged, which affects the characteristics of the device. There is now the possibility that this will become a particularly big obstacle in securing this.
また、上記従来装置ではリード接着部以外のチップ表面
に電極を形成するため、一定サイズのチップについてリ
ードの多層化により外部出力ピン数を増しても、これに
対応して同様に無制限にチップ表面の電極数を増すこと
はできなかった。In addition, in the conventional device described above, electrodes are formed on the chip surface other than the lead bonding area, so even if the number of external output pins is increased by multilayering the leads for a certain size chip, the number of external output pins can be increased without limit on the chip surface. It was not possible to increase the number of electrodes.
本発明の目的は、多層リード構造を有する半導体装置に
おいて、上記問題点を解決するため、チップ表面の電極
上にリード部を重ねた構造のパッケージを提供すること
である。SUMMARY OF THE INVENTION An object of the present invention is to provide a package in which a lead portion is stacked on an electrode on a chip surface in order to solve the above problems in a semiconductor device having a multilayer lead structure.
上記目的達成の第１手段としては、多層リードの下層す
なわちチップ表面寄りの導電材層とチップ表面電極をは
んだバンプ等を介してワイヤレスボンディングし、さら
に上層の導電材層と前記下層導電材層との電気的絶縁を
図る目的で前記下層導電材層の上部に存在する絶縁材層
に貫通孔を設け、この貫通孔を通して上層の導電材層と
チップ表面電極を電気的に接続することにより達成され
る。As a first means of achieving the above objective, the lower layer of the multilayer lead, that is, the conductive material layer near the chip surface, and the chip surface electrode are wirelessly bonded via solder bumps or the like, and then the upper conductive material layer and the lower conductive material layer are bonded together. This is achieved by providing a through hole in the insulating material layer existing above the lower conductive material layer for the purpose of electrically insulating the lower conductive material layer, and electrically connecting the upper conductive material layer and the chip surface electrode through the through hole. Ru.
また、上記目的達成の第２手段としては、同様に多層リ
ードの下層導電材層とチップ表面電極とをワイヤレスボ
ンディングし、さらに下層導電材層の上部に絶縁材層を
介して設けられる上層導電材層の内端を前記下層導電材
層の内端より内側すなわちチップ中央寄りに延長し、こ
れをチップ表面電極と電気的に接続することにより達成
される。In addition, as a second means for achieving the above object, the lower conductive material layer of the multilayer lead and the chip surface electrode are similarly bonded wirelessly, and the upper conductive material layer is further provided on top of the lower conductive material layer with an insulating material layer interposed therebetween. This is achieved by extending the inner end of the layer inward from the inner end of the lower conductive material layer, that is, toward the center of the chip, and electrically connecting this to the chip surface electrode.
前記第１手段においては、まず下層すなわちチップ表面
寄りの導電材層がはんだバンプ等を用いてリード下部の
チップ表面電極と電気的に接続される０次に上層の導電
材層は前記下層導電材層との間に存在する絶縁材層に設
けられた貫通孔を通し、リード下部のチップ表面電極と
はんだバンプ等を介して電気的に接続される。この時、
上層の導電材層の接続部とチップ表面Ｉ！極との間に下
層導電材層が存在する場合は、下層導電材層の該当部に
も貫通孔を設ける必要がある。In the first means, first, the lower conductive material layer near the chip surface is electrically connected to the chip surface electrode at the bottom of the lead using solder bumps or the like.The upper conductive material layer is connected to the lower conductive material. It is electrically connected to the chip surface electrode at the bottom of the lead via a solder bump or the like through a through hole provided in an insulating material layer existing between the lead and the lead. At this time,
Connection part of upper conductive material layer and chip surface I! If a lower conductive material layer exists between the electrode and the electrode, it is necessary to provide a through hole in the corresponding portion of the lower conductive material layer as well.
これにより、タブの代わりにリード部をチップに貼り合
わせた多層リード構造の半導体装置において、リード部
をチップ表面の電極上に重ねても、各層の導電材とリー
ド下部のチップ表面電極を電気的に接続することができ
るようになるので、リードパターンにかかわらず、前記
電極チップ表面に自由に配置できるようになる。As a result, in semiconductor devices with a multilayer lead structure in which lead parts are attached to the chip instead of tabs, even if the lead parts are stacked on top of the electrodes on the chip surface, the conductive material in each layer and the chip surface electrodes under the leads can be electrically connected. Therefore, the electrode chip can be freely arranged on the surface of the electrode chip regardless of the lead pattern.
同様に、電極部をさけてリードをひき回す手間も不要と
なる。また、チップ表面のリード接着部にも電極が形成
できるので、同じチップサイズの従来装置に比べてより
多くの外部圧力をとり出すことができるようになる。Similarly, it is no longer necessary to route the lead around the electrode section. Furthermore, since electrodes can be formed on the lead bonding portions on the chip surface, more external pressure can be extracted compared to conventional devices with the same chip size.
前記第２手段においては、まず、同様に、下層の導電材
層がはんだバンプ等を用いてリード下部のチップ表面電
極と電気的に接続される６次に、上層の導電材層は内端
が下層導電材層の内端よりも内側すなわちチップ中央寄
りに延長されているので、この延長部分の下部のチップ
表面に設けられた電極と、はんだバンプ等を用いて電気
的に接続される。In the second means, first, similarly, the lower conductive material layer is electrically connected to the chip surface electrode at the bottom of the lead using solder bumps or the like. Since it is extended inward from the inner end of the lower conductive material layer, that is, closer to the center of the chip, it is electrically connected to an electrode provided on the chip surface below this extended portion using a solder bump or the like.
これにより、タブの代わりにリード部をチップに貼り合
わせた多層リード構造の半導体装置において、リード部
をチップ表面の電極上に重ねても、各層の導電材とリー
ド下部のチップ表面電極を電気的に接続することができ
るようになるので、前記電極をチップ表面に自由に配置
できる。また、チップ表面のリード接着部にも電極が形
成できるので、同じチップサイズの従来装置に比べてよ
り多くの外部出力をとり出すことができるようになる。As a result, in semiconductor devices with a multilayer lead structure in which lead parts are attached to the chip instead of tabs, even if the lead parts are stacked on top of the electrodes on the chip surface, the conductive material in each layer and the chip surface electrodes under the leads can be electrically connected. Since the electrodes can be connected to the chip surface, the electrodes can be freely arranged on the chip surface. Furthermore, since electrodes can be formed on the lead bonding portions on the chip surface, more external output can be extracted compared to conventional devices with the same chip size.
ただし、第２手段では、一本のリード部下部に複数個の
電極が存在する場合は、外部端子寄りの電極から順に、
下層の導電材層と接続する必要がある。However, in the second method, if there are multiple electrodes at the bottom of one lead part, the electrodes are arranged in order from the electrode closest to the external terminal.
It is necessary to connect to the underlying conductive material layer.
実施例について図面を参照して説明する。 Examples will be described with reference to the drawings.
第１図は本発明の高密度実装半導体パッケージの第１実
施例の斜視図、第２図は第１図の半導体パッケージの■
−■断面図である６本装置は、第１図及び第２図に示す
通り１表面に電極１を設けた半導体チップ２に、下層導
電材層３．絶縁材層４及び上層導電材層５の三層から成
る多層リード６を貼り合わせ、これらをエポキシ等のモ
ールド樹脂７で被覆することにより構成される。チップ
２の表面の電極以外の部分には、ペースト材をコーティ
ングする。或いは酵いフィルム材を接着する等により、
絶縁材層８が形成される。ここで。FIG. 1 is a perspective view of a first embodiment of the high-density packaging semiconductor package of the present invention, and FIG. 2 is a perspective view of the semiconductor package of FIG. 1.
6, which is a cross-sectional view of the semiconductor chip 2 shown in FIGS. It is constructed by bonding together multilayer leads 6 consisting of three layers, an insulating material layer 4 and an upper conductive material layer 5, and covering them with a molding resin 7 such as epoxy. A portion of the surface of the chip 2 other than the electrodes is coated with a paste material. Or by gluing fermented film material, etc.
A layer of insulating material 8 is formed. here.
下層導電材層３はチップ表面電極１とはんだ等を介して
電気的に接続され、また、上層導電材層５は、下層導電
材層３との間に貼り合わされた絶縁フィルム９に設けら
れた貫通孔を通してはんだ１０によりチップ表面電極１
と電気的に接続される。The lower conductive material layer 3 is electrically connected to the chip surface electrode 1 via solder or the like, and the upper conductive material layer 5 is provided on an insulating film 9 bonded to the lower conductive material layer 3. Chip surface electrode 1 is connected by solder 10 through the through hole.
electrically connected to.
下層導電材層５とチップ表面電極１の接続部に位置する
下層導電材層３の該当部にも、絶縁フィルム９と同様に
貫通孔が設けられている。一方、多層リード６の外部端
子側端部は各層毎に基板の電極ピッチに対応した段差が
付与されており、各層をはんだ１１により基板側電極に
接続することにより、各出力を分離することができる。Similarly to the insulating film 9, a through hole is provided in the corresponding portion of the lower conductive material layer 3 located at the connection portion between the lower conductive material layer 5 and the chip surface electrode 1. On the other hand, the external terminal side end of the multilayer lead 6 is provided with a step corresponding to the electrode pitch of the board for each layer, and by connecting each layer to the board side electrode with solder 11, each output can be separated. can.
本装置の多層リードは、例えば次の手順により製造され
る。まず、第３図に示す通り、あらかじめチップ表面電
極の位置に対応して貫通孔９ａが設けられた絶縁フィル
ム９に、あらかじめ同様にチップ表面電極位置に対応し
た貫通孔３ａが設けられた下層導電材層３を１両者の貫
通孔９ａ及び３ａが一致するように位置合わせして貼り
合わせ。The multilayer lead of this device is manufactured, for example, by the following procedure. First, as shown in FIG. 3, an insulating film 9 is provided with through holes 9a corresponding to the positions of the chip surface electrodes, and a lower conductive film 9 is provided with through holes 3a corresponding to the positions of the chip surface electrodes. The material layers 3 are aligned and bonded together so that the through holes 9a and 3a of both are aligned.
その後、前記下層導電材層３を外枠３ｂより切断する。Thereafter, the lower conductive material layer 3 is cut from the outer frame 3b.
次に、裏面に絶縁材層４をコーティング、或いは接着し
た上層導電材層５を、その先端部５ａが前記絶縁フィル
ム９の貫通孔９ａをおおうように位置合わせして、この
状態のまま上側から絶縁フィルム９及び絶縁材層４を介
して前記下層導電材層３に貼り合わせ、その後、前記上
層導電材層５を外枠５ｂより切断する。なお、使用する
導電材層が例えば銅箔の様な剛性の低い部材の場合には
このように絶縁フィルム９を介して導電材同志を貼り合
わせることが望ましいが、使用する導電材層が薄板状で
剛性が高い場合には、特に絶縁フィルムを用いずに、絶
縁材層４のみを介して導電材同志を貼り合わせてもよい
。Next, the upper conductive material layer 5 coated or bonded with the insulating material layer 4 on the back side is aligned so that its tip 5a covers the through hole 9a of the insulating film 9, and in this state, it is inserted from above from above. It is attached to the lower conductive material layer 3 via the insulating film 9 and the insulating material layer 4, and then the upper conductive material layer 5 is cut from the outer frame 5b. Note that if the conductive material layer to be used is a member with low rigidity, such as copper foil, it is desirable to bond the conductive materials together through the insulating film 9, but if the conductive material layer to be used is in the form of a thin plate, When the rigidity is high, the conductive materials may be bonded to each other through only the insulating material layer 4 without particularly using an insulating film.
第４図は第１図とは異なる第２実施例である高密度実装
半導体パッケージの斜視図、第５図は第４図の半導体パ
ッケージの■−■断面図である。FIG. 4 is a perspective view of a high-density packaging semiconductor package according to a second embodiment different from that shown in FIG.
本装置は、上層導電材層５の内端が下層導電材層３の内
端よりも内側すなわちチップ中央寄りに配置され、下層
導電材層３に上層導電材層とチップ表面電極を電気的に
接続するための貫通孔が設けられていない点と、上層導
電材層５と下層導電材層３の間に挿入される絶縁フィル
ム９を全リードが共有している点で、第１図に示した実
施例とは異なる構造であるが、その他の点では前記実施
例と同様の構造である。In this device, the inner end of the upper conductive material layer 5 is arranged inside the inner end of the lower conductive material layer 3, that is, closer to the center of the chip, and the upper conductive material layer and the chip surface electrode are electrically connected to the lower conductive material layer 3. The structure shown in FIG. 1 has the following advantages: it does not have a through hole for connection, and all the leads share the insulating film 9 inserted between the upper conductive material layer 5 and the lower conductive material layer 3. Although the structure is different from that of the embodiment described above, the structure is similar to that of the embodiment described above in other respects.
本装置の多層リードは、例えば次の手順により製造され
る。まず、第６図に示す通り、絶縁フィルム９にあらか
じめ、チップ表面電極の位置に対応して貫通孔９ａを設
ける０次に、第７図に示す通り、あらかじめペースト材
をコーティングする或いはフィルム材を接着する等の手
段により裏面に絶縁材層４を形成した上層導電材層５を
、その先端部５ａが前記貫通孔９ａをおおうように位置
合わせして前記絶縁フィルム９に貼りあわせ、その後、
前記上層導電材層５を外枠５ｂから切断する。The multilayer lead of this device is manufactured, for example, by the following procedure. First, as shown in FIG. 6, through holes 9a are formed in the insulating film 9 in advance in correspondence with the positions of the chip surface electrodes.Next, as shown in FIG. 7, a paste material is coated in advance or a film material is applied. The upper conductive material layer 5, on which the insulating material layer 4 is formed on the back surface, is aligned and bonded to the insulating film 9 so that its tip 5a covers the through hole 9a by means such as adhesion, and then,
The upper conductive material layer 5 is cut from the outer frame 5b.
さらに第８図に示す通り、前記絶縁フィルム９及び絶縁
材層４の裏面すなわち上層導電材層５との接着面に対向
した面に、パターン印刷等の手段により下層導電材層３
を形成し、その後、絶縁フィルム９を支持枠９ｂから切
断する。なお、第９図はこのようにして製造された第８
図の多層リードの［−Ｗ断面を表わしている。Furthermore, as shown in FIG. 8, the lower conductive material layer 3 is printed on the back surface of the insulating film 9 and the insulating material layer 4, that is, the surface facing the adhesive surface with the upper conductive material layer 5, by means of pattern printing or the like.
is formed, and then the insulating film 9 is cut from the support frame 9b. In addition, FIG. 9 shows the No. 8 manufactured in this way.
This represents the [-W cross section of the multilayer lead in the figure.
第１０図は第１図及び第４図とは異なる第３実施例であ
る高密度実装半導体パッケージの斜視図、第１１図及び
第１２図はそれぞれ第１０図の半導体パッケージのｘｔ
−ｘｔ断面図及び朋−届所面図である１本装置は、第１
０図、第１１図及び第１２図に示す通り１表面に電極１
を設けた半導体チップ２に多層リード６を接着し、これ
らをエポキシ等のモールド樹脂７により被覆することに
より構成される。多層リード６は、下層導電材層３と上
層導電材層５を絶縁フィルム９を介して貼り合わせた三
層構造である。FIG. 10 is a perspective view of a high-density packaging semiconductor package which is a third embodiment different from FIGS. 1 and 4, and FIGS. 11 and 12 are xt of the semiconductor package of FIG.
-xt sectional view and 1-xt cross-sectional view and 1-xt cross-sectional view.
As shown in Figure 0, Figure 11 and Figure 12, electrode 1 is placed on one surface.
It is constructed by adhering multilayer leads 6 to a semiconductor chip 2 provided with a semiconductor chip 2, and covering these with a molding resin 7 such as epoxy. The multilayer lead 6 has a three-layer structure in which a lower conductive material layer 3 and an upper conductive material layer 5 are bonded together with an insulating film 9 interposed therebetween.
第１２図に示す通り、下層導電材層３とチップ表面電極
１は、はんだバンプ等を介してワイヤレスボンディング
され、一方、第１１図に示す通り、上層導電材層５とチ
ップ表面電極１は、ワイヤ１２を介して電気的に接続さ
れる。ここで、上層導電材層とチップ表面電極との接続
部に位置する絶縁フィルム９には、該当部に前記ワイヤ
１２の径よりも大きい貫通孔９ａがあらかじめ設けられ
ており、ワイヤ１２はこの貫通孔９ａを通してボンディ
ングされる。As shown in FIG. 12, the lower conductive material layer 3 and the chip surface electrode 1 are wirelessly bonded via solder bumps, etc., while as shown in FIG. 11, the upper conductive material layer 5 and the chip surface electrode 1 are Electrically connected via wire 12 . Here, a through hole 9a larger than the diameter of the wire 12 is previously provided in the insulating film 9 located at the connection portion between the upper conductive material layer and the chip surface electrode, and the wire 12 is inserted through this hole. Bonding is performed through the hole 9a.
本装置の多層リードは、例えば次の手順により製造され
る。まず、第１３図に示す通り、あらかじめ片面にパタ
ーン印刷等により下層導電材層３を形成した絶縁フィル
ム９に、チップ表面の電極位置に対応した貫通孔９ａを
設ける０次に、第１４図に示す通り、前記絶縁フィルム
９に、上層導電材層５をその先端部５ａが前記貫通孔９
ａ上に若干突出するように位置合わせして、貼り合わせ
る。さらに、第１５図に示す通り、前記絶縁フィルム９
の外周部を上層導電材層５のピッチに合わせてモールド
樹脂７で被覆される領域までカッティングし、その後、
上層導電材層５を外枠５ｂから切断する。The multilayer lead of this device is manufactured, for example, by the following procedure. First, as shown in FIG. 13, through-holes 9a corresponding to the electrode positions on the chip surface are formed in an insulating film 9 on which a lower conductive material layer 3 has been formed by pattern printing or the like on one side in advance.Next, as shown in FIG. As shown, the upper conductive material layer 5 is attached to the insulating film 9 so that its tip 5a is connected to the through hole 9.
Align it so that it slightly protrudes above a, and paste it together. Furthermore, as shown in FIG. 15, the insulating film 9
The outer periphery of the upper conductive material layer 5 is cut to match the pitch of the upper conductive material layer 5 to the area covered with the mold resin 7, and then,
The upper conductive material layer 5 is cut from the outer frame 5b.
なお、第１図及び第４図の実施例では、下層導電材層３
と上層導電材層５の間に挿入する絶縁材層を絶縁フィル
ム９とは別に形成したが、もちろん、これらの実施例に
おいても、本実施例と同様に絶縁フィルム９をリード形
状に合わせてカッティングする方法を用いて前記絶縁材
層を形成してもよい。Note that in the embodiments shown in FIGS. 1 and 4, the lower conductive material layer 3
The insulating material layer to be inserted between the upper conductive material layer 5 and the upper conductive material layer 5 was formed separately from the insulating film 9, but of course, in these examples, the insulating film 9 was cut to fit the lead shape as in this example. The insulating material layer may be formed using a method.
第１６図は更に別の第４実施例の斜視図、第１７図は第
１６図の半導体パッケージのＸ■−Ｘ■断面図である０
本装置は、表面に電極１を設けた半導体チップ２に多層
リード６を接着し、これらをエポキシ等のモールド樹脂
７で被覆することにより構成される。多層リード６は絶
縁材層４を介して下層導電材層３と上層導電材層５を貼
り合わせた三層構造であり、上層導電材層５の内端すな
わちチップ中央寄り端部は、絶縁材層４及び下層導電材
層３の内端よりも内側すなわちチップ中央寄りに延長さ
れている。FIG. 16 is a perspective view of yet another fourth embodiment, and FIG. 17 is a cross-sectional view of the semiconductor package shown in FIG.
This device is constructed by bonding multilayer leads 6 to a semiconductor chip 2 having electrodes 1 on its surface, and covering these with a molding resin 7 such as epoxy. The multilayer lead 6 has a three-layer structure in which a lower conductive material layer 3 and an upper conductive material layer 5 are bonded together with an insulating material layer 4 interposed therebetween. It extends inward from the inner ends of the layer 4 and the lower conductive material layer 3, that is, closer to the center of the chip.
ここで、下層導電材層３ははんだバンプ１０によりチッ
プ表面電極１と電気的に接続され、上層導電材層５は内
側に延長された前記内端部において、チップ表面電極１
とはんだバンプ１０により電気的に接続される。一方、
多層リード６の外部出力端′子側端部は、導電材層毎に
基板の電極ピッチに対応した段差が付与され、上層導電
材）ｔ４５を下層導電材層３より外側に延長した構造に
なっている。このようにして各導電材層をはんだ１１に
より基板側配線部に接続することにより、チップからの
出力を分離することができろ。Here, the lower conductive material layer 3 is electrically connected to the chip surface electrode 1 by solder bumps 10, and the upper conductive material layer 5 is connected to the chip surface electrode 1 at the inner end portion extending inward.
and are electrically connected by solder bumps 10. on the other hand,
The external output terminal side end of the multilayer lead 6 is provided with a step corresponding to the electrode pitch of the substrate for each conductive material layer, and has a structure in which the upper conductive material t45 is extended outward from the lower conductive material layer 3. ing. In this way, by connecting each conductive material layer to the board-side wiring section with the solder 11, it is possible to separate the outputs from the chip.
なお、チップ表面の電極以外の部分には、リードとの絶
縁を図る目的で絶縁材層８が形成されているが、エポキ
シ等の樹脂材或いは低融点ガラス等から成る絶縁性の接
着剤を用いてリードをチップに接着する場合は、この接
着材層を前記絶縁材層としてもよい。Note that an insulating material layer 8 is formed on the surface of the chip other than the electrodes for the purpose of insulating it from the leads. In the case where the leads are bonded to the chip by bonding the leads to the chip, this adhesive layer may be used as the insulating layer.
本装置の多層リードは１例えば絶縁フィルムの上面及び
下面にそれぞれ寸法の異なる二枚の銅箔を接着し、これ
をリード形状にカッティングすることにより製造される
。The multilayer lead of this device is manufactured by, for example, adhering two pieces of copper foil of different sizes to the upper and lower surfaces of an insulating film, and cutting these into a lead shape.
ところで１以上で説明した４種の実施例はいずれもリー
ド部が３層構造を有する場合であるが。Incidentally, all of the four embodiments described above are cases in which the lead portion has a three-layer structure.
リード部が４層以上の多層構造を有する場合にも。Even when the lead part has a multilayer structure of four or more layers.
同様に、本発明を適用することができる。Similarly, the invention can be applied.
本発明によれば、多層リードをチップ表面上に貼り合わ
せた構造の半導体装置において、前記リードをチップ表
面電極上に重ねても、リードの各導電材層とチップ表面
電極を自由に電気的に接続することができる。従って、
チップ表面に自由に電極を配置することができ、信号処
理の高速化を図ることができる。又、電極をさけてリー
ドをひき回す余分な手間を省き、費用を節約することが
できる。さらに、チップ表面のリード接着領域にも電極
を形成できるので、同じチップサイズの従来装置よりも
多数の出力をとり出すことができ。According to the present invention, in a semiconductor device having a structure in which multilayer leads are bonded on the chip surface, even if the leads are stacked on the chip surface electrode, each conductive material layer of the lead and the chip surface electrode can be freely electrically connected. Can be connected. Therefore,
Electrodes can be freely arranged on the chip surface, making it possible to speed up signal processing. Further, it is possible to save costs by eliminating the extra effort of routing the leads around the electrodes. Furthermore, since electrodes can be formed in the lead bonding area on the chip surface, it is possible to extract more output than conventional devices with the same chip size.
高機能化、高密度実装化を達成することができる。High functionality and high density packaging can be achieved.
第１図は本発明の第１実施例である高密度実装半導体パ
ッケージの斜視図、第２図は第１１ｉ１の■−ｎ断面図
、第３図は第１図の多層リード部の組立て図である。第
４図は本発明の第２実施例である高密度実装半導体パッ
ケージの斜視図、第５図は第４図の■−■断面図、第６
図、第７図、第８図は夫々第４図の多層リード部の組立
て図、第９図は第８図のＷ−ＩＸ断面図である。第１０
図は本発明の第３実施例である高密度実装半導体パッケ
ージの斜視図、第１１図及び第１２図は夫々第１０図の
ＸＩ−Ｘ［及び店−１断面図、第１３図、第１４図、第
１５図は夫々第１０図の多層リード部の組立て図である
。第１６図は本発明の第４実施例である高密度実装半導
体パッケージの斜視図、第１７図は第１６図のＸ■−Ｘ
■断面図である。
１・・・電極、２・・・半導体チップ、３・・・下層導
電材層。
４・・・絶縁材層、５・・・上層導電材層、６・・・多
層リード、７・・・モールド樹脂、８・・・絶縁材層、
９・・・絶縁フィルム、１０・・・はんだバンプ、１１
・・・はんだ、１２・・・ワイヤ、３ａ・・・貫通孔、
３ｂ・・・外枠、５ａ・・・上層導電材層先端部、５ｂ
・・・外枠、９ａ・・・貫通葛 １ 回
５」暮！］
第 ２ 回
モールに抽力ｉｉ７ Ｑ棄邑殊フイＩＬ
ム第３図
ｂ
第 Ｌ 図
丁
３５ 因
第 ６ 口
第 ′７ 図
不 ３ 図
築 ９ 図
箒 １０ 図
更 １１ 図
蔓 １ｚ 図
第 １３ 図
第 １４ 園
％ １５ Ｌ？コ
第 １６ 図
工［
第 １７ 図FIG. 1 is a perspective view of a high-density packaging semiconductor package according to the first embodiment of the present invention, FIG. 2 is a sectional view taken along the line ■-n of FIG. 11i1, and FIG. 3 is an assembled view of the multilayer lead portion of FIG. be. FIG. 4 is a perspective view of a high-density packaging semiconductor package according to a second embodiment of the present invention, FIG. 5 is a sectional view taken along the line ■-■ in FIG.
7 and 8 are assembled views of the multilayer lead portion shown in FIG. 4, and FIG. 9 is a sectional view taken along the line W-IX in FIG. 8. 10th
The figure is a perspective view of a high-density packaging semiconductor package according to a third embodiment of the present invention, and FIGS. 11 and 12 are cross-sectional views taken along 15 are assembled views of the multilayer lead portion of FIG. 10, respectively. FIG. 16 is a perspective view of a high-density packaging semiconductor package that is a fourth embodiment of the present invention, and FIG. 17 is a
■It is a sectional view. DESCRIPTION OF SYMBOLS 1... Electrode, 2... Semiconductor chip, 3... Lower conductive material layer. 4... Insulating material layer, 5... Upper conductive material layer, 6... Multilayer lead, 7... Mold resin, 8... Insulating material layer,
9... Insulating film, 10... Solder bump, 11
...Solder, 12...Wire, 3a...Through hole,
3b...Outer frame, 5a...Top portion of upper conductive material layer, 5b
...outer frame, 9a...penetrating kudzu 1 time 5'' night! ] 2nd maul ii7 Q Abandoned Jushui IL
Figure 3b Figure L Figure 35 Cause 6 Mouth '7 Figure not 3 Zuzuki 9 Zuhoki 10 Figure Sara 11 Figure vine 1z Figure 13 Figure 14 Garden% 15 L? Fig. 16 Fig. 17
Claims (1)
、前記電極（１）と外部端子を電気的に接続するためあ
らかじめ製作された少なくとも２層以上の導電材層（５
、３）より構成される半導体パッケージにおいて、一方
の前記導電材層（５）が少なくとも１ケ所以上で前記電
極（１）と電気的に接続され、かつ当該接続部が一方の
前記導電材層（５）と前記チップ（２）との間に存在す
る少なくとも一層以上の他方の導電材層（３）と一方の
前記導電材層（５）とを電気的に絶縁する部材（９）に
より囲まれたことを特徴とする半導体パッケージ。 ２、外表面に電極（１）を設けた半導体チップ（２）と
、前記電極（１）と外部端子を電気的に接続するためあ
らかじめ製作された少なくとも２層以上の導電材層（５
、３）より構成される半導体パッケージにおいて、前記
半導体チップ表面寄りの少なくとも１層以上の前記導電
材層（３）の内端が上部の前記導電材層（５）の内端よ
りも前記半導体チップ（２）の周辺寄りに位置すること
を特徴とする半導体パッケージ。[Claims] 1. A semiconductor chip (2) provided with an electrode (1) on its outer surface, and at least two or more conductive layers prepared in advance to electrically connect the electrode (1) to an external terminal. Material layer (5
, 3), one of the conductive material layers (5) is electrically connected to the electrode (1) at at least one location, and the connection portion is connected to one of the conductive material layers (5). 5) and the chip (2), surrounded by a member (9) that electrically insulates the other conductive material layer (3) and one of the conductive material layers (5). A semiconductor package characterized by: 2. A semiconductor chip (2) provided with an electrode (1) on its outer surface, and at least two or more conductive material layers (5) prepared in advance to electrically connect the electrode (1) and an external terminal.
, 3), in which the inner end of at least one conductive material layer (3) closer to the surface of the semiconductor chip is closer to the inner end of the upper conductive material layer (5) than the inner end of the upper conductive material layer (5). (2) A semiconductor package characterized by being located near the periphery.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13137489A JPH02310956A (en) | 1989-05-26 | 1989-05-26 | High-density mounting semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13137489A JPH02310956A (en) | 1989-05-26 | 1989-05-26 | High-density mounting semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02310956A true JPH02310956A (en) | 1990-12-26 |
Family
ID=15056448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13137489A Pending JPH02310956A (en) | 1989-05-26 | 1989-05-26 | High-density mounting semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02310956A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04278548A (en) * | 1991-03-07 | 1992-10-05 | Nec Corp | Resin sealed semiconductor device |
| JPH05136202A (en) * | 1991-05-11 | 1993-06-01 | Goldstar Electron Co Ltd | Semiconductor package and manufacture thereof |
| US5304738A (en) * | 1991-06-28 | 1994-04-19 | Vlsi Technology, Inc. | System for protecting leads of a semiconductor chip package during testing, burn-in and handling |
| DE4429004A1 (en) * | 1994-08-16 | 1995-06-14 | Siemens Nixdorf Inf Syst | Support spider for integrated circuit chip terminals |
| DE4430050A1 (en) * | 1994-08-24 | 1996-02-29 | Siemens Ag | Lead frame for LOC assembly in inner lead region |
| US5598030A (en) * | 1992-05-21 | 1997-01-28 | Kabushiki Kaisha Toshiba | Semiconductor device having multilevel tab leads |
| KR100243376B1 (en) * | 1997-04-28 | 2000-02-01 | 유무성 | Semiconductor package &manufacturing method thereof |
| US6774466B1 (en) * | 1999-01-28 | 2004-08-10 | Renesas Technology Corp. | Semiconductor device |
| US6909166B2 (en) * | 2001-09-21 | 2005-06-21 | Stmicroelectronics S.R.L. | Leads of a no-lead type package of a semiconductor device |
| JP2010145137A (en) * | 2008-12-16 | 2010-07-01 | Epson Toyocom Corp | Sensor device |
| US8544323B2 (en) | 2008-12-16 | 2013-10-01 | Seiko Epson Corporation | Sensor device |
| JP2014112104A (en) * | 2014-02-21 | 2014-06-19 | Seiko Epson Corp | Sensor device |
-
1989
- 1989-05-26 JP JP13137489A patent/JPH02310956A/en active Pending
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04278548A (en) * | 1991-03-07 | 1992-10-05 | Nec Corp | Resin sealed semiconductor device |
| JPH05136202A (en) * | 1991-05-11 | 1993-06-01 | Goldstar Electron Co Ltd | Semiconductor package and manufacture thereof |
| US5304738A (en) * | 1991-06-28 | 1994-04-19 | Vlsi Technology, Inc. | System for protecting leads of a semiconductor chip package during testing, burn-in and handling |
| US5598030A (en) * | 1992-05-21 | 1997-01-28 | Kabushiki Kaisha Toshiba | Semiconductor device having multilevel tab leads |
| DE4429004A1 (en) * | 1994-08-16 | 1995-06-14 | Siemens Nixdorf Inf Syst | Support spider for integrated circuit chip terminals |
| DE4430050A1 (en) * | 1994-08-24 | 1996-02-29 | Siemens Ag | Lead frame for LOC assembly in inner lead region |
| KR100243376B1 (en) * | 1997-04-28 | 2000-02-01 | 유무성 | Semiconductor package &manufacturing method thereof |
| US7342267B2 (en) | 1999-01-28 | 2008-03-11 | Renesas Technology Corp. | MOSFET package |
| US7985991B2 (en) | 1999-01-28 | 2011-07-26 | Renesas Electronics Corporation | MOSFET package |
| US7332757B2 (en) | 1999-01-28 | 2008-02-19 | Renesas Technology Corp. | MOSFET package |
| US6774466B1 (en) * | 1999-01-28 | 2004-08-10 | Renesas Technology Corp. | Semiconductor device |
| US7394146B2 (en) | 1999-01-28 | 2008-07-01 | Renesas Tehcnology Corp. | MOSFET package |
| US7400002B2 (en) | 1999-01-28 | 2008-07-15 | Renesas Technology Corp. | MOSFET package |
| US8816411B2 (en) | 1999-01-28 | 2014-08-26 | Renesas Electronics Corporation | Mosfet package |
| US8455986B2 (en) | 1999-01-28 | 2013-06-04 | Renesas Electronics Corporation | Mosfet package |
| US8183607B2 (en) | 1999-01-28 | 2012-05-22 | Renesas Electronics Corporation | Semiconductor device |
| US6909166B2 (en) * | 2001-09-21 | 2005-06-21 | Stmicroelectronics S.R.L. | Leads of a no-lead type package of a semiconductor device |
| US8544323B2 (en) | 2008-12-16 | 2013-10-01 | Seiko Epson Corporation | Sensor device |
| US8701485B2 (en) | 2008-12-16 | 2014-04-22 | Seiko Epson Corporation | Sensor device |
| JP2010145137A (en) * | 2008-12-16 | 2010-07-01 | Epson Toyocom Corp | Sensor device |
| JP2014112104A (en) * | 2014-02-21 | 2014-06-19 | Seiko Epson Corp | Sensor device |
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