JPH02301315A - Automatic frequency control circuit - Google Patents

Abstract

PURPOSE:To evade complicated adjustment by controlling an oscillated frequency of an oscillation means based on the count of an intermediate frequency being a digital quantity. CONSTITUTION:A 2nd intermediate frequency signal SlF2 outputted from a frequency converter 2 is fed to an FM demodulator 6 via a cascade connection circuit comprising a band pass filter 4 and a distributer 14 and outputted. Moreover, the 2nd intermediate frequency signal SlF2 distributed by the distributer 14 is fed to a counter 16 via a connector switch 15 and a count K from the counter 16 is fed to a computer 12. When a 1st intermediate frequency signal SlF1 reaches a nonmodulation period and a key pulse signal reaches a high level, the connector switch 15 is turned on and the 2nd intermediate frequency signal SlF2 is fed to the counter 16, in which the frequency is counted. The count K is a digital quantity in general and the oscillated frequency of the oscillation means 13 is controlled based on the digital quantity. Thus, a problem of complicated adjustment or the like different from the analog system is evaded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an automatic frequency control circuit (hereinafter referred to as rAFC circuit) suitable for application to, for example, a BS tuner.

[Prior art] The AFC circuit used in FM receivers, etc., has an average value type AF that controls based on the average value of the entire period of the input signal.
There are C circuits and keyed AFC circuits that are controlled based on a reference signal for a partial period.

Keyed AFC circuits include those that use pure analog circuits, such as sample-and-hold circuits (
(See Japanese Unexamined Patent Publication No. 133450/1983, etc.). FIG. 3 shows an example.

In the figure, a first intermediate frequency signal SIFI in the JGH2 band is supplied to an input terminal l from a BS converter (not shown). When the satellite broadcasting signal is of the MUSE transmission system, the first intermediate frequency signal SIF+ has non-modulated portions at regular intervals, as shown in FIG. 2A, for example. 17 μsec is recommended as this non-modulation period tc.

This first intermediate frequency signal 4s+Fx is supplied to the frequency converter 2. This frequency converter 2 is supplied with a local excavation signal SL from a voltage-controlled excavator (hereinafter referred to as rVCOJ).

The second intermediate frequency signal SIF2 output from the frequency converter 2 is supplied to the FM demodulator 5 via the bandpass filter 4. The demodulated signal output from this FM demodulator 5 is supplied to an output terminal 6, and a changeover switch 7
is supplied to the fixed terminal of a 914.

The output signal of this changeover switch 7 is supplied to a sample hold circuit 9 via a low pass filter 8. and,
The output signal of this sample hold circuit 9 is supplied to the VCO 3 as a control signal, and the output signal of the selector switch 7 is
Supplied to the fixed terminal on the side.

Reference numeral 10 denotes a key pulse generator, and from this key pulse generator lO, a high level "1'" is generated corresponding to the non-modulation period tc of the first intermediate frequency signal 5IFI, and a low level is generated corresponding to the signal period to. Key pulse signal P that becomes “0”
(shown in FIG. 2B) is output. This key pulse signal P is supplied to the sample and hold circuit 9, and is also supplied to the changeover switch 7 as a changeover control signal. and,
The changeover switch 7 is set so that the key pulse signal P is at high level "1".
and when the low level is "0", they are connected to the a side and the b side, respectively.

In the above configuration, when the first intermediate frequency signal SIFI is in the non-modulation period tc and the key pulse signal P is at a high level "!", the changeover switch 7 is connected to the aIR11, so the FM[i unit 5 The output signal of
is supplied to

Here, if the intermediate frequency fi of the second intermediate frequency signal 5IF2 deviates from the specified l1fi (for fIs, 402.78MHz), the FM demodulator 5 outputs a corresponding error signal, so the corresponding error signal is output from the FM demodulator 5. Only VCO3
The oscillation frequency also shifts, and as a result, the second intermediate frequency signal 5I
The frequency of F2 is controlled to be constant.

Also, the first intermediate frequency signal S IFI is 11'lt in signal order.
.

When the key pulse signal P is at the low level "0'', the selector switch 7 is connected to the b side, so the output of the sample and hold circuit 9 is held at the value before the transition to state t3. The oscillation of °VCO3 is controlled by .

Further, as an average value type AFC circuit, for example, there is a digital system using a microcomputer and a synthesizer (see Japanese Patent Laid-Open No. 63-821, etc.).

FIG. 4 shows an example of this, and is an example applied to a BS tuner.

Portions corresponding to those in FIG. 3 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In the figure, a demodulated signal output from an FM demodulator 5 is converted into a digital signal by an A/D converter 11 and then supplied to a computer 12.

Further, 13 is a synthesizer, and an oscillation signal from the VCO 13a is supplied to a phase comparator 13d via a cascade connection circuit of a distributor 13b1 and a frequency divider 13c. An oscillation signal from an oscillator 13e is supplied to this phase comparator 13d, and a comparison error signal from this phase comparator 13d is supplied as a control signal to the VCO 13a via a low-pass filter 13f. Then, the VCO distributed by the distributor 13b
The oscillation signal from I3a is supplied to the frequency converter 2 as a local oscillation signal SL.

Further, the frequency divider 13c of the synthesizer 13 is controlled by the computer 12.

In the above configuration, if the drive frequency of the phase comparator 13d is constant, the oscillation frequency of the VCO 13a is
It is uniquely determined by the frequency division ratio of c, and its stability is comparable to that of the reference Q oscillator 13e, and generally provides stability comparable to that of a crystal oscillator.

Here, if the intermediate frequency fi of the second intermediate frequency signal 5IF2 deviates from the specified value, the FM demodulator 5 outputs a corresponding error signal, which is transmitted to the A/D converter 11.
After being converted into a digital signal, the signal is supplied to the computer 12 and subjected to appropriate processing. And VCO1
The frequency division ratio of the frequency divider 13c is controlled by the computer 12 so that the oscillation frequency of the frequency divider 3a follows the deviation,
As a result, the intermediate frequency fi of the second intermediate frequency signal 5IF2
is controlled so that it is constant.

[Problems to be Solved by the Invention] By the way, according to the example in FIG. 3, since it is an analog system, adjustment is complicated and correction of temperature characteristics etc. is required.
There are also problems such as aging.

On the other hand, even with the digital system as shown in the example in Figure 4, control is performed based on the IM modulation signal from the FM demodulator 5, which is an analog signal, so the problem in the example in Figure 3 is essentially solved. It has not been.

Therefore, in this invention, A
The purpose is to provide an FC circuit.

[Means for Solving the Problems] The present invention includes a frequency converter that mixes an excavation signal from an excavation means with a high-frequency human signal and outputs an intermediate frequency signal, and a frequency converter that outputs an intermediate frequency signal and that counts the intermediate frequency when the intermediate frequency signal is supplied. The device comprises a counting means and a calculation means for calculating the deviation of the intermediate frequency from a specified value based on the count value of the counting means, and the oscillation frequency of the oscillation means is controlled based on the calculation result of the calculation means. .

[Function] In the above configuration, the oscillation frequency of the excavation means 13a is controlled based on the count value I( of the intermediate frequency f1. In other words, the total value l( is generally a digital quantity, and the oscillation frequency of the excavation means 13a is controlled based on the count value I( of the intermediate frequency f1. The oscillation frequency of the oscillation means 13a is controlled by the oscillation means 13a, and problems such as complicated adjustment as in the analog system are eliminated.

[Embodiment] An embodiment of the present invention will be described below with reference to FIG. In this figure 1, figures 3 and 4
Portions corresponding to those in the drawings are denoted by the same reference numerals, and detailed explanation thereof will be omitted.

In the same figure, a second intermediate frequency signal 5IF2 outputted from the frequency converter 2 is converted to FM through a cascade connection circuit of a bandpass filter 4 and a distributor 14! The demodulated signal is supplied to the FM demodulator 6 and output from the FM demodulator 5. The It signal is supplied to output terminal 6.

Further, the second intermediate frequency signal 5I distributed by the distributor 14
F2 is supplied to the counter 16 via the connection switch 16. And the counted value from this counter 1G is a computer! 2.

Further, the key pulse signal P from the key pulse generator 10 is supplied to the computer 12 and also to the connection switch 15. The connection switch 15 is turned on and off when the key pulse signal P is at a high level "1" and a low level "0", respectively.

In the above configuration, the first intermediate frequency signal S IFI is in the non-modulation period tc, and the key pulse signal P is at a high level "l".
”, the connection switch 15 is turned on and the second
The intermediate frequency signal 5IF2 is supplied to a counter 16, and its frequency is counted. Then, when this period tc passes and the signal period to begins, and the key pulse signal P becomes low level "0", the connection switch 15 is turned off and the second intermediate frequency signal 5IF2 is no longer supplied to the counter 16. , counter]6 holds the following values as a count value K (K is an integer).

K=fi-tc In this case, if tc is constant, the count value has the second
It is proportional to the intermediate frequency fi of the intermediate frequency signal 5IF2. Since this count value is a digital quantity, it can be easily read by the computer 12. This count KiK
is a predetermined value K' when the intermediate frequency f1 is a predetermined value
becomes.

Here, if a deviation occurs in the frequency of the first intermediate frequency layer number S IFI, the frequency fL of the local oscillation signal SL from the VCO 13a of the synthesizer 13 has not changed yet, so the intermediate frequency f1 will be lower than the specified value. A deviation of Δft occurs. Therefore, the deviation Δ between the count value ■( and the predetermined value ′)
K occurs.

The computer 12 calculates the deviation Δ■( from the count value '), and further calculates the deviation Δfi of the intermediate frequency f1 from this deviation Δ.
The frequency divider 13 changes the frequency fL of the local excavation signal SL from the VC013a so that this deviation Δf1 does not occur.
The frequency division ratio of c is controlled.

As a result, the frequency fL changes by ΔfL, so that the intermediate frequency fi is controlled to be the specified value.

Although not described above, after the above series of operations is completed, a reset signal R is supplied from the computer 12 to the counter 816 (shown in FIG. 2C), and the counter 1111K is reset after each series of operations.

By the way, as mentioned above, the intermediate frequency f1 is 402.7
Assuming that the frequency is 8 MHz and the non-modulation period tc is 17 usee, the count value I( will be 6847 if the intermediate frequency fi is maintained at a specified value.

If K differs by 1, the corresponding frequency shift Δfi will be Δfi=l/lc″−=58.8 kHz.

Therefore, the resolution is 5B and 8kHz. If higher resolution is required, the sum of the past 11 count values may be calculated, and the difference frequency Δf1 may be calculated using the following equation in place of K.

Δfi=1/ (n-tc)'i58.8/n (K
Hz) However, in this case, the resolution of the synthesizer 13 must also be at the same level.

As described above, according to the present example, the VC of the synthesizer 13 is calculated based on the count value I of the intermediate frequency f1 of the second intermediate frequency signal S IF2, which is a digital quantity counted by the counter 16.
The oscillation frequency of O13a is controlled, and problems such as complicated adjustment, which occur in conventional analog systems, can be eliminated.

In the above-mentioned embodiment, the reset signal R is supplied from the computer 12 to the counter 16, and the count value I (is reset for each series of operations, but the counter 16 is not reset. Alternatively, the computer 12 may be configured to calculate the current count value from the difference from the previous count value.

Further, in the above-described embodiment, the specified value of the intermediate frequency fi is 402.78 MHz, but it can be similarly applied to other cases where the specified value is 134.26 MHz.

C. Effects of the invention As explained above, according to the invention, the oscillation frequency of the oscillation means is controlled based on the count value of the intermediate frequency, which is a digital quantity, and the adjustment is complicated as in the analog system. It is possible to solve problems such as -t1.

[Brief explanation of the drawing]

FIG. 1 is a structural diagram showing one embodiment of the present invention, FIG. 2 is a diagram for explaining the same, and FIGS. 3 and 4 are structural diagrams of a conventional example. 1...Input terminal 2...Frequency converter 4...Band pass filter 5...FM demodulator 6...Output terminal 10...Key pulse generator 12...Computer 13 Synthesizer ]4...Distributor 15...Connection switch 16...Counter

Claims (1)

[Claims] (1) A frequency converter that mixes a high frequency input signal with an excavation signal from an oscillation means and outputs an intermediate frequency signal, a counting means that is supplied with the intermediate frequency signal and counts intermediate frequencies, and a counter of this counting means. an automatic frequency control circuit comprising a calculation means for calculating a deviation of the intermediate frequency from a specified value based on a numerical value, and an oscillation frequency of the oscillation means is controlled based on the calculation result of the calculation means. .