JPH02306789A - Picture processing device - Google Patents

Abstract

PURPOSE:To improve the transmission efficiency by generating a difference signal between adjacent video signals by 1H for one vertical period based on an inputted video signal and coding the difference signal and transmitting the result. CONSTITUTION:A 1st horizontal line of video signal L1 inputted from an input terminal 1 and outputted from an A/D converter 2 is inputted to a differential arithmetic unit 4 and inputted to a shift register 3. Then a 2nd horizontal line of video signal L2 is inputted to the differential arithmetic unit 4 via the A/D converter 2 and inputted to the shift register 3. In this case the 1st horizontal line of video signal L1 is supplied from the shift register 3 to an inverting input of the differential arithmetic unit 4, the differential arithmetic unit 4 applies the difference arithmetic operation of both the signals and outputs its difference signal H2 to an encoder 8. Thus, a low frequency component of a video signal is eliminated, only a high frequency component is sent to apply the band compression of the transmission signal to improve the transmission efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an image processing device that can compress the transmission band of a video signal when transmitting the video signal.

(Prior Art) A conventional image processing device that transmits a video signal transmits the video signal in the same band as it is, and adopts a method in which the receiving side also receives the video signal as is.

(Problem to be Solved by the Invention) For this reason, the transmission line requires a sufficient bandwidth to transmit the video signal as it is, which causes a problem in that the transmission efficiency decreases accordingly.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an image processing device that improves transmission efficiency by compressing the band of video signals to be transmitted.

(Means for Solving the Problems) In order to solve the above problems, an image processing device of the present invention includes an input terminal for inputting a video signal, and a delay in sequentially delaying the video signal input from the input terminal by one horizontal synchronization period. and a delay means for sequentially outputting a difference signal between the video signal input from the input terminal and a video signal delayed by one horizontal synchronization period by the delay means, and outputting only the video signal of the first horizontal line as is. difference signal output means, and a video signal of the first horizontal line outputted from the difference signal output means and the subsequent one horizontal line 3tl! An input means for sequentially inputting a difference signal for a period, and a video signal for the first horizontal line inputted from the input means and a difference signal for the subsequent 1 horizontal period J4 are sequentially added to each horizontal line. and video signal restoring means for sequentially restoring the video signals of.

(Function) By introducing the video signal inputted from the input terminal into the delay means, the video signal is sequentially delayed by one horizontal period of 3ilIuJJ over one vertical period and output.

By guiding the video signal input from the input terminal and the video signal delayed by one horizontal synchronization period by the delay means to the difference signal output means, the video signal input from the input terminal is guided to the difference signal output means. A difference signal between the signal and a video signal delayed by one horizontal synchronization period by the delay means is sequentially output.

Further, only the video signal of the first horizontal line is output as is. This makes it possible to remove the low frequency components of the video signal and transmit only the high frequency components.

On the other hand, the video signal of the first horizontal line output from the difference signal output means and the difference signal for one subsequent horizontal synchronization period are sequentially inputted from the input terminal. Then, the video signal for each horizontal line is sequentially restored by sequentially adding the video signal of the first horizontal line input from the input terminal and the subsequent difference signal for one horizontal synchronization period in the video signal restoring means.

That is, the video signal of the first horizontal line inputted from the input terminal and the subsequent difference signal for one horizontal synchronization period are inputted to an addition calculator, and then inputted to a shift register that delays one horizontal synchronization period, The IH-delayed signal from the shift register is input to the addition calculator. This results in
When the video signal of the first horizontal line is input to the addition unit, since the signal is not held in the shift register, no signal is supplied from the shift register to the addition unit, and the video signal of the first horizontal line is input to the addition unit. The signal is output as is and is also supplied to the shift register.

When the difference signal between the video signal of the first horizontal line and the video signal of the second horizontal line is input to the addition calculator, the video signal of the first horizontal line held in the shift register is supplied to the addition calculator. Therefore, the addition calculator restores the video signal of the second horizontal line by adding the video signal of the first horizontal line and the difference signal. The video signal of this second horizontal line is output as is and is also supplied to the shift register. By performing such signal processing over one vertical period, the original video signal is restored.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the electrical configuration of a signal sending system of an image processing apparatus according to the present invention.

In the figure, an input terminal 1 through which a video signal is introduced is connected to a synchronization separation circuit 6 that separates a synchronization signal from the video signal, and an A that converts an analog signal into a digital signal.
/D converter 2, and the output of the A/D converter 2 is connected to the plus input of the difference calculator 4,
■Connected to shift register 3 which performs horizontal synchronization period bone delay. Further, the output of the shift register 3 is connected to the minus input of the difference calculator 4.
The output of is connected to an output terminal 9 via an encoder 8 that performs encoding for transmission (for example, Huffman encoding).

On the other hand, an output 61 of the synchronization separation circuit 6 indicating the separated horizontal synchronization signal S is connected to the clock terminal (CK terminal) of the D-flip-flop 7, and a synchronization signal indicating the separated vertical synchronization signal Sv. The output 62 of the separation circuit 6 is D
- Connected to the data input terminal (D#A) of flip-flop 7, and connected to the output terminal (D#A) of D-flip-flop 7.
Q output) is connected to the clear terminal (CLR terminal) of the shift register 3 as a clear signal. Also, A/
The D converter 2, shift register 3 and encoder 8 include:
A clock signal from a clock signal generator 5 is provided, and each circuit is configured to be synchronized by this clock signal.

Next, the operation of the signal transmission system of the image processing device with the above configuration is as follows.
This will be explained with reference to the waveform diagram of the input/output signals to each terminal of the D-flip-flop 7 shown in FIG. 2, and the waveform diagram of the output signal of the difference calculator 4 shown in FIG.

The video signal input from input terminal 1 is sent to A/D converter 2.
After being converted into a digital signal by Supplied to the negative input. That is, the difference signal between the video signals of adjacent IH portions appears at the output of the difference calculator 4.

Here, 7, the output of the D-flip-flop 7 falls in synchronization with the fall of the vertical synchronization signal Sv supplied to the data input, and the first output signal supplied to the clock terminal after the vertical synchronization signal Sv rises. Since the signal Sc that rises in synchronization with the rise of the horizontal synchronization signal S is sent out as a clear signal, the shift register 3 to which this clear signal SC is led is set to 1 by the vertical synchronization signal SV.
It is cleared every vertical period, and is cleared by the first horizontal synchronization signal S after the vertical synchronization signal S rises.

Therefore, the video signal of the first horizontal line inputted from the input terminal 1 and outputted from the A/D converter 2 is inputted to the difference calculator 4 and also inputted to the shift register 3. At this time, since the shift register 3 is in an initial state where no signal is held, nothing is supplied to the minus input of the difference calculator 4, and as a result, the video signal L1 of the first horizontal line is It passes through the arithmetic unit 4 and is output as is (indicated by signal H). Next, the video signal L2 of the second horizontal line is input to the difference calculator 4 via the A/D converter 2, and is also input to the shift register 3. At this time, since the video signal L+ of the first horizontal line is supplied from the shift register 3 to the minus input of the difference calculator 4, the difference calculator 4
A difference calculation is performed to subtract the video signal L1 of the first horizontal line from the video signal L2 of the second horizontal line, and the difference signal H2("
Lz L,) is output to the encoder 8. That is,
By performing such a difference calculation, the low frequency components of the video signal are removed and only the high frequency components are transmitted, thereby compressing the band of the transmission signal and improving the transmission efficiency.

The difference calculator 4 performs such a difference calculation from the video signal L2 of the second horizontal line to the video signal L of the 525th horizontal line.
By sequentially performing up to SO5, the output is H)
(L3 Lx) -H5zs (Lszs-L
sxa> difference signals appear sequentially. This difference signal H1°H,
... are encoded by the encoder 8 and then sent out via the output terminal 9.

On the other hand, FIG. 4 shows the electrical configuration of the signal receiving system of the image processing apparatus for restoring the video signal encoded in this manner to the original video signal.

In the figure, an input terminal 10 to which an encoded video signal is introduced is connected to a synchronous part detection circuit 15 that detects synchronous parts from the signal, and also decodes the signal (
For example, the output of the decoder 11 is connected to one input of the addition calculator 12. The output of the adder 12 is a D/D converter that converts the derived digital signal into an analog signal.
It is connected to the A converter 17 and also to a shift register 13 that performs a horizontal synchronization period delay, and the output of the shift register 13 is connected to the other input of the addition calculator 12. Further, the output of the D/A converter 17 is led to a video device such as a television receiver (not shown) via an output terminal 18.

On the other hand, the output 151 of the synchronous portion detection circuit 15 indicating the separated horizontal synchronous signal S8 is connected to the clock terminal (CK terminal) of the D-flip-flop 16, and the synchronous portion indicating the separated vertical synchronous signal SV. The output 152 of the detection circuit 15 is connected to the data input terminal (D terminal) of the D-flip-flop 16, and the output terminal (Q output) of the D-flip-flop 16 is used as a clear signal to clear the shift register 13. Connected to the terminal (CLR terminal). Further, the decoder 11, shift register 13, and D/A converter 17 are supplied with a clock signal from the clock signal generator 14, and the respective circuits are synchronized by this clock signal.

Next, the operation of the signal receiving system of the image processing device with the above configuration is as follows.
This will be explained with reference to the waveform diagram of the input/output signals to each terminal of the D-flip-flop 16 shown in FIG. 5, and the waveform diagram of the output signal of the addition calculator 12 shown in FIG.

The encoded video signal input from the input terminal 10 is
The signal is input to the synchronous part detection circuit 15 and decoded by the decoder 11, and then input to the addition calculator 12. After being added to the word () from the shift register 13 in the addition calculator 12, the signal is inputted to the shift register 13 again and inputted to the D/A converter 17, where it is converted into an analog signal. After being restored to the original video signal, it is sent out from the output terminal 18.

Here, the output of the D-flip-flop 16 falls in synchronization with the fall of the vertical synchronization signal Sv supplied to the data input, and the first signal supplied to the clock terminal after the vertical synchronization signal Sv rises. Since the signal Sc that rises in synchronization with the rise of the horizontal synchronization signal SN is sent as a clear signal, the shift register 13 to which this clear signal S is guided is cleared every vertical period by the vertical synchronization signal Sv. , clearing is canceled by the first horizontal synchronizing signal SN after the vertical synchronizing signal Sv rises.

Therefore, the signal H4 corresponding to the first horizontal line input from the input terminal 10 and decoded by the decoder 11
is input to the addition calculator 12.

At this time, since the shift register 3 is in an initial state where no signal is held, nothing is supplied to the other input of the addition operator 12, and as a result, the signal H+ corresponding to the first horizontal line is (=L+) passes through the adder 12 and is output as is to the A/D converter 17 and shift register 13.

Next, the difference signal H2 between the second horizontal line and the first horizontal line is
is input to the addition calculator 12. At this time, the shift register 3 outputs a signal HI corresponding to the first horizontal line.
(=L+) is supplied to the other input of the addition calculator 12, so the addition calculator 12 adds the signal H, (=L,) corresponding to the first horizontal line and this difference signal Hz. As a result, the video signal L of the second horizontal line! (=H1
+l(,) is output to the A/D converter 17 and shift register 13.

The addition calculator 12 performs this addition operation using the difference signal H2.
By performing the processing sequentially from to the difference signal H523, the video signal L2 of the second horizontal line...the video signal LSNS of the 525th horizontal line appear in sequence at the output. In this way, the video signal L1 of the first horizontal line to the video signal Lszs of the 525th horizontal line are sequentially output to the D/A converter 17, where they are converted into analog signals, and then
By outputting from the output terminal 18, the video signal of frame (2) is restored.

(Effects of the Invention) The image processing device of the present invention generates a difference signal between video signals for adjacent IHs in one vertical period based on a video signal input from an input terminal, and encodes this difference signal. Since the configuration is configured to transmit, it is possible to remove the low frequency components of the video signal and encode and transmit only the high frequency components, thereby improving transmission efficiency. Further, by inputting a signal obtained by encoding such a difference signal and sequentially adding video signals for IH in the vertical period, it is possible to restore the original video signal.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the electrical configuration of the signal transmission system of the image processing device of the present invention, Fig. 2 is a waveform diagram of input/output signals to each terminal of the D-flip-flop, and Fig. 3 is a difference calculation 4 is a block diagram showing the electrical configuration of the signal receiving system of the image processing device of the present invention, and FIG. 5 is a waveform of input/output signals to each terminal of the D-flip-flop. FIG. 6 is a waveform diagram of the output signal of the addition arithmetic unit. 1... Input terminal 2... A/D converter 3... Shift register 4... Difference calculator 6... Synchronization separation circuit 7... D-flip flow, P8... Encoder IO ... Input terminal 11 ... Decoder 12 ... Addition unit 13 ... Shift register 15 ... Synchronous part detection circuit 16 ... D-flip-flop 17 ... D/A converter

Claims (1)

[Scope of Claims] 1) an input terminal for inputting a video signal; a delay means for sequentially delaying the video signal input from the input terminal by one horizontal synchronization period and outputting the video signal; and a video signal input from the input terminal. and a video signal delayed by one horizontal synchronization period by the delay means, and a difference signal output means for sequentially outputting a difference signal between the video signal and the video signal delayed by one horizontal synchronization period by the delay means, and outputting only the video signal of the first horizontal line as is; an input means for sequentially inputting the video signal of the first horizontal line and the difference signal for one subsequent horizontal synchronization period, and the video signal of the first horizontal line inputted from the input means and the difference signal for one horizontal synchronization period thereafter; An image processing apparatus comprising: video signal restoring means for sequentially restoring a video signal for each horizontal line by sequentially adding signals.