JPH02288938A - Shared memory access controller for multiprocessor - Google Patents

Abstract

PURPOSE:To enable an individual microprocessor to make access to a shared memory by providing the shared memories more than the microprocessors. CONSTITUTION:The number of shared memories in multiprocessor system is set more than that of microprocessors 10 and 15. Therefore, when the microprocessor (#1) 10 makes access to a memory (#1) 14, the microprocessor (#2) 15 can make access to a memory (#2) 19, and adversely, when the microprocessor (#1) 10 makes access to the memory (#2) 19, the microprocessor (#2) 15 can make access to the memory(#1) 14. In such a manner, simultaneous access to each of the shared memories 14 and 19 by each of the microprocessors 10 and 15 can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a shared memory access control device for high-speed access to shared memory in a multiprocessor system.

2. Description of the Related Art Conventionally, a shared memory access control device for this type of multiprocessor system is equipped with a data buffer, an address multiplexer, an access controller, and one shared memory. It is configured so that the shared memory can be accessed through divided access.

FIG. 2 is a block diagram showing the configuration of a shared memory access control device for a conventional multiprocessor system. In FIG. 2, a microprocessor 20.25 provides control of the system. The data buffer 21 controls the signal flow of MPU #1 data signal C to the microprocessor 20, MPU #2 data signal C to the microprocessor 25, and memory #1 data signal C to the memory 24. address multiplexer 22
is the M P tL# 1 address signal d from the microprocessor 20 and the MPU# from the microprocessor 25.
2 The address signal e is sent to the MPU of the controller 23.
A higher selection signal is selected and outputted as a memory #1 address signal f. The access controller 23 receives the MPU #1 control signal i from the microprocessor 20.
and MPU4f2 controller 1- from microprocessor 25
Memory #1 controller 1 to memory #1, which time-divides 7 accesses to memory 24, is output in response to input signals 17 and 17, and arbitration is performed.

In this way, the conventional shared memory access control device of the multiprocessor system described in 1.
By time-sharing access to the access controllers 1-0-23, each microphone 17 processor 20.
25 can be accessed.

Problems to be Solved by the Invention However, in the conventional shared memory access control device for the multiprocessor system described above, each microb 17 accessor accesses one shared memory in a time-sharing manner. There was a problem in that the microphones 17 and TT7 processors could not access the shared memory at the same time.

The present invention solves these conventional problems,
An object of the present invention is to provide an excellent shared memory access control device for a multiplex system which allows individual microbuses to simultaneously access shared memory.
The target is

Means for Solving the Problems I - In order to solve the problem, the present invention provides a shared memory in which the number of shared memories is greater than the number of microprocessors, and the shared memory is connected to each microprocessor through each data buffer, address multiplexer, and access controller. Each memory is configured to access a plurality of shared memories.

According to the configuration described in Section 142, by making the number of shared memories in a multiprocessor system greater than the number of microprocessors, each microphone 17 processor can access the shared memory at the same time, and the amount of access by the microprocessors to the shared memory can be reduced. This has the effect of speeding up data transfer between microprocessors using shared memory as a buffer.

Embodiment FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 1, a microprocessor 10.15 provides control of the system. Data buffer 1116 is M)) U #1 data signal - “r”; a, M I)
Memory # for LJ#2 data communication-reb and memory 4
1 data signal C, memory #2 data signal to memory 9 - signal f17 of bow c' are controlled from 1 to 1.

Address multiplex → Nozu 2, 17 is M I) U
#: ] Address signal d and MPU#2 address signal e are selected according to MPU selection signals g and g of access controller 1 to roller 3.18, and memory #1 address signal -p is selected.
E, f, memory #2 address signal-p3. Output as f ′. Access: 7-1 to Roller 3, No. 18, l: MPU #1 Con 1 to IV-Le Faith i,
MPU #2 = 1 - 17 - Outputs memory # 1 control signal 1 (, memory # 2 control 1 - 1 V - signal river (') from memory # 1 control signal 1 ('), and outputs each memory 14.19 / ＼Access which microphone 1'1p I7 set 0,15
or through mediation.

Next, the operation of the configuration described in "-1" will be explained. - In the configuration described in l1, if the microbe 17 setter (#1) 10 is accessing the memory (#iM4), the microphone 1 colober setter (#2) 15 can access the memory (#2) 19, and vice versa. When the microprocessor (#1) 10 is accessing the memory (#2) 19, the microprocessor (#2) 15 can access the memory (#1) 1/I.

Thus, according to embodiment 1, the individual microprocessors 10.15 simultaneously access each shared memory 1419.
It has the advantage of being accessible. Further, in the above embodiment, by increasing the amount of accesses of the microprocessor 10.15 to the shared memory 14.19, data transfer between microprocessors using the shared memory 14.19 as a buffer can be speeded up. .

Effects of the Invention As described above, according to the present invention, since the shared memory control device of a multiprocessor system is provided with more shared memories than the number of microprocessors, the advantage is that each microprocessor can access each shared memory. have Furthermore, by increasing the amount of access by microprocessors to the shared memory, data transfer between microprocessors using the shared memory as a buffer can be speeded up.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a shared memory access control device for a multiprocessor system according to an embodiment of the present invention, and FIG. 2 is a schematic block diagram of a shared memory access control device for a conventional multiprocessor system. 10, Is... microprocessor, 11.16...
・Data buffer, 12.17...Address multiplexer, 13.18...Access controller, 14
．． 19...Memory. Agent Yoshihiro Morimoto

Claims (1)

[Claims] 1. A shared memory access control device for a multiprocessor, comprising shared memories equal to or greater than the number of processors controlled by each of a plurality of microprocessors via a plurality of data buffers, an address multiplexer, and an access controller.