JPH0227620Y2 - - Google Patents

Description

[Detailed description of the invention] [Technical field of the invention] This invention is a limiter that amplifies the audio signal before FM detection and removes the amplification variation in, for example, an audio intermediate frequency amplification circuit (hereinafter referred to as SIF circuit). Regarding circuits.

[Technical background of the invention]

The limiter circuit in the SIF circuit plays the role of amplifying the audio signal and removing amplitude changes before FM detection.

A conventional example of such a limiter circuit is shown in FIG. In the figure, Q ₁₁ to Q ₁₈ are transistors, R ₁₁
~ _R21 is a resistor and _C11 is a capacitor. Also,
IN is the input terminal, OUT is the output terminal, and +B is the power supply.

The illustrated limiter circuit consists of transistors Q ₁₁ ,
First stage limiter amplifier consisting of _Q12 , transistor
It consists of two limiter amplifiers: a two-stage limiter amplifier consisting of transistors Q ₁₄ and Q ₁₅ , and a three-stage limiter amplifier consisting of transistors Q ₁₇ and Q ₁₈ . The limiter amplifier in each stage has a differential amplifier circuit configuration.

In the first-stage limiter amplifier, a resistor _R11 is inserted between the differential inputs, so an offset occurs due to the voltage drop across this resistor _R11 . Therefore, the first stage output voltage V _AO decreases, the second stage input voltage V _BI decreases, and the second stage output voltage V _BO decreases. resistance here
Since DC feedback is applied by R ₁₄ , the base bias voltage V _b of transistors Q ₁₂ and Q ₁₅ decreases, and the first stage input voltage V _AI decreases.
As a result, the bias voltage of the limiter amplifiers in the first and second stages gradually decreases, but as the bias voltage decreases, the current flowing through the limiter amplifiers decreases and the gain decreases, so the output voltages of the first and second stages V _AO , V _BO There is a movement to raise the
Balance it out at the appropriate place. At this time, since the rate at which the two-stage input voltage V _BI and the base bias voltage V _b decrease do not match, an offset also occurs in the two-stage limiter amplifier. In the three-stage limiter amplifier, by setting the ratio of the resistance values of feedback resistor _R14 and resistor _R15 to an appropriate value, the base bias voltages of transistors _Q17 and _Q18 are matched to eliminate offset. . In this case, the base currents of the four transistors Q ₁₁ , Q ₁₂ , Q ₁₅ , and Q ₁₈ flow through the resistor R 14, and the base currents of the four transistors Q ₁₁ , Q 12 , Q 15 , and Q 18 flow through the resistor R ₁₅ .
Q ₁₇ Only one base current flows. Therefore, if each base current is equal, the resistance _R14 and
The resistance ratio with _R15 should be 1:4.

[Problems with background technology]

However, in the case of the above configuration, an offset occurs in the two-stage limiter amplifier, so it is not suitable as a limiter amplifier in an SIF circuit. That is, F.M.
In a detection operation, subtle changes in the rise and fall of an input signal have a large effect on the output. In other words, the AMR of the SIF circuit is greatly influenced by the output waveform of the limiter circuit. In a limiter circuit with an offset as described above, the second
As shown in the figure, the rising and falling edges of the signal after amplitude limiting (indicated by the broken line in the figure) are normal rising and falling edges (indicated by the solid line in the figure) when passed through a limiter circuit without offset. (the rising and falling edges of the signal shown) will be different. This significantly worsens the AMR of the SIF circuit. In particular, a two-stage limiter amplifier receives a signal that has not yet undergone complete amplitude limiting, that is, a signal that is still a sine wave rather than a rectangular wave signal, and converts this into a rectangular wave. Offset greatly affects the rise and fall of the output waveform of the limiter circuit. In addition, in Figure 2, V _OS
is the offset voltage.

[Purpose of invention]

This invention was made in order to cope with the above-mentioned circumstances, and its purpose is to provide a limiter circuit without offset.

[Summary of the idea]

This idea can be explained using, for example, FIG. 3. In transistors Q ₃₄ and Q ₃₅ that constitute a two-stage limiter amplifier, load resistance R _{32 is}
and the transistor _Q33 through the base-emitter current path forming the emitter follower.
The voltage drop in the path to the base of Q ₃₄ and the power +
The circuit constants are set so that the voltage drop in the path from B ₁ to the base of transistor Q ₃₅ via load resistor R ₃₆ , the base-emitter current path of transistor Q ₃₆ forming an emitter follower, and the feedback resistor R ₄₄ is equal. is set.

[Example of idea]

Hereinafter, one embodiment of this invention will be described in detail with reference to the drawings. In the figure, the input terminal IN is connected to the base of a transistor _Q31 , and the collector of this transistor _Q31 is connected to the first power supply + _B1 . Transistor Q ₃₂ forms a differential pair with transistor Q ₃₁ , and the common connection point of its emitters is a resistor.
Grounded through a series circuit of R ₃₁ and diode D ₁₁ . The collector of this transistor Q ₃₂ is connected to the power supply +B ₁ via a load resistor R ₃₂ .
Further, the collector of this transistor Q ₃₂ is connected to the base of a transistor Q ₃₃ , the collector of this transistor Q ₃₃ is connected to the first power supply +B ₁ , the emitter is connected to the base of the transistor Q ₃₄ , and the resistor R ₃₃ to ground. The collector of transistor Q ₃₄ is connected to the power supply +B ₁ . Transistor Q ₃₅ is a transistor
It forms a differential pair with _Q34 , and the common connection point of its emitters is grounded through a series circuit of resistor _R35 and diode _D32 . The collector of transistor Q ₃₅ is connected to the base of transistor Q ₃₆ and to the power supply +B ₁ via load resistor R ₃₆ . The emitter of transistor Q ₃₆ is connected to the collector of transistor Q ₃₇ and also to the base of transistor Q ₃₈ via bias resistor R ₃₇ , so that the collector of transistor Q ₃₈ is connected to the second power supply +B ₂ . It is connected.
Transistor Q ₃₉ forms a differential pair with transistor Q ₃₈ , and the common connection point of its emitters is connected to transistor Q 38.
Connected to Q ₄₀ collector. transistor
The collector of Q ₃₉ is connected to the output terminal OUT and also to the second power supply +B ₂ via a load resistor R ₃₈ . The bases of transistors Q ₃₇ and Q ₄₀ are commonly connected, and the midpoint of the connection is connected to the second power supply +B ₂ via resistor R ₃₉ , and
It is grounded through a series circuit of diode D ₃₃ and resistor R ₄₀ . The emitters of transistors Q ₃₇ and Q ₄₀ are grounded via resistors R ₄₁ and R ₄₂ , respectively.

The base of the transistor _Q31 is a bias resistor
It is grounded through a series circuit of R ₄₃ and a capacitor C ₃₁ for bypassing the AC component. Bias resistance R ₃₄
The midpoint of connection between and capacitor C ₃₁ is a transistor
Connected to the bases of Q ₃₂ , Q ₃₅ , and Q ₃₉ . Furthermore, the emitter of the transistor _Q36 is
Transistors Q ₃₅ , Q _{32 ,}
Q ₃₉ is connected to the midpoint of the connection between resistor R ₄₃ and capacitor C ₃₁ .

Transistors Q ₃₁ and Q ₃₂ form a first-stage limiter amplifier, transistors Q ₃₄ and Q ₃₅ form a two-stage limiter amplifier, and transistors Q ₃₈ and Q ₃₉ form a three-stage limiter amplifier. Resistor R ₃₁ and diode D ₃₁
constitutes the constant current source of the first stage limiter amplifier, and the resistor
_R35 and diode _D32 form a constant current source for the two-stage limiter amplifier. Transistors Q ₃₇ , Q ₄₀ , diode D ₃₃ , and resistors R ₄₀ to _{R 42} form a current mirror circuit. As a result, the constant current amount of the three-stage limiter amplifier can be adjusted from the midpoint of the connection between resistors _R37 and _R44 to the transistor
It is set to the same value as the amount of current flowing into _Q37 . As a result, fluctuations in the emitter potential of the transistor _Q36 can be suppressed, thereby stabilizing the operation. Transistors Q ₃₃ and Q ₃₆ are output transistors forming emitter followers that lead the outputs of the first-stage limiter amplifier and second-stage limiter amplifier to the subsequent stage, respectively.

The operation of the limiter circuit described above is basically the same as the circuit shown in FIG. 1 above. However, the transistor Q ₃₄ is connected from the first power supply +B ₁ to the resistor R ₃₂ and the current path between the base and emitter of the transistor Q ₃₃ .
The voltage drop in the path from the first power supply +B ₁ to the base of the resistor R ₃₆ and the base of the transistor Q ₃₆
Circuit constants are set so that the voltage drops in the emitter-to-emitter current path and the path to the base of the transistor _Q35 via the resistor _R44 are equal. As a result, the offset of the two-stage limiter amplifier is eliminated, a limiter output with less waveform distortion can be obtained, and the AMR of the SIF circuit can be improved.

The specific values of the circuit constants shown in FIG. 3 are examples of circuit constants set to achieve the above object. In addition, how to determine the circuit constants is as follows:
The values of the circuit elements except the load resistor R ₃₂ may be set, and the resistance value of the load resistor R ₃₂ may be determined in accordance with the set value so as to achieve the above object. Below, we will use the formula to find the resistance value of this load resistor _R32 . Since the resistance values of the resistors R ₃₁ and R ₃₅ are equal, the constant current values of the first stage limiter amplifier and the second stage limiter amplifier are equal. Letting this be I _O , the current flowing through the resistor R ₃₂ will be I _O /2. If the constant current of the three-stage limiter amplifier is also I _O , then the current flowing through the resistor R ₄₄ is 1/β 4/2 I _O. This is done by using a resistor _R44 to eliminate the offset of the 3-stage limiter amplifier.
This is because the resistance ratio of R37 and _R37 is set to approximately 1:4. However, β is the DC current amplification factor of the transistor.

If the voltage of the first power supply +B ₁ is V _CC1 , then V _CC1 =I _O /2・R _a +V _F +1/β 4/2I _O・R _b +V _F +I _O・R _c +V _F ……(1) Since the relationship holds, I _O = V _CC1 −3V _F /Ra/2+2R/βb+R _c =0.32 [mA]
...(2) becomes. However, R _a , R _b , and R _c are the resistances R _{36 and} R 36 , respectively.
This is the resistance value of R ₄₄ and R ₃₅ . V _F is the forward voltage drop between the base and emitter of a transistor or the forward voltage drop of a diode.

Transistors Q ₃₁ and Q ₃₂ of the first stage limiter amplifier
Let the base currents of I ₁ and I ₂ be respectively, and I ₁ :I ₂ =
1:x, then 1/1+x・I _O・1/β・R ₁ = hlnx/1+x −hln1/1+x=hlnx (3). However, R _I is the input resistance of transistor Q ₃₁ . Here, if I ₂ =I ₁ +ΔI, then x=I ₁ +ΔI/I ₁ =1+ΔI/I ₁ (4). If ΔI≪I ₁ , then hlnx=hln(1+ΔI/I ₁ )=hΔI/I ₁ =h·(x−1) (5). From equations (3) and (5), 1/1+x・I _O・1/β・R _I =h・(x−1)……(6
) becomes. From equation (6), x ² −1=I _O /h・β・R _I ...(7) From equation (7), becomes. In this case, by appropriately setting the values of h, β, and R _I , x becomes 1.06.

Since the offset of the two-stage limiter amplifier is 0, R _d・x/1+x・I _O +V _F1 =R _a・I _O /2+V _F2 +R _b・4/2β・I _O (9) holds true. However, R _d is the resistance value of resistor R ₃₂ and V _F1 .
V _F2 is V _F of transistors Q ₃₃ and Q ₃₆ , respectively. From equation (9), R _d = R _a /2+R _b・2/β+V _F1 −V _F2 /I ₀ /x/1+x
...(10) becomes. Emitter current of transistors Q ₃₃ and Q ₃₆
I ₁₁ and I ₁₂ are: I ₁₁ = R _C・I _O +2V _F /Re=0.18 [mA] ...(11) I ₁₂ = V _CC2 −V _F /R _f +R _g・R _g /R _h =0.68 [mA]……(12
) becomes. However, R _e to _{R h} are the resistances R ₃₃ , R ₃₉ , and
The resistance values of R ₄₀ and R ₄₁ and V _CC2 are the voltage of the second power supply +B ₂ . From equations (11) and (12), V _F1 −V _F2 /I _O =h·lnI ₁₂ /I ₁₁ /I _O (13). Therefore, R _d =5.5/2×10 ³ +2/100×2×10 ³ +0.11×10 ³ /1.0
6/1+1.06 = 5.64×10 ³ [Ω].

Note that the above values were obtained through a number of approximations to facilitate calculation. In contrast,
The values shown in FIG. 3 are values obtained from computer simulation.

[Effect of idea]

Thus, according to this invention, a limiter circuit without offset can be provided.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional limiter circuit, FIG. 2 is a signal waveform diagram for explaining the influence of offset, and FIG. 3 is a circuit diagram showing an embodiment of the limiter circuit according to this invention. IN...Input terminal, OUT...Output terminal, +B ₁ ...
...First power supply, +B ₂ ...Second power supply, Q ₃₁ to _{Q 40} ...
…Transistor, R ₃₁ to R ₄₄ … Resistor, D ₃₁ to _{D 33}
...Diode, C ₃₁ ...Capacitor.

Claims (1)

[Claims for Utility Model Registration] A first transistor whose base is connected to an input terminal, and a transistor which forms a differential pair with the first transistor and whose collector is connected to a power supply via a first load resistor. a first differential amplifier circuit having two transistors; a third transistor having a base connected to the collector of the second transistor and forming an emitter follower; a third transistor having a base connected to the emitter of the third transistor; a second differential amplifier circuit having a fifth transistor forming a differential pair with the fourth transistor and having a collector connected to the power supply via a second load resistor; a sixth transistor connected to the collector of the fifth transistor and forming an emitter follower; a seventh transistor whose base is connected to the emitter of the sixth transistor via a first bias resistor; a third differential amplifier circuit comprising an eighth transistor forming a differential pair with the first transistor, the collector of which is connected to the output terminal, and the eighth transistor connected to the power supply via a third load resistor; the base of the transistor and the second,
a second bias resistor inserted between the bases of the fifth and eighth transistors; and a second bias resistor inserted between the emitter of the sixth transistor and the bases of the second, fifth, and eighth transistors. a feedback resistor; a capacitor inserted between the bases of the second, fifth, and eighth transistors and reference potential terminals; and a collector connected to a common connection point of the emitters of the seventh and eighth transistors; This 7th and 8th
A limiter circuit comprising: a ninth transistor forming a constant current source of the transistor; and a tenth transistor whose collector is connected to the emitter of the sixth transistor and which is connected in a current mirror to the ninth transistor. .