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JPH02260640A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02260640A
JPH02260640A JP8295489A JP8295489A JPH02260640A JP H02260640 A JPH02260640 A JP H02260640A JP 8295489 A JP8295489 A JP 8295489A JP 8295489 A JP8295489 A JP 8295489A JP H02260640 A JPH02260640 A JP H02260640A
Authority
JP
Japan
Prior art keywords
film
protective film
providing
openings
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8295489A
Other languages
Japanese (ja)
Inventor
Yukihiro Imura
行宏 井村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP8295489A priority Critical patent/JPH02260640A/en
Publication of JPH02260640A publication Critical patent/JPH02260640A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To prevent the deterioration of the characteristics of a MOSFET due to hot electrons, to superpose a second protective film and to prevent an intrusion of H and water from the outside by a method wherein openings are formed in a first layer protective film, P-SiN film, and the H in the MOSFET is diffused to the outside through the openings. CONSTITUTION:A gate electrode 3 is provided on a gate oxide film (a gate insulating film) 2 of a P-type semiconductor Si substrate 1 and N-type source and drain regions 4 and 5 are formed. The whole surface including the electrode 3 is covered with an interlayer insulating film 6 and openings are formed to provide metallic wirings 9. Then, the whole surface is covered with a P-SiN film (a first protective film) 10, openings 11 are formed, the substrate is exposed to a H2-free non-oxidizing atmosphere of 200 to 450 deg.C for 1 to 20 hours and H (hydrogen) is diffused to the outside through the openings 11. Subsequently, a second protective film, a P-SiN film 12 is deposited and the film 12 on pad parts only is removed. According to this constitution, the deterioration of the characteristics of a MOSFET due to hot electrons which are caused by the H can be inhibited up to a degree identical with the case where a PSG film is used.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関する。特に半導体集
積回路の保ii膜の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device. In particular, the present invention relates to a method of manufacturing a protective film for semiconductor integrated circuits.

〔発明の概要〕[Summary of the invention]

本発明は金属−酸化物一半導体からなるMO3型半導体
集積回路の製造において、保護膜にブラズマを利用した
化学的気相成長法により形成された窒化膜(P−3iN
)を第1層の保護膜として用い、集積回路内の水素を加
熱等の手段により大気中に外方拡散させた後に、同じく
プラズマを利用した化学的気相成長法により形成された
窒化膜(P−3iN)あるいはスパッタ法により形成さ
れたアルミニウム等の金属膜を第2層の保護膜として用
いるようにしたものである。
The present invention uses a nitride film (P-3iN) formed as a protective film by chemical vapor deposition using plasma in the manufacture of MO3 type semiconductor integrated circuits made of a metal-oxide-semiconductor.
) is used as the first layer protective film, hydrogen in the integrated circuit is diffused outward into the atmosphere by means such as heating, and then a nitride film ( A metal film such as aluminum (P-3iN) or aluminum formed by sputtering is used as the second layer protective film.

〔従来の技術〕[Conventional technology]

従来の保護膜を用いたMO3型半導体装置(集積回路)
の製造方法を第2図fal〜(「)を用いて説明する。
MO3 type semiconductor device (integrated circuit) using conventional protective film
The manufacturing method will be explained using FIG.

P型半導体基板51の表面にゲート酸化膜52を設ける
(第2図(a))。通常ポリンリコンよりなるゲート電
極53をゲート酸化膜52上の一部に設ける(第2図(
b))。ゲート電極53をマスクとしてN型のソース領
域54およびドレイン領域55をイオン注入等により形
成する(第2図(C))。ゲート電極53とゲート酸化
膜52を覆う層間絶縁膜56を形成する(第2図(d)
)。ソース領域54およびドレイン領域55の一部分の
領域からはゲート酸化膜52および層間絶縁膜56を除
去し、ゲート電極53の一部分の領域からは層間絶縁I
PJ56を除去して、コンタクトホールを形成した後、
アルミニウム等の金属配線59を用いて所望の領域を接
続する(第2図(e))。全面にP−3iNよりなる保
護膜60を堆積した後、外部引き出し部(パッド部)の
み保護膜60を除去する(第2図(r))。
A gate oxide film 52 is provided on the surface of a P-type semiconductor substrate 51 (FIG. 2(a)). A gate electrode 53 usually made of polyrecon is provided on a part of the gate oxide film 52 (see FIG. 2).
b)). Using the gate electrode 53 as a mask, an N-type source region 54 and a drain region 55 are formed by ion implantation or the like (FIG. 2(C)). An interlayer insulating film 56 is formed to cover the gate electrode 53 and the gate oxide film 52 (FIG. 2(d)).
). Gate oxide film 52 and interlayer insulating film 56 are removed from part of source region 54 and drain region 55, and interlayer insulating film 56 is removed from part of gate electrode 53.
After removing PJ56 and forming a contact hole,
Desired regions are connected using metal wiring 59 made of aluminum or the like (FIG. 2(e)). After depositing the protective film 60 made of P-3iN over the entire surface, the protective film 60 is removed only from the external lead portion (pad portion) (FIG. 2(r)).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

前述のように従来の技術では半導体集積回路の保護膜と
してP−3iNを用いている。P−3iNはPSG等の
リンガラスに比べ水分を非常に通しにくいからである。
As mentioned above, the conventional technology uses P-3iN as a protective film for semiconductor integrated circuits. This is because P-3iN is much less permeable to moisture than phosphorus glass such as PSG.

しかし、P−3iNの保護膜は半導体の微細化にともな
うホットエレクトロンによるMOS)ランジスタの劣化
を加速することが明らかになっている。この劣化は半導
体集積回路の製造工程で発生する水素がP−3iNによ
ってMOS)ランジスタ内に閉じ込められてしまうこと
により起こる@P−3iNは水分だけでなく水素も非常
に通しにくいからである。
However, it has been revealed that the P-3iN protective film accelerates the deterioration of MOS transistors due to hot electrons accompanying the miniaturization of semiconductors. This deterioration occurs when hydrogen generated during the manufacturing process of the semiconductor integrated circuit is trapped inside the MOS transistor by P-3iN. This is because P-3iN is extremely difficult to pass not only moisture but also hydrogen.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は上記の欠点を除去し、半導体の微細化に対応で
きる半導体集積回路の保護膜を提供するために、P−3
iN膜を第1層の保護膜として形成した後に、水素を含
まない非酸化性の雰囲気で熱処理を施し、MO5I−ラ
ンジスタ内に閉じ込められている水素をp−siNll
gに設けられた窓を通して半導体集積回路の外部へ拡散
させ、さらに、外部恋らの水素や水の侵入を防ぐために
、第2の保護膜としてP−3iNあるいはアルミニウム
等の金属膜を配置するようにした。
The present invention eliminates the above-mentioned drawbacks and provides a protective film for semiconductor integrated circuits that can cope with the miniaturization of semiconductors.
After forming the iN film as the first protective film, heat treatment is performed in a non-oxidizing atmosphere that does not contain hydrogen to remove the hydrogen trapped inside the MO5I transistor.
A metal film such as P-3iN or aluminum is placed as a second protective film to diffuse hydrogen and water to the outside of the semiconductor integrated circuit through the window provided in the second protective film. I made it.

〔作用〕[Effect]

MOS)ランジスタ内に閉じ込められている水素をP−
3iN膜に設けられた窓を通して半導体集積回路の外部
へ拡散させることで、水素に起因するMO3I−ランジ
スタのホットエレクトロンによる劣化を、P−3iN膜
を用いない場合と同程度にまで抑制することができる。
MOS) The hydrogen trapped inside the transistor is converted to P-
By diffusing to the outside of the semiconductor integrated circuit through the window provided in the 3iN film, it is possible to suppress the deterioration of the MO3I-transistor caused by hydrogen due to hot electrons to the same extent as when the P-3iN film is not used. can.

さらに、第2の保護膜によって、外部からの水素や水の
侵入を防ぐことができる。
Furthermore, the second protective film can prevent hydrogen and water from entering from the outside.

〔実施例〕〔Example〕

第1図+al〜(hlは本発明による半導体装置の製造
方法の工程順断面図である。P型半導体基板1の表面に
ゲート酸化膜2を設ける(第1図(a))。通常ポリシ
リコンよりなるゲート電極3をゲート酸化膜2の上の一
部に設ける(第1図(b))。ゲート電極3をマスクと
してN型のソース領域4およびドレイン領域5をイオン
注入等により形成する(第1図(C))。ゲート電極3
とゲート酸化膜2を覆う層間絶縁膜6を形成する(第1
図(d))。ソース領域4およびドレイン領域5の一部
分の領域からはゲート酸化膜2および層間絶縁膜6を除
去し、ゲート電極3の一部分の領域からは層間絶縁膜6
を除去して、コンタクトホールを形成した後、アルミニ
ウム等の金属配線9を用いて所望の領域を接続する(第
1図(e))。全面にP−3iNよりなる第1の保護膜
10を堆積する(第1図(f))。第1の保護膜10の
一部分を除去して、窓11を形成した後、装置全体を水
素を含まない非酸化性の200〜450℃程度の雰囲気
に1〜20時間晒し、半導体装直向に含まれる水素(l
()を窓11から外部へと拡散させる(第1図(g))
。さらに、P−3iNよりなる第2の保護膜12を堆積
した後、外部引き出し部(バンド部)のみ第2の保護膜
12を除去する(第1図(h))。
FIG. 1 +al~(hl is a cross-sectional view in the order of steps of the method of manufacturing a semiconductor device according to the present invention. A gate oxide film 2 is provided on the surface of a P-type semiconductor substrate 1 (FIG. 1(a)). Usually polysilicon A gate electrode 3 made of the following is provided on a part of the gate oxide film 2 (FIG. 1(b)). Using the gate electrode 3 as a mask, an N-type source region 4 and a drain region 5 are formed by ion implantation or the like ( Figure 1(C)).Gate electrode 3
and an interlayer insulating film 6 covering the gate oxide film 2 (first
Figure (d)). Gate oxide film 2 and interlayer insulating film 6 are removed from part of source region 4 and drain region 5, and interlayer insulating film 6 is removed from part of gate electrode 3.
After removing and forming contact holes, desired regions are connected using metal wiring 9 such as aluminum (FIG. 1(e)). A first protective film 10 made of P-3iN is deposited on the entire surface (FIG. 1(f)). After removing a portion of the first protective film 10 to form the window 11, the entire device is exposed to a non-oxidizing hydrogen-free atmosphere of about 200 to 450° C. for 1 to 20 hours, and the semiconductor device is directly exposed. Contained hydrogen (l
() to the outside from the window 11 (Figure 1 (g))
. Further, after depositing the second protective film 12 made of P-3iN, the second protective film 12 is removed only at the external extension portion (band portion) (FIG. 1(h)).

前述の実施例では第2の保護膜としてP−3iNliを
用いたが、第2の保護膜としてはアルミニウム等の金属
膜でもよい。
In the above embodiment, P-3iNli was used as the second protective film, but the second protective film may also be a metal film such as aluminum.

また、半導体素子としてNチャネル型のMOSトランジ
スタについて述べたが、本発明はPチャネル型のMOS
)ランジスタに対しても全く同様に用いることができる
Furthermore, although an N-channel type MOS transistor has been described as a semiconductor element, the present invention is a P-channel type MOS transistor.
) It can be used in exactly the same way for transistors.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明によれば、第1NのPSiN膜
に窓を開けて、MOS)ランジスタ内に含まれる水素を
外部へ拡散させることで、ホットエレクトロンによる特
性の劣化を、PSG等のリンガラスを保護膜に用いた場
合と同程度にまで抑制することのできる効果を有する。
As described above, according to the present invention, by opening a window in the 1N PSiN film and diffusing the hydrogen contained in the MOS transistor to the outside, deterioration of characteristics due to hot electrons can be suppressed. This has an effect that can be suppressed to the same extent as when glass is used as a protective film.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(al〜thlは本発明の実施例を示す半導体装
置の製造方法の工程順断面図、第2図(al〜(flは
従来の半導体装置の製造方法の工程順断面図である。 1.51・ 2.52 3、53・ 4.54・ 5.55・ 6 56・ 9I 59・ 60・ ・ ・ P型半導体基板 ゲート酸化膜 ゲート電極 ソース領域 ドレイン領域 層間絶縁膜 金属配線 保護膜 以上 出願人 セイコー電子工業株式会社 代理人 弁理士  林   敬 之 助(b) (C) 話 (d)             (/l)半導イ本装
に/)HaI:程ノ119断面図第1図 (d) 従来の+導体装置の警伍1稚111θ@面口第 2 図
FIG. 1 (al to thl are step-by-step cross-sectional views of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 (al to (fl) are step-by-step cross-sectional views of a conventional method for manufacturing a semiconductor device. 1.51・ 2.52 3, 53・ 4.54・ 5.55・ 6 56・ 9I 59・ 60・ ・ P-type semiconductor substrate Gate oxide film Gate electrode Source region Drain region Interlayer insulating film Metal wiring protective film Applicant: Seiko Electronic Industries Co., Ltd. Agent Patent Attorney: Keisuke Hayashi (b) (C) Story (d) (/l) Semiconductor in this book/) HaI: Hodono 119 cross-sectional view Figure 1 (d) Figure 2 of conventional + conductor device

Claims (4)

【特許請求の範囲】[Claims] (1)1導電型の半導体基板の表面にゲート酸化膜を設
ける工程と、前記ゲート酸化膜の一部分にゲート電極を
設ける工程と、前記ゲート電極の両側に逆導電型のソー
ス領域およびドレイン領域を設ける工程と、前記ゲート
電極および前記ゲート酸化膜を覆う層間絶縁膜を設ける
工程と、前記ゲート酸化膜および前記層間絶縁膜の一部
を除去してコンタクトホールを設けた後、金属配線をコ
ンタクトホールと所望の領域との間に設けるトランジス
タとする工程と、前記金属配線および前記層間絶縁膜と
を覆う第1の保護膜を設ける工程と、前記第1の保護膜
の一部を除去して窓を設ける工程と、前記窓を通して前
記トランジスタ内の水素を外方拡散させる工程と、前記
第1の保護膜および前記窓を覆う第2の保護膜を設ける
工程とからなる半導体装置の製造方法。
(1) A step of providing a gate oxide film on the surface of a semiconductor substrate of one conductivity type, a step of providing a gate electrode on a part of the gate oxide film, and a step of providing a source region and a drain region of opposite conductivity type on both sides of the gate electrode. a step of providing an interlayer insulating film covering the gate electrode and the gate oxide film; and a step of forming a contact hole by removing a part of the gate oxide film and the interlayer insulating film, and then inserting the metal wiring into the contact hole. and a desired region, a step of providing a first protective film covering the metal wiring and the interlayer insulating film, and a step of removing a portion of the first protective film to form a window. A method for manufacturing a semiconductor device comprising the steps of: providing a second protective film covering the first protective film and the window; diffusing hydrogen in the transistor outward through the window; and providing a second protective film covering the first protective film and the window.
(2)前記第1の保護膜および前記第2の保護膜とはプ
ラズマを利用した化学的気相成長法により形成される窒
化膜であることを特徴とする請求項(1)記載の半導体
装置の製造方法。
(2) The semiconductor device according to claim (1), wherein the first protective film and the second protective film are nitride films formed by chemical vapor deposition using plasma. manufacturing method.
(3)前記第2の保護膜はアルミニウム等の金属薄膜で
あることを特徴とする請求項(1)記載の半導体装置の
製造方法。
(3) The method for manufacturing a semiconductor device according to claim (1), wherein the second protective film is a thin film of metal such as aluminum.
(4)前記窓を通して前記トランジスタ内の水素を外方
拡散させる工程は、200〜450℃程度の加熱である
ことを特徴とする請求項(1)記載の半導体装置の製造
方法。
(4) The method of manufacturing a semiconductor device according to claim (1), wherein the step of outwardly diffusing hydrogen in the transistor through the window involves heating at about 200 to 450°C.
JP8295489A 1989-03-31 1989-03-31 Manufacture of semiconductor device Pending JPH02260640A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8295489A JPH02260640A (en) 1989-03-31 1989-03-31 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8295489A JPH02260640A (en) 1989-03-31 1989-03-31 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02260640A true JPH02260640A (en) 1990-10-23

Family

ID=13788616

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8295489A Pending JPH02260640A (en) 1989-03-31 1989-03-31 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02260640A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6608353B2 (en) 1992-12-09 2003-08-19 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor having pixel electrode connected to a laminate structure

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6608353B2 (en) 1992-12-09 2003-08-19 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor having pixel electrode connected to a laminate structure
US7045399B2 (en) 1992-12-09 2006-05-16 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US7061016B2 (en) 1992-12-09 2006-06-13 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US7105898B2 (en) 1992-12-09 2006-09-12 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US7547916B2 (en) 1992-12-09 2009-06-16 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US7897972B2 (en) 1992-12-09 2011-03-01 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US8294152B2 (en) 1992-12-09 2012-10-23 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit including pixel electrode comprising conductive film

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