JPH02266457A - Method for controlling execution of processing - Google Patents

Abstract

PURPOSE:To continuously execute interrupted processing independently of the sort and state of the processing by allowing a normal processor receiving the information of fault generation when the fault is generated in one of plural processors to temporarily form a virtual processor and allowing the virtual processor to continuously execute the processing executed by the defective processor. CONSTITUTION:If a fault is generated in an instruction a3(71) during the execution of processing A40 based upon a processor 10, the processor 10 informs the fact of the fault generation to a normal processor 20. At that time, the processor 20 suspends the execution of the executing processing B, extracts (83) the state information of the processor (IP0) 10 and forms a virtual processor 23 by means of virtual processor execution controlling/supporting processing (60). The residual part (instruction a4(74) etc.) of the processing A including the instruction a3(71) not executed by the virtual IP execution processing (70) is executed by the formed virtual processor 23. Consequently, substitutive recovery (continuous execution) processing can be executed.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention is a multiprocessor system in which a plurality of processing units share a main storage device, in which one processing unit is unable to execute processing due to a failure or the like. If you cannot continue,
The present invention relates to a process execution control method that provides a method for allowing a process being executed on a processing device to be normally executed continuously regardless of the type of process or the process state.

[Conventional technology]

In recent years, computer systems have become widespread, various online systems, VANs, etc. have become more sophisticated, and there is an increasing demand for systems with high reliability. Furthermore, in order to meet the increasing demand for computer system performance, computer systems are becoming increasingly multiprocessor-based. In a multiprocessor in which multiple processing units share the main memory (referred to as a tightly coupled multiprocessor), even if one of the multiple processing units that make up the system fails, other normal processing units will be able to recover. By taking over the processing that was interrupted due to a failure, it is possible to continue processing as a whole system. Regarding this method, several techniques have been proposed in the past (Japanese Patent Publication No. 47-36181, Japanese Patent Publication No. 61-56537, Japanese Patent Application Laid-Open No. 58-5856, Japanese Patent Application No. 62-29565). etc.).

In conventional technology, information such as the state of the failed processing device at the time of failure and the logical unit number of the failed processing device is transferred to the failed processing device, normal processing device, or recovery control device. The information is stored in a storage device or directly transferred to a normal processing device, and the normal processing device uses that information to take over and re-execute the process that was interrupted on the faulty processing device. This is what I do. However, in either case, the recovery of processing based on the notified or obtained information is temporary, and only one operation of the processing that was being executed at the time of the failure, such as one instruction or interrupt processing, etc. The purpose was to re-run the program and complete it normally.

On the other hand, the conventional virtual computer method (Japanese Patent Laid-Open No. 57-21268
(e.g., Publication No. 0), the purpose is to use the entire system as a virtual computer system, and does not consider simultaneous operation with processing of the real computer state, dynamic transition between the real computer state, etc. do not have.

[Problem to be solved by the invention]

In conventional technology, another normal processing device takes over and re-executes one operation, such as one instruction or interrupt processing, that was being executed by the processing device at the time when processing execution was interrupted due to a failure or the like. It is possible to terminate the process normally, but if you look at the process that was being executed as a whole process flow related to the process that was being executed on other processing devices, for example, waiting for a clock (waiting until a clock is available) ) processing, etc., there may be cases where the interrupted processing due to a failure or the like cannot be continued and replaced by another normal processing device. In other words, the method for continuing the process is as follows:
(1) With regard to processing that has been interrupted due to the occurrence of a failure, etc., a method for recovering by taking over only one interrupted instruction or one interrupted operation, regardless of the state of the processing, and (2) ) Restarts the interrupted process from the interrupted instruction, taking over not only the interrupted instruction but also a series of subsequent instructions that cannot be interrupted, making it possible to interrupt the process other than when waiting for a lock or securing a lock. There is a method of executing the process until a specific state is reached, but with either of these methods, it is impossible with the prior art to continue executing the process normally in all cases.

Using Figures 2 and 3, method (1) shows that there is no problem in the case of Figure 2, but a problem occurs in the case of Figure 3.
It will be explained that method (2) causes no problem in the case shown in FIG. 3, but a problem occurs in the case shown in FIG.

FIG. 2 is an explanatory diagram showing the flow of processing in two processing devices (IPs). In the figure, 201 and 206 indicate the normal instruction processing of the processing unit (IPO or IPI).
207 is lock AI +1! The fact of success is that 202 is lock A6! 208 indicates the sequence of command processing with lock A secured, 203 indicates the state of waiting for lock A, 210 indicates the state of waiting for lock A, which took over 203, and 204 indicates the occurrence of a failure, etc. Indicates the fact that processing execution has been interrupted. Further, 205 indicates that the IPI has been notified of the fact that the IPO processing execution has been interrupted, and 209 indicates the point in time when the fact has been acknowledged. Figure 2 shows that IPI first secures lock A on a certain area of the main memory.207
), so next time after IPO fails to secure lock A on this same storage area (202, 203)
, processing execution is interrupted due to a failure in IPO, etc. (204')
This shows the case where this occurs. The fact that this processing execution interruption has occurred is notified to IP1 immediately after the occurrence (205
). Now, considering method (1) above, IPO
The IPI process that re-executes (210) the process that was interrupted (wait for lock A 203) only takes over and re-executes one instruction or process that was interrupted, and only if they finish normally. In this case, if the original processing of IP1 (208) is continued, processing (20
After 8) releases lock A, the process (203) that was interrupted by IPO can be continued. However, in method (2) above, if a state other than the lock wait state is considered as a specific state that can be interrupted (for example, when a series of several instruction processes that cannot be separated from each other are completed), the IPI The re-executed process (lock wait 203) does not end and becomes a self-locking state in which the lock wait state continues indefinitely, so the system function stops.

FIG. 3 is also an explanatory diagram showing the flow of processing in two processing devices (IP). In the figure, 301.306
indicates the normal instruction processing of the processing unit (IPO or IPI), 302 indicates the fact that lock A was successfully secured, 307 indicates the fact that lock AltI was not retained, 311 indicates the fact that lock A was released, and 303.310 indicates the fact that lock A was successfully secured. 308 indicates the state of waiting for lock A, and 1.304 indicates the fact that processing execution has been interrupted due to occurrence of a failure or the like. Also, 30
5 indicates that the IPI has been notified of the interruption of IPO processing execution, and 309 indicates the point in time when this fact has been acknowledged. In FIG. 3, IPO first secures lock 8 for a certain area of the main memory (302), and then, after IPI fails to secure lock A for the same storage area (302),
307, 308) Processing execution is interrupted due to a failure in IPO (
304) has occurred. The fact that this process execution interruption has occurred is notified to the IPI immediately after the occurrence (
305). Now, considering the method (1) above, the IPI process (310) that re-executes the process (303) that was interrupted in IPO is a series of processes (303).
If only one of the interrupted instructions or one process is re-executed, and if they finish normally, the original process of IP1 (308) is continued, as shown below. Even if IPI takes over one instruction, it does not mean that all of IPO's original processing (303) has been completed, so the possibility that IPO will release lock A during the execution of taking over is extremely low, and IP1's lock waiting process (303) is not completed. 308") does not end, the system becomes stuck in a self-locked state where it continues to wait for a lock indefinitely, and system processing stops. However, with method (2) above,
Considering states other than the lock secured raw state as specific states that can be interrupted, the process re-executed in IP1 (31
0, which is a successor to the IPO process (303)) ends with the release of lock A (311), and then continues to execute the IP1 process (308) (for example,
For the area released by 311, rP1 can now retake lock A as its own processing and execute the original IPI processing.

In these two examples, the fact that processing execution has been interrupted in the IPO is immediately notified to the IPI regardless of the processing state of the IPI, but the processing state of the IPI is in the above-mentioned specific state (-paragraphed state). , e.g. input/output interrupts,
Also, an interrupt notification may be made when an external interrupt becomes possible. In this case, the same I
ll theory, it is impossible to continue executing all interrupted processes.

As described above, in the conventional technology, it is not possible to continue executing a process that has been interrupted due to a failure in all types of processes and situations.

Therefore, an object of the present invention is to continue executing this interrupted processing regardless of the type of processing or the situation.

[Means to solve the problem]

In order to overcome the above-mentioned problems, the present invention provides a method in which a normal processing device that has received a notification of processing execution suspension uses a value indicating the state of the processing device that interrupted processing execution at the time of interruption, that is, a program status word, a register value, Creating a virtual processing device, which is a component of a virtual computer system, using the timer value, and executing the interrupted process using the execution environment of this virtual processing device,
The processing that was originally executed in the processing device that received the notification is executed in a time-sharing manner.

[For production]

The operation of the above method will be explained.

When the state of the processing device that has suspended processing execution, i.e., the program status word, register value, and timer value, is notified to other normal processing devices, the normal processing device can execute a virtual computer by means of software, bird air, or both. Create a virtual processing device, which is a component of the system,
The contents of the status information of the processing device that interrupted execution of the notified process are set in the execution environment definition information, so that the continued execution of the interrupted process can be started. The created virtual processing device is executed as one job or task on a normal processing device.

Generally, with a virtual computer system, it is possible to create multiple virtual computers (virtual processing units) on -1 physical computers (actual processing units) and have each virtual computer run on a separate O8. can. In this case, physical (real)
As a computer, even though the processing of the instructions of the plurality of OSs and the processing of the virtual machine control program are executed in a time-sharing manner, when viewed as a logical (virtual) computer, each O8 It can be said that the processing of the instruction is executed in parallel with other O8 processing and virtual machine control program processing. The present invention focuses on a function in which the processing of instructions by such a virtual processing device is executed concurrently and in parallel with other processing, and it is possible to continue execution of interrupted processing, which is the problem of the above-mentioned conventional technology. (Preventing something from happening.)

That is, according to the present invention, no matter what state the process is in when it is interrupted due to a failure or the like, the virtual process created when the process execution is interrupted (regardless of the type of process or the process state) In the device, in parallel with the processing operation that the normal processing device that received the notification is originally performing, it is possible to take over and execute the processing that was interrupted due to the failure, and to continue executing (recovering) the interrupted processing. Such a logical simultaneous processing function may be realized by, for example, incorporating a method such as time division into a physical processing device having only one execution function, as described above.

Generally, there are two processing modes of a processing device: a supervisor mode in which all instructions can be executed, and a Brablem mode in which only some instructions can be executed. If the status is supervisor mode, 5PV (supervisor)
Both privileged instructions called commands and general instructions called FRB (Brablem) instructions can be used, but if the state is in Brablem mode, the SP ■ instruction cannot be used. Therefore, SPV instructions cannot be used when the virtual processing unit is executed in Brablem mode. In such cases, the virtual processing device (
(Virtual IP) Execution support processing performs simulation processing of SPv instructions to make it appear as if the instructions have been executed.

Further, as a feature of the present invention, such a virtual processing device temporarily performs <b' only when processing execution is interrupted.
Continued execution (recovery) of a process that was created (at the time) and was interrupted
It disappears once processing is complete.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

This embodiment mainly shows a method for solving the problem in the case of FIG. 2 using method (2) above. For details of the instructions, interrupts, etc. in this embodiment, please refer to the Hitachi Manual 1M Series Processing Device, etc. In this embodiment, the fact that the processing device has a failure or the like and the execution of the process is interrupted is called an interrupt. The execution of the virtual processing device shall be reported to the normal processing device by For example, when both input/output interrupts and external interrupts become possible, the process ends. The reason for this is that the process generally does not allow interruption in the middle of execution;
For example, processes that cause infinite loops, interrupt-disabled waits, deadlocks, etc.) run in a state where external interrupts and input/output interrupts are disabled to prevent interruptions due to external interrupts, input/output interrupts, etc., and to prevent CPU changes. . Therefore, conversely, if a process allows interrupts, it can be considered as an indicator that no inconvenience will occur even if the process is interrupted, whereas if a process allows interrupts, it will cause inconvenience to the entire process. It becomes possible to temporarily interrupt the process without any trouble and re-execute it later on another processing device. In other words, after finishing execution of the processing on the virtual processing device, it is possible to restart all the processing with one fewer processing device from which the faulty processing device has been disconnected. In this embodiment, a point in time when the process becomes capable of input/output interrupts and external interrupts is considered as a case where the process can be interrupted without causing any inconvenience to the flow of the process.

FIG. 1(a) is a block diagram schematically showing the configuration of a multiprocessor system to which an embodiment of the execution control method of the present invention is applied.

Figure 1 (Al Niote, 10 is the processing device lPO520
is a processing device IPI, and 30 is a main storage device (area shared by processing devices 10, 20, . . . ). Processing device (10,
20) has an instruction execution unit (11, 21), the execution state of which is indicated by a program status word (12, 22). The program status word also indicates the address of the instruction being executed.

Further, on the main storage device, an information storage area 31 and processes 32 to 35 executed by the processing device are placed.

Note that these plurality of processing devices 10, 20, . . . (two in this embodiment) are accessed by a coexisting storage device 30 by a system controller (not shown).

An overview of the operation will be explained with reference to FIG. 1 (al).

First, the instruction execution unit 11 in the processing device (IPO) 10 executes the process A (4) stored on the main storage device 30.
0) (consisting of instruction aH41), instruction a2 (42), etc.), and the instruction execution unit 21 in the processing device (IPI) 20 executes the process B (50 )(
Instruction b1 (51), instruction b2 (52), instruction b3 (53
), etc.) are being executed. If a failure occurs in the instruction a3 (71) while the processing device 10 is executing the process A40, the processing device 1o saves (stores) its own status information in the area 31 on the main storage device 30 (81). ), the fact that a failure has occurred is notified to the normal processing device 20 (
contact) (82). This evacuation and notification are performed by a processing device or a recovery control device (not shown).

Therefore, upon receiving the notification, the processing device 20 suspends the execution of the process B that is currently being executed, and this suspended state (
The instruction b2 (executed up to 52) is saved (stored) (this saving of the interrupted state is not shown). Next, the processing device (IP
The state information of the ONO is extracted 83), and the virtual processing device 23 is extracted by the virtual processing device execution control/support processing (60).
Create. Then, the remaining part of process A (instruction a4 (72), etc.), including the instruction a3 (71) that could not be executed, is executed by the virtual IP execution process (70) using the created virtual processing device 23. .

FIG. 1 (Fig. 1) is an explanatory diagram showing the flow of operation of an embodiment of the virtualization method according to the present invention. The operation of this embodiment will be explained in more detail with reference to FIG. 1(b).

In the figure, 101 and 102 are processing devices (IP) 0
104 indicates a report of the fact of a failure, and 103 to 119 are all processing devices (IP)
1 shows the processing executed in 1. In addition, the dotted line portions indicate processes related to the execution of the virtual processing device, 121 is a control process for the execution of the virtual processing device (hereinafter referred to as virtual IP execution control process), and 122 is the execution of the virtual processing device (hereinafter referred to as virtual IP execution control process). (hereinafter referred to as virtual IP execution), and 123 indicates processing that supports execution of the virtual processing device (hereinafter referred to as virtual IP execution support processing).

A series of processes A is currently being executed in the processing device IPO (
101), and instruction a is being executed in process A (102
) has a failure (marked with an x).

Further, in the normal processing device IPI, processing B is being executed (103). In this example, it is impossible to interrupt process A without causing inconvenience to the flow of processing at the time of failure (hereinafter simply referred to as uninterruptible), and process B causes inconvenience to the flow of processing. (hereinafter referred to simply as "interruptible"). The fact that a failure has occurred in IPO is reported to IPI by an interrupt during execution of process B (104). After receiving the failure report, the IPI performs a process to interrupt process B (105). Next, (12
1) Preparation processing for virtual IP execution (creation of an environment for virtual IP reality) is performed (106).

Details of this preparation process will be described later. Once the virtual IP execution is ready, the virtual IP execution time is determined and the virtual IP execution begins (122). In the execution of the virtual IP, first, the instruction a, which is being executed at the time of the failure occurrence and has not yet been completed, is executed (107).

After that, the continuation of process A continues to be executed (108)
.

During the execution of process A, an instruction b that cannot be directly executed in virtual IP execution (for example, as mentioned above, when virtual IP execution is in programm mode, if the instruction is an SPv instruction, it cannot be directly executed). If the command is executed (109), the virtual IP execution support process is activated (123) and performs a simulation process of the command (110'').As a result, from the IPI's perspective, it is confirmed that the command has been executed. An example of an instruction that cannot be directly executed in virtual IP execution is the 5ICP instruction (SIGNAL PROCE).
SSOR command. A type of supervisor command SP■, IP
When the simulation of the command is completed, processing A continues to be executed again (111).The virtual IP execution time is set to a certain value in advance. (106), and when the set time elapses, the execution of the virtual IP is temporarily suspended (121, 112'').This suspended state is
Like other tasks, it is temporarily saved and saved for time-sharing processing, and control is passed to the dispatcher (113
). The dispatcher may dispatch any process, but in this example, it will dispatch process B that IP1 was previously performing (114'').Process B
is executed for a preset time, and control is passed to the dispatcher again (115). Next, the dispatcher resumes virtual IP execution (116, 1
21). First, virtual IP execution control processing is performed, and time for virtual IP execution is set. Continue processing A
is continuously executed (117). In the execution of this process A, for example, the LPSW command (LOAD PROG
RAM 5TATUS WORD (program status word) command. The program state word defines the state of the processor when the program is executed. Whether or not to allow interrupts, SP■,
If the processing state of Process A is changed by a command that changes the processing state (indicating FRB mode distinction) and becomes interruptible, then Process A will be interrupted at that point and control will not be transferred to the virtual IP execution control process. cross (118). Judging whether a state can be interrupted is tentatively determined because in software, commands to change the processing state are possible only in supervisor mode.
It is possible to perform ff1iP execution in Brablem mode, or it is also possible to use a hardware function that detects a specific instruction and similarly puts its execution into an interruptible state. In virtual IP execution control, the interrupted state of process A is saved so that it can be executed directly on the processing device IPI instead of on the virtual IP, the virtual IP execution is ended, and control is passed to the dispatcher (119).

FIG. 4 shows an example of a processing device control table that defines the environment for virtual IP execution. In the figure, 401 is the main storage, 402 is a storage area commonly used by each processing device, and 403a and 403b are storage areas used exclusively by each processing device (for example, a fixed save area PS).
A). The latter uses address conversion called brifix conversion (a method of address conversion that realizes multiprocessors) for each processing unit to convert the 0
It is mapped to the area starting from the address. For details on brifix conversion, please refer to, for example, the Hitachi manual [M series processing equipment]. In the figure, 404 is a processing device control table that defines the environment for virtual IP execution;
Reference numeral 5 denotes a fault state information storage area in which the fault processing device stores information at the time of fault occurrence. In this area 405,
Stored are the program status word at the time of failure, various timer values, values of all registers, and information for specifying the location of failure. Note that the main storage device 30 in FIG. 1(a) corresponds to the common storage area 402 in FIG.
The storage section of the virtual processing device 21 corresponds to area 405 in the figure, and almost corresponds to 404 in FIG. Areas 403a and 403b in FIG. 4 are omitted in FIG. 1(a).

The processing device control table 404 is created by copying the program status word, various timer values, and all register values from this information, and further storing the number of the processing device in which the failure has occurred. The above-mentioned virtual [P execution support processing 123]
refers to this processing unit control file 404 and performs instruction simulation for virtual IP execution. Details of the virtual IP execution support process will be described later. Furthermore, the virtual IP
When execution is interrupted due to instruction simulation, because a set time has elapsed, or because it has become possible to interrupt, the status information is temporarily stored in this processing unit control table, and the execution can be restarted using virtual IP execution, or Used for execution in real computer state.

FIGS. 5 to 8 are flowcharts of the process of executing the virtual RP. FIG. 5 shows virtual IP execution preparation processing 500 performed by a normal processing device that has received notification of a failure. This process 5
00 corresponds to 105 in FIG.

In the figure, 501 to 504 are descriptions of processing contents, and 505
is a connector for processing flow description. The processing device that receives the notification of the occurrence of a failure by an interrupt (501) stores the execution state of the process (task) that was being executed up to that point in the task table so that it can be continued (502). Next, read the status information of the failed IP from the storage area stored by the failed IP (503).
, and store it in the processing device control table (504), and prepare for virtual IP execution. After completing the above process, the virtual I
Transfer control to P execution control processing.

FIGS. 6(a) and 6(b) show virtual RP execution control processing 600.
610 is a flowchart. This process corresponds to FIG. 1 106. In the figure, 601, 602, and 604 are descriptions of processing contents, and 505, 603, and 802 are connectors. The virtual IP execution control process generates a timer interrupt when the virtual IP execution exceeds the set time, and
In order to pass control to the P execution support process, set the time for virtual IP execution and set that value in the timer (6
01). Then, virtual IP processing using virtual IP execution is started (602). Process 604 will be described after FIG.

FIG. 7 is an explanatory diagram of processing 700 in virtual IP execution. In the figure, 701, 702, and 703 are descriptions of processing contents, and 603 and 704 are connectors. usually,
These processes are performed by hardware.

Process 701 is an instruction fetch. Processing 702 is a part that determines whether the fetched instruction can be executed in virtual IP execution or not. As mentioned earlier, when virtual rP execution is set to programm mode, it is determined whether the fetched instruction is executable only in supervisor mode. The instruction becomes an instruction that cannot be executed by virtual IP execution. In addition, for example, the prior art (Japanese Patent Application Laid-Open No. 57-212680
Lord! ! It is also possible to use special execution modes controlled by hardware or microprograms, as shown below. Process 703 is instruction execution.

701 to 703 while the instruction can be executed by virtual IP execution.
The process is repeated and the process progresses. If an instruction that cannot be executed by virtual IP execution appears, control is passed to virtual IP execution support processing.

FIG. 8 is an explanatory diagram showing a flow 800 of virtual IP execution support processing. This process corresponds to FIG. 1 123. In the figure, 801, 803, 804, and 805 are descriptions of processing contents, and 704, 802, and 603 are connectors. This provisional 9J! , virtual IP is used for IP execution support processing.
If an instruction that cannot be directly executed in P execution appears, control is transferred when the time set for virtual IP execution has elapsed. In this process, it is first determined whether or not the timer has ended (801), and if the timer has ended, control is passed to the virtual IP execution control process. If the timer has not ended, the instruction being executed is simulated (803), and as a result, it is determined whether or not it can be interrupted (804).
. If interruption is not possible, start virtual IP execution again. If it becomes possible to interrupt the process, the status of the process being executed by virtual IP execution can be stored in the task table that controls execution in the real computer state, so there is no need to continue virtual IP execution (, In order to finish this, the status of the process being executed by virtual IP execution is stored in the task table, and
P execution is ended (805'). When the timer expires, execution of the virtual IP is suspended and control is passed to the dispatcher to execute other tasks. Thereafter, the processing status of the virtual IP execution control process is stored in the task table so that the virtual IP can be re-executed (604).

So far, an embodiment has been described that enables virtual IP execution mainly by software. In addition to the method described above, the virtual IP may be executed using dedicated hardware or the like. At that time, the processing order of the virtual IP execution support processing and the like may be slightly different.

〔Effect of the invention〕

As explained in detail above, in the multiprocessor system of the present invention, when a failure occurs in one of the multiple processing units, the normal processing unit that has received notification of the failure temporarily creates a virtual processing unit to create a virtual processing unit. Since the virtual processing device is configured to take over and execute the processing that was being executed by the faulty processing device, this virtual processing device can perform the processing that should normally be performed by the above normal processing device and take over from the faulty processing device. As a result, no matter what state the process being executed at the time of failure is (even if it is waiting for a lock), the inconvenience will not occur. This has excellent effects, such as being able to execute the recovery (continuation execution) processing on behalf of the user without causing any situations such as system failure or system outage.

[Brief explanation of drawings]

FIG. 1(a) is a block diagram showing an overview of the configuration of a multiprocessor system to which an embodiment of the processing execution control method of the present invention is applied; Explanatory diagram showing the flow of operation of the embodiment, second
3 and 3 are explanatory diagrams of processing operations for explaining the problems to be solved by the present invention, and FIG. 4 is an explanatory diagram of an embodiment of a processing device control table that defines an environment for virtual IP execution. 5, FIGS. 6(a) and 6(b), FIG. 7, and FIG. 8 are flowcharts of each process for executing the virtual IP. [Explanation of symbols] 10, 20--Processing device (IP), 23--Virtual IP, 30--Main storage device, 31--IP status information, 101, 102--Fault Processing at the occurrence IP, 103-119... Processing at the IP that executes virtual IP, 114... Notification of failure occurrence, 121...
・Virtual IP execution control processing, 122...Virtual IP execution,
123...Virtual IP execution support processing, 201, 206
, 301 , 306...Normal processing in IP, 2
08, 303, 310... Processing while securing lock A, 203°210, 308... Lock A waiting state,
204, 304... Failure occurrence, 404... Processing device control table, 405... Failure state information storage area,
501-504, 601, 602. 604, 701-703, 801, 803-80
5...Description of virtual IP execution processing contents Agent Patent attorney Kenjibu 2 (1 other person) ;MU) to Fig. 4 Fig. f

Claims (1)

[Claims] 1. A plurality of processing devices, a main storage device shared by the plurality of processing devices, and when it becomes impossible to continue executing the process being executed in one of the processing devices. , and means for notifying at least one of the other operating processing devices of this fact, the processing device that has received the notification is the one that is unable to continue executing the processing. 1. A method for controlling execution of a process, characterized in that a value representing a state at the time of interruption of the execution of the process is used to continue executing the process whose execution has been interrupted in a processing device that has become unable to continue executing the process. 2. A virtual processing device that is a component of a virtual computer system is used when continuing the processing using the value representing the state of the processing device at the time of interruption of the processing execution. Execution control method for processing. 3. When using a virtual processing device that is a component of the virtual computer system, the process of generating the virtual processing device that is a component of the virtual computer system and controlling its execution is one of the steps in normal calculation processing. 3. The process execution control method according to claim 1, wherein the method is executed as a process. 4. When using a virtual processing device that is a component of the virtual computer system, the process of generating the virtual processing device that is a component of the virtual computer system and controlling its execution requires continuous execution of the process. 4. The process execution control method according to claim 3, wherein the process is executed only for a certain period of time. 5. The process execution control method according to claim 1, wherein the execution time of the continuously executed process is set by a timer. 6. In the continued execution of the process, the processing device that received the notification temporarily suspends the process it was executing, and performs the process that should be continued by the virtual processing device and continues execution on the processing device that received the notification. 3. The process execution control method according to claim 1, wherein the process is executed in a time-sharing manner. 7. In the continued execution of processing by the virtual processing device,
3. The process execution control method according to claim 1, wherein when an instruction that cannot be directly executed is issued, a simulation process of the instruction is performed. 8. Execution of the process according to claim 1 or 2, characterized in that when the process to be performed by the failed processing device that is continuously executed on the virtual processing device is completed, the virtual processing device is canceled. Control method.