JPH02251992A - Liquid crystal display panel and its manufacture - Google Patents

Abstract

PURPOSE:To easily inspect TFTs on an active matrix array by connecting a driving IC to a source signal line to which a switching element is connected through a conductive joint layer. CONSTITUTION:The liquid crystal display panel has thin film transistors(TFT) TM11 - TM34 and TS11 - TS44 for picture element driving and a scanning circuit 19 on a polysilicon substrate 11. The scanning circuit 19 is put in operation to apply an optional gate signal line 15 with a voltage which operates the TFTs or a voltage which does not operate the TFTs. Therefore, a probe is pressed against all gate signal lines 15 at a time to obtain effect similar t that at the time of signal application. Further, a source IC 14 is mounted after the liquid crystal display panel is inspected, so the impedance of a source IC 14 need not be considered at the time of inspection and secure and stable inspection is therefore performed. Consequently, the manufacture yield is improved and it is easily decided fast whether or not the liquid crystal display panel is normal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a liquid crystal display panel used in an active matrix liquid crystal display device and a method for manufacturing the same.

Conventional technology In recent years, as the number of picture elements in liquid crystal display devices has increased, the number of scanning lines has increased, and the display contrast and response speed of the conventionally used simple matrix type liquid crystal display devices have decreased. Active matrix type liquid crystal display devices in which elements are arranged are being used. However, the active matrix array used in the liquid crystal display device has tens of thousands or more thin film transistors (hereinafter referred to as TP).
(referred to as T). Therefore, it is difficult to fabricate all active matrix arrays without defects, and with the current technology, it is necessary to inspect TPTs formed on active matrix arrays to determine whether they are good or bad. Therefore, there has been a need for a liquid crystal display panel that can easily inspect TPT on an active matrix array and a method for manufacturing the same.

Hereinafter, a conventional liquid crystal display panel will be explained with reference to the drawings. FIG. 9(a) is a plan view of a conventional liquid crystal display panel. Also, FIG. 9(b) shows the EE′ of FIG. 9(a).
FIG. Note that parts unnecessary for the explanation have been omitted, and some parts have been enlarged or exaggerated to make the explanation easier.

Furthermore, the number of signal lines and the number of ICs of the liquid crystal display panel are drawn very small to facilitate drawing.

The above also applies to the following drawings.

In FIGS. 9(a) and 9(b), 90 is a liquid crystal, 91 is a substrate made of soda glass, 92 is a substrate on which a counter electrode is formed (hereinafter referred to as a counter substrate), 93 is a gate signal line, 9
Reference numeral 4 indicates a source signal line; 95 indicates a connection electrode forming portion formed on the substrate 91 for connection with the flexible substrate 96; and 96
is a substrate 97 on which a gate or source signal line and an IC are mounted.
97 is a printed circuit board (hereinafter referred to as an IC board) on which a scanning IC 98 or a source IC 99 is mounted;
8 is an IC (hereinafter referred to as a scanning IC) for applying a signal to the gate signal line 93 of the liquid crystal display panel, and 99 is an IC for applying a signal to the source signal line 94 of the liquid crystal display panel.
C (hereinafter referred to as source IC), 100 is a resin for sealing the liquid crystal 90 between the substrate 91 and the counter substrate 92 (hereinafter referred to as
(called sealing resin). Hereinafter, items with the same number or symbol have the same configuration or content. FIG. 10 is a partial equivalent circuit diagram of a TFT group formed on the panel 91 and facing the liquid crystal. 1st
In Figure 0, Tl1%T44 is a TFT, St~S4 is a source signal line, Gl''Ga is a gate signal line, and pH~
P44 is a picture element electrode. Further, FIG. 11 is a partially enlarged plan view of the connection electrode forming portion 95. In Figure 11, 1
10 is a connection electrode.

As is clear from FIGS. 9 to 11, a conventional liquid crystal panel has a TFT group and connection electrodes formed on a glass substrate 91, and a counter substrate is attached to form a panel. An IC for applying a signal to the panel is mounted on an IC board 97 by soldering, and the board and the panel are connected using a flexible board 96. An anisotropic conductive film is used to connect the flexible substrate 96, and the flexible substrate 96 and the connection electrode and the flexible substrate 96 and the lead wire 101 are connected by thermocompression bonding.

A conventional method for manufacturing a liquid crystal display panel will be described below. FIG. 12(a) shows a plan view of the substrate after the array formation process. 12(a) is a sectional view taken along the line FF' of FIG. 12(a). In FIGS. 12(a) and 12(b), 120 is a TFT group forming section (hereinafter referred to as a display area) shown in FIG. First, in the array forming process, a metal thin film, an amorphous silicon thin film, etc. are layered on soda glass, and the display area 120 and signal lines 93 and 94 are formed.
and a connection electrode 110 is formed.

FIG. 13(a) shows a plan view of the substrate after the panel forming process. 13(c) is a sectional view taken along the line CG' in FIG. 13(a). After the array forming process, the substrate is sent to a panel forming process. In this step, the counter substrate 9 is placed on the display area.
2 is attached, the peripheral part is sealed with sealing resin, and the liquid crystal 90
is injected. After the process is completed, non-defective products are sent to the next inspection process. FIG. 14 is an explanatory diagram of the inspection process. In FIG. 14, 140 is a gate signal line G and a source signal line S3.
141 is a resistance value measuring means, PS, ~PS, and PC, -PC4 is a connecting means such as a probe (hereinafter referred to as a probe), SS, ~S S a and SG+-3G4
is a selection means (hereinafter referred to as a switch) consisting of a relay or an analog switch. The main purpose of the inspection process is to detect cross-shorts, which can be serious display defects. Therefore, in this process, the probe PG+~P
G4 is the gate signal line of the liquid crystal display panel.
Then, the probes PS+ to PS are pressed against the source signal line. Usually, a liquid crystal display panel has 200 or more signal lines, so it is difficult to press a probe to all the signal lines at once. Therefore, the probes are attached to an XY stage and moved, and the probes are sequentially pressed against each other to perform the inspection. After the Bolob pressure contact, only the switch SSI is closed, and the switches SG1 to SG are closed in sequence, and the resistance value in each state is measured by the resistance value measuring means 141. Probes PG, ~PG are used to perform the above operations on all gate signal lines.

Do this by moving sequentially. Next, only the switch SS2 is closed, the switches sc and -sc are closed in the same manner, and the probes PC, to PG4 are moved. The resistance values between all gate signal lines and source signal lines are measured by sequentially closing and moving the switches SS to SS4 through the above operations. The measured resistance value is high if the intersection of the gate signal line and the source signal line is normal, and low resistance if there is a short circuit. In FIG. 14, since a cross short 140 has occurred, the resistance value becomes low when the switches SG and S S 3 are closed.

Items with cross shorts are discarded as defective. Next, the connection process will be explained. In the connection process, the IC
First, scan IC 98 or source IC 9 is placed on substrate 97.
9 etc. will be loaded. Next, an anisotropic conductive film is formed on the flexible substrate 96. Next, the flexible board 96
are positioned on the lead wire 101 of the IC board 97 and the connection electrode forming portion 95, and then thermocompression bonded and connected.

The liquid crystal display panel is completed through the above steps.

Problems to be Solved by the Invention In recent years, there has been a trend toward miniaturization of the signal line spacing of liquid crystal display panels to 200 μm or less. Furthermore, the number of signal lines is increasing to several hundred or more. Therefore, in the conventional liquid crystal display panel and its manufacturing method, the following serious problem occurs in the inspection process. During the inspection process of liquid crystal display panels, it is necessary to detect cross shorts, which can be a serious display defect, and to determine whether the liquid crystal display panel is good or bad. In addition, disconnections between the source and drain of TPT (hereinafter referred to as S-D oven) and short-circuits between the gate and drain (hereinafter referred to as S-D oven), which result in black dot-like display defects.
It is preferable to also detect TPT source-drain shorts (hereinafter referred to as S-D shorts) that result in white spot display defects (referred to as G-D sheets) and white dot-like display defects. In order to perform the above-mentioned inspection, it is necessary to press the probe to the extraction electrodes of the source signal line and gate signal line of the liquid crystal display panel to establish an electrical connection. However, there is a trend toward miniaturization of the lead-out electrodes of signal lines, and it is becoming difficult to accurately position the probe. Further, as the size becomes smaller, the positioning time also becomes longer. The number of signal lines on liquid crystal display panels is also increasing, and there is a limit to the number of probes that can be pressed at once, which increases the number of times the probe must be moved and requires longer inspection times. For example, even if the number of signal lines is 200X 400, the number of signal lines is 25X
Even if 25 probes are pressed at once and a 25 x 25 probe is inspected in 10 seconds, the inspection time will be about 20 minutes. In addition, point defects such as SD short, GD short, and SD oven defects can hardly be detected by conventional inspection processes, and are not normally performed. The above-mentioned point defects are inspected by display after the liquid crystal display panel is completely completed to determine whether the panel is good or bad. However, if a product turns out to be defective after it has been completed, the manufacturing cost will be significantly increased, which is a serious issue.

Means for Solving the Problems In order to solve the above problems, the liquid crystal display panel of the present invention includes:
A switching element for driving a picture element and a scanning circuit for applying a signal to a gate signal line connected to the switching element are formed on a polysilicon substrate, and a protruding electrode is formed on a source signal line connected to the switching element. The driving ICs are connected via a conductive bonding layer.

Further, in the method for manufacturing a liquid crystal display panel of the present invention, a switching element for driving picture elements and a scanning circuit are formed on a polysilicon substrate, a substrate on which a counter electrode is formed is mounted on the polysilicon substrate, and a liquid crystal display panel is provided between the substrates. In addition, the scanning circuit is operated and the inspection pad is used to perform the inspection process of the liquid crystal panel, and then the driving IC with protruding electrodes formed on the source signal line is conductive. The connection is made via a bonding layer.

Function: The liquid crystal display panel of the present invention has a TPT for driving picture elements and a scanning circuit formed on a polysilicon substrate. By operating the scanning circuit, a voltage that operates TPT (hereinafter referred to as on-voltage) or TPT is applied to any gate signal line.
It is possible to apply a voltage that does not cause the device to operate (hereinafter referred to as an off voltage). Therefore, the same effect as applying a signal by pressing the probe to all the gate signal lines at once can be obtained. Further, in the method for manufacturing a liquid crystal display panel of the present invention, the source IC is loaded after the liquid crystal display panel is inspected, so there is no need to consider the input impedance of the source IC during inspection. Therefore, reliable and stable inspection can be performed.

EXAMPLE Hereinafter, an example of the liquid crystal display panel of the present invention will be described with reference to the drawings. FIG. 1(a) is a plan view of the liquid crystal display panel of the present invention. In addition, Fig. 1(b) is a cross-sectional view taken along line AA' in Fig. 1(a), and Fig. 1(C) is a cross-sectional view taken along line AA' in Fig. 1(a).
It is a sectional view taken along the BB' line of a). Figure 1 (a) (b)
In (C), 10 is a liquid crystal, 11 is a semiconductor substrate made of polysilicon, etc., 12 is a counter substrate, and 13 is a portion where electrodes for testing the liquid crystal display panel are formed (
14 is a chip-shaped source IC 115 as a gate signal line; 16 is a source signal line;
7 and 18 are lead lines, 19 is a forming part of a scanning circuit for applying an on voltage or an off voltage to the gate signal line for scanning, and 20 is a sealing resin.

As is clear from FIGS. 1(a), 1(b), and 1(c), the liquid crystal display panel of the present invention has a TPT and a scanning circuit formed on a polysilicon substrate. Further, test electrodes corresponding to each signal line are formed around the display area, and a source IC 14 chip is connected to the source signal line by glass-on-chip technology (hereinafter referred to as COG technology). Furthermore, the liquid crystal display panel of the present invention will be explained using FIGS. 2 to 4. First, FIG. 2 is a partial equivalent circuit diagram of a display area portion in which a TPT is formed. In Figure 2, TM11-TM
34 and TSII to TS, , are TFTs. As is clear from FIG. 2, in the liquid crystal display panel of the present invention, two TPTs are formed in one picture element electrode, and the two TPTs are connected to different gate signal lines and source signal lines, respectively. . FIG. 3(a) is a partially enlarged plan view of the source IC 14 and the drawer vA 18 section. Figure 3(a)
Reference numeral 30 indicates an electrode (hereinafter referred to as an IC connection electrode) formed on the substrate 11 for connection to the terminal of the source IC 14 chip, and a dotted line 31 indicates the loading position of the source IC 14 chip.

As described above, the source IC 14 chip is connected to the source signal line of the liquid crystal display panel of the present invention via the IC connection electrode 30. FIG. 3(b) is a block diagram of the scanning circuit of the scanning circuit forming section 19. In FIG. 3(b),
32 is a shift register circuit; 33 is a latch circuit for latching and holding the logic output of the shift register circuit 32;
34 is a drive circuit that outputs an on voltage or an off voltage according to the logic output of the latch circuit 33, and 35 is an output terminal X.
. Note that the output current limiting circuit 35 can cancel or operate the input/output current limiting function by a logic input to the CL terminal. usually,
It is activated during the inspection process and deactivated during the display state. The shift register circuit 32 outputs an H or L level logical output depending on the clock φ and the data input to SP' or SPZ. The logic output is a latch circuit 33
is passed through or held in the latch circuit 33, and an on voltage or an off voltage is output from the drive circuit. Figure 4 shows
FIG. 3 is a partially enlarged plan view of the test electrode forming section 13. FIG. In FIG. 4, 41 is an inspection electrode. As is clear from FIG. 4, all source signal lines or gate signal lines have been led out up to the inspection electrode 41. The test electrodes 41 are pulled out one by one and connected to the scanning circuit forming section 19 or I
It is led to the C connection electrode 30. The inspection electrode 41
is formed at least on the source signal line.

Hereinafter, a method for manufacturing a liquid crystal display panel according to the present invention will be explained. FIG. 5(a) shows a plan view of the substrate 11 after the array formation process. Further, FIG. 5) is a sectional view taken along line CC' in FIG. 5(a). First, in the array forming step, TPTs, scanning circuits, etc. are formed on a polysilicon substrate using semiconductor technology.

Further, IC connection electrodes 30 and the like are also formed. After the array formation process, proceed to the panel formation process. FIG. 6(a) shows a plan view of the substrate after the panel forming process.

Moreover, FIG. 6 [present] is a sectional view taken along the line DD' of FIG. 6(a). In this step, the counter substrate 12 is attached on the display area in which TPT etc. are formed, and after the peripheral part is sealed with sealing resin, a vacuum is created between the substrates, and the liquid crystal 10
is injected. After the above steps are completed, non-defective products proceed to the next inspection step. FIG. 7 is an explanatory diagram of the liquid crystal display panel in the inspection process. In FIG. 7, the scanning 19 is only drawn on the left side of the drawing for ease of explanation. In Fig. 7, 70 is S-D short, 71 is G-D short, 74
is a cross short, 72 is a signal applying means capable of applying a DC voltage, 73 is a signal detecting means for detecting signals such as current, QS, ・QS is a probe, US, ・U
S is a switch. First, a method for detecting cross short 74 will be explained. The probes PS, ~PS, are pressed against a test electrode 41 formed at the end of the source signal line. Next, the scanning circuit 19 is operated and an off voltage is applied to all gate signal lines. Note that here, the off-voltage is treated as one voltage, and the on-voltage is treated as ten voltages. Next, the switches SS and SS are closed one by one, and the signal detection means 73 measures whether there is an output voltage or current in each state. Now, since the cross short circuit 74 has occurred, when the switch S33 is closed, the off voltage is detected by the means detection means 73.
detected. Therefore, it can be seen that the source signal line S and the gate signal line are short-circuited. Next switch SS
3 remains closed, an on-voltage is applied to the gate signal line G1, and the gate signal line G1 is sequentially shifted to the last gate signal line. The signal detection means 73 monitors whether there is any change in the off-voltage in each of the above states. Now, when an on voltage is applied to the gate signal line G3, the signal detected by the signal detection means 73 changes from an off voltage to an on voltage. Therefore, gate signal line G3
It is possible to detect that a cross short has occurred in the source signal S3. In addition, the output current limiting circuit 3 is connected to the scanning circuit 19.
5, even if a cross short occurs or a short occurs between adjacent gate signal lines, no overcurrent will flow, and the panel and scanning circuit can be stably operated without damaging the panel or scanning circuit. Tests can be performed.

Inspection can be performed by moving the probes PS, -PSs and performing the above operations on other source signal lines as well.

Next, a method for detecting the GD short 71 will be explained. First, the probes PS and -PS are pressed against the test electrode 41 formed at the end of the source signal line.

Next, the scanning circuit 19 is operated, and an on voltage is applied to the gate signal line Gl, and an off voltage is applied to the other gate signal lines. At that time, the selection means SS1 to SS5 are sequentially selectively closed, and the signal detection means 73 measures whether there is an output current in each source signal line.

The above operation is performed for all gate signal lines in the same way as in the explanation of cross short. Now, when an ON voltage is applied to the gate signal line G4 and the selection means S S3 is closed, T
Since the G-D short 71 occurs in the FT's TM's z and the TFT's TM, is in the operating state, the gate signal line G4→G-D short 71→TM3's drain→TM,, source → source (separate line sz → PS, → SS
3→signal detection means 73 is generated, so that TP
It is possible to detect that a defect has occurred in the TMI of T.

Move the probe and perform the above operations for all source signal lines.

Finally, a method for detecting an SD short will be explained.

First, probes PS, ~PSs and QS, ・QS
, are pressed against the test electrode 41. Next, the scanning circuit 19 is operated, and an on voltage is applied only to the gate signal line G, and an off voltage is applied to the other gate signal lines. Next, the selection means U S t and U S a are closed, and the source signal line St
and S4 to which the voltage from the signal applying means 72 is applied.
Next, selection means SS.

SSz, SSs are sequentially and selectively closed, and each source signal line S, , S3 . The signal detection means 73 measures whether there is an output voltage at S. Next is the gate signal line G.

The above operation is performed by applying an on-voltage to only the terminal. The above operation is performed for all gate signal lines.

Since an S-D short 70 has now occurred in TM2□ of the TFT, an on-voltage is applied to the gate signal line Gt, and the TFT
When TS, □ is activated and the selection means 5S33 is closed, the signal applying means 72→U S t→Q S t
→Source signal line S2→S-D short 70→P2□→T
FT T S t□→source signal line S,→PS.

Since a current path of →SS3→signal detection means 73 is generated, it is possible to detect that the SD short 70 has occurred at T M z t of the TFT. Move the probe and perform the above operations for all source signal lines.

After the inspection process is completed, a source IC connection process is performed on non-defective products. FIG. 8 is a cross-sectional view of the source IC 14 bonded to the tC connection electrode 30. In FIG. 8, 80 is a protruding electrode, and 81 is a conductive bonding layer. The protrusion electrode is made of An and is formed in a two-step protrusion shape on the terminal of the source IC 14 using ball bonding or nail head bonding technology. Further, a conductive bonding layer of several tens of micrometers is formed on the protruding electrode. The conductive bonding layer is made of a mixture of flakes such as A, ・A, -Ni-C-3, IO□, etc. with an epoxy-based or finol-based adhesive as the main adhesive, and is formed by a technique such as transfer. be done. The source IC 14 is electrically connected to the IC connection electrode 41 via the protruding electrode and the conductive bonding layer.

Next, the conductive bonding layer is fully cured using a method such as an electric oven or a heat column to complete the liquid crystal display panel.

In the description of the method for manufacturing a liquid crystal display panel of the present invention, an inspection process is performed after the panel forming process, but it is clear that the same effect can be obtained even if the panel forming process is performed after the inspection process. Therefore, after the inspection process, a panel forming process may be performed.

Further, although the liquid crystal display panel of the present invention has two TPTs formed on one picture element electrode, the present invention is not limited to this.

Effects of the Invention In the liquid crystal display panel of the present invention, a TPT for driving picture elements and a scanning circuit are formed on a semiconductor substrate, and a source IC is mounted using COG technology. Since the scanning circuit has a relatively small circuit scale and can be easily formed, the incidence of defects and failures is low. When attempting to incorporate the function of a source IC into a semiconductor substrate, the circuit for realizing the function is large and is prone to defects and failures. Therefore, the manufacturing yield of the liquid crystal display panel of the present invention is much higher than that of a panel in which the function of a source IC is built into a semiconductor substrate. In addition, conventional liquid crystal display panels that use flexible substrates and are connected to scanning ICs cannot handle fine pattern signal line pitches of 100 μm or less, but the liquid crystal display panel of the present invention can sufficiently handle the problem. It is possible.

Furthermore, in the method for manufacturing a liquid crystal display panel of the present invention, an inspection step is performed before connecting the source IC.

In the inspection process, the current generated during S-D short is usually 1
It is extremely small, less than μA. Therefore, the source IC
is connected or formed during the inspection process, the I
This is affected by the input impedance of C. Therefore, it is difficult to detect minute currents, and defects cannot be detected. Further, by simply operating the scanning circuit, on-voltage or off-voltage can be applied to all gate signal lines at once. Therefore, the same effect as when probes are pressed into contact with all the gate signal lines can be obtained, and the test time can be constantly shortened. Further, the probe only needs to be pressure-connected on the source signal line side, which leads to a reduction in the manufacturing cost of the probe. Furthermore, in the liquid crystal display panel of the present invention, two TPTs are formed on one picture element electrode, and voltage can be applied to all gate signal lines at once by the scanning circuit, which cannot be detected with conventional liquid crystal display panels. It is also possible to detect S-D open and S-D short that were not present. From the above, after the scanning circuit is formed, the quality of the liquid crystal display panel can be determined quickly and easily, which is highly effective.

[Brief explanation of drawings]

1(a) to (C) are a plan view and a sectional view of the liquid crystal display panel of the present invention, FIG. 2 is a partial equivalent circuit diagram of the display area of the liquid crystal display panel of the present invention, and FIG. 3(a) 3(b) is a functional block diagram of the scanning circuit; FIG. 4 is a partially enlarged plan view of the test electrode forming portion of the liquid crystal display panel of the present invention; FIG. Figure 5 (a) [Yes]) ~
FIG. 8 is an explanatory diagram of the method for manufacturing a liquid crystal display panel of the present invention,
9(a) and 9(b) are a plan view and a sectional view of a conventional liquid crystal display panel, FIG. 10 is a partial equivalent circuit diagram of a display area of a conventional liquid crystal display panel, and FIG. 11 is a connection of a flexible substrate. Partially enlarged plan view of the connection electrode forming part for
2(a) to 14 are explanatory diagrams of a conventional method of manufacturing a liquid crystal display panel. 10.90...LCD, 11.91...
Substrate, 12・92...Counter electrode, 13...
...Inspection electrode formation section, 14...Source IC,
15・93・Gl~G4・・・Gate signal line, 1
6.94.S, -S,... Source signal line, 17
・18...Leader line, 19...Scanning circuit forming part, 20・100...Sealing resin, P
, ~P44...Picture element electrode, Tll~T44・T
M,,~TM3.・TS,,-'rs 44...
...TFT, 30...IC connection electrode, 31
...IC loading position, 32...Shift register circuit, 33...Latch circuit, 34...
...Drive circuit, 35...Output current limiting circuit, 41...Testing electrode, 70...S
-D short, 71...G-D short, 72
... Signal application means, 73 ... Signal detection means, 74, 140 ... Cross short, P
S, ~PS, ・PC, ~PG, ・QS, ・
Q S 4... Connection means, SS, ~SS4
・sc, -sc.・US2 ・US,... Selection means, 80...
... Projection electrode, 81 ... Conductive bonding layer, 95
......Connection electrode forming part, 96...Flexible substrate, 97...IC board, 98...
...Scan IC199...Source IC1101...
... Lead wire, 110 ... Connection electrode, 141 ... Resistance value measuring means. Name of agent: Patent attorney Shigetaka Awano Haka 1 person 1M 2
figure! J+4Ss - Source IK % IIGl-G4--
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10,000l+-In case--TPT! 1 Gin Umbrella! 1= Ward 32- Shift Jis9 circuit 33-F1 Sochiro path 34--Drive circuit P-F-F-R-C-R-MTI-EN-I-N-W13゜CL-I-K11 SubFIll#IH group mm child 41, -
-One ellipse electrode τ- π--- β--- Source/drain rectangle & 3τ recess/tray'/Short %τ recess fl! ! En1xJ Season pitching signal detection means %-Cross Zicoat QSz, QSa---f* l! + Role USt, US Filter-1 Translation Means Figure 10/10-m- Connecting Power 1 112FJ! A +2f) --- Infusion Ill Area F. Figure 8' +40--Cross shoot 141--Resistance am constant means

Claims (7)

[Claims] (1) A switching element that drives a picture element and a scanning circuit that applies a signal to a gate signal line connected to the switching element are formed on a semiconductor substrate, and a driving signal line is connected to a source signal line connected to the switching element. A liquid crystal display panel characterized in that ICs are connected via a conductive bonding layer. (2) The liquid crystal display panel according to claim (1), wherein an output current control circuit is formed in the output section of the scanning circuit. (3) The liquid crystal display panel according to claim (1), wherein a plurality of switching elements are formed in one picture element. (4) The liquid crystal display panel according to claim (1), wherein an inspection electrode is formed between the electrode connecting the driving IC and the display area in which the switching element is formed. (5) The liquid crystal display panel according to claim (2), wherein the output current control circuit can be switched between a normal output current state and an output current limiting state by an applied external input signal. (6) A switching element for driving picture elements and a scanning circuit are formed on a polysilicon substrate, a substrate on which a counter electrode is formed is mounted on the substrate, liquid crystal is injected between the substrates to form a panel, and the scanning circuit is formed. The liquid crystal panel is operated and an inspection pad is used to perform an inspection process on the liquid crystal panel, and then a driving IC having a protruding electrode formed on a source signal line is connected via a conductive bonding layer. A method for manufacturing a liquid crystal display panel. (7) The method for manufacturing a liquid crystal display panel according to claim (6), wherein the inspection step is performed by detecting a current flowing through a source signal.