JPH0225136A - Light reception circuit - Google Patents

Abstract

PURPOSE:To detect the normality or abnormity of a reception signal by discriminating whether or not a clock component exists in a received binarization code and further discriminating whether or not a consecutive time of the clock component is shorter than the shortest transmission data length. CONSTITUTION:A received optical signal is converted into an electric signal by a photodetector 1, amplified by an amplifier 2 and binarized by a signal comparator 3. When a binary signal (a) outputted from the signal comparator 3 is normal and a clock component exists, a clock component detection 5 detects it and outputs a detection signal (b). A reception fault signal output circuit 6 receiving the detection signal (b) discriminates whether or not its consecution time T0 is over the shortest transmission data length or over in a timing t1. When an identification error or missing of the reception signal takes place, the clock component in the reception signal is missing over a prescribed period or locally. Thus, the reception abnormal signal output circuit 6 outputs a reception abnormal signal (c).

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an optical receiving circuit for receiving optical signals suitable for an optical fiber communication system.

(Prior Art) When performing optical fiber communication, in order to reduce the number of optical fibers, it is common to transmit clock information on one optical fiber at the same time as the information to be transmitted. To do this, the information to be transmitted is converted into a serial signal, and then encoded with a clock signal to convert the information and clock into a single signal, which is then transmitted.

There are various types of code signals containing lock information, but Manchester code signals and the like are used in optical fiber communications. This code signal is the exclusive OR of the clock and data, as shown in FIG. Therefore, even if the data is continuously "0" or "1", the code signal rises and falls at intervals within one period T of the clock waveform, depending on the clock waveform.

On the receiving side, after converting the optical signal into an electrical signal in the optical receiving circuit, the code signal is input to the PLL circuit, and the synchronization clock is regenerated based on the edge of the change point of the code signal. to separate the clock signal from the code,
By sampling the received signal in synchronization with this, the original signal is restored and received.

(Problem to be Solved by the Invention) By the way, when receiving this optical signal, the optical signal is converted into an electrical signal by a light receiving element, amplified, and then converted into a digital signal by being binarized by a voltage comparator. It is carried out. Therefore, in order to perform correct binarization, it is necessary that the level of the received signal is sufficient, and when a signal of the same level as the reference voltage of the voltage comparator is received, rQJ[1 ) could result in incorrect signal judgment or signal loss during reception. When such a signal loss occurs, the original and subsequent transmission data (
A phenomenon occurs in which a packet (hereinafter referred to as a packet) is broken into multiple pieces, which can cause serious malfunctions, especially in systems that control transmission and reception by counting the number of packets.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an optical receiving circuit that can detect errors in binarization, particularly missing clock signals, when receiving optical signals whose level has decreased, and can notify the occurrence of an abnormality.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides an optical receiving circuit that photoelectrically converts a received optical signal and converts it into a binary signal, in order to detect a change in the signal level of the binary signal within a specified time. a clock component detection circuit that detects the presence or absence of a clock component included in the code; and a clock component detection circuit that monitors the output of this detection circuit and detects whether the clock component is received when the duration of the clock component is shorter than the expected shortest transmission data length. The present invention is characterized in that it includes a reception abnormal signal output circuit that outputs an abnormal signal.

(Function) With this configuration, it is determined whether or not a clock component exists in the received binary code, and if a clock component is present, the shortest transmission data for which the duration of the clock component is assumed is determined. By determining whether the signal is shorter than the length, it is possible to detect whether the received signal is normal or abnormal9 (Embodiment) FIG. The optical receiving circuit of this embodiment includes a light receiving element 1 that converts an optical signal into an electrical signal, an amplifier 2 that amplifies the converted electrical signal. A signal comparator 3 which converts the received electrical signal amplified by the amplifier 2 into a binary output signal a. and a reference signal generator 4 for binarization, and 2 which is the output of the signal comparator 3.
The presence or absence of a clock component in the value signal a is detected, and when a clock component is present.

The clock component detection circuit 5 that outputs the detection signal S further determines the duration of the detection signal S, and determines the duration of the detection signal S.

It is comprised of a reception abnormality signal output circuit 6 which outputs reception abnormality No. 43C when the length is shorter than the expected shortest transmission data length.

Here, the signal comparator 3 should actually be configured with a voltage comparator. Also, as explained in FIG. 3 above, in the case of optical communication, the reception signal 18 includes a clock component for synchronization. . This is a signal component that always inverts to "OJo" 1 within a certain period of time, and the clock component detection circuit 5 monitors whether the received signal is inverted to rOJMrlJ within a certain period of time and detects whether the received signal is inverted to 1. For example, it is configured to output a detection signal assuming that there is a clock component. For example, in the case of Manchester code, the fixed time monitoring time referred to here is set as a time slightly longer than one cycle time T of the original clock as shown in FIG. Once detected, the continuity of the clock component is monitored by setting a new monitoring time from that point onwards. Therefore, as long as the received signal is normal and the clock component is present, the detection signal remains in the "1" state continuously from the start to the end of one optical signal reception.

On the other hand, the reception abnormality signal output circuit 6 monitors whether or not there are more detection signals output from the clock component detection circuit 5 than the shortest reception signal unit (transmission data) that should be received continuously. - For example, measure the time from the rising edge of the detection signal to the falling edge, compare it with a specified time that is the shortest received signal unit, and if it is shorter than the specified time, a reception abnormal signal C is generated. It can be configured with a timer circuit that outputs an output.

With the above configuration, the operation of converting the optical signal received by the light-receiving element 1 into an electrical signal, amplifying it to a certain level in the amplifier 2, and then binarizing it in the signal comparator 3 is the same as in the general case. Therefore, if the level of the received signal is low and the same level as the reference signal of the signal comparator 3, identification errors, omissions, etc. of the received signal will occur. The clock component detection circuit 5 is provided to prevent such problems.
Then, if the binarized signal a output from the signal comparator 3 is normal and a clock component is present, the reception abnormality signal output circuit 6 detects this and outputs all the detection signals. Output. Upon receiving this detection signal, the reception abnormality signal output circuit 6 determines whether or not the duration time TI is longer than the specified time (minimum transmission data length) at a timing of t, as shown in FIG. .

When an identification error or omission occurs in the received signal, the clock component in the received signal is partially or over a certain period of time missing. Therefore, the detection signal is "0" in the middle of reception.
” will fall. Then, the reception abnormality signal output circuit 6 outputs the duration T. It is determined that the time is shorter than the specified time, and a reception abnormality signal C is output.

In this way, the optical receiving circuit includes the clock component detection circuit 5,
By providing the reception abnormality signal output circuit 6, it is possible to detect an abnormality in the operation of the optical reception circuit or the reception signal itself, and prevent malfunctions in transmission and reception control.

Note that this reception abnormality signal C may be set to "1" only when an abnormality is detected, or it may be set to "1" continuously when a -degree abnormality is detected and held until a reset signal is received from a transmission/reception control unit (not shown). You can do it like this.

[Effects of the Invention] As described above, according to the present invention, it is possible to detect abnormalities in received signals due to identification errors and omissions of received signals in an optical fiber communication system, and to prevent malfunctions in transmission/reception control and reception of erroneous data. I can do it. .

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an optical receiving circuit showing an embodiment of the present invention;
FIG. 2 is an explanatory diagram of the operation of the reception abnormality signal output circuit, and FIG. 3 is an explanatory diagram of the Manchester code. DESCRIPTION OF SYMBOLS 1... Light receiving element, 2... Amplifier, 3... Voltage comparator, 4... Reference signal generator, 5... Clock component detection circuit. 6... Reception error (I output circuit Figure 1 1 WC-----D ■Ding-----Figure 2 Figure 3

Claims (1)

[Claims] A light receiving element that converts an encoded received optical signal including a clock signal for synchronization into an electrical signal, an amplifier that amplifies the electrical signal, and a signal that binarizes the output signal of this amplifier by comparing it with a reference signal. a clock component detection circuit that detects the presence or absence of a clock component included in a code by checking a signal level change within a specified time of the binary signal output from the signal comparator; and a reception abnormality signal output circuit that monitors the output of the detection circuit and outputs a reception abnormality signal when the duration of the clock component is shorter than the expected shortest transmission data length. Optical receiver circuit.