JPH0224025B2 - - Google Patents
Info
- Publication number
- JPH0224025B2 JPH0224025B2 JP59147957A JP14795784A JPH0224025B2 JP H0224025 B2 JPH0224025 B2 JP H0224025B2 JP 59147957 A JP59147957 A JP 59147957A JP 14795784 A JP14795784 A JP 14795784A JP H0224025 B2 JPH0224025 B2 JP H0224025B2
- Authority
- JP
- Japan
- Prior art keywords
- superlattice structure
- effect transistor
- field effect
- carrier
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005669 field effect Effects 0.000 claims description 15
- 239000010409 thin film Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 20
- 238000010586 diagram Methods 0.000 description 9
- 239000010408 film Substances 0.000 description 8
- 239000000969 carrier Substances 0.000 description 5
- 230000007423 decrease Effects 0.000 description 3
- 239000012159 carrier gas Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 230000005195 poor health Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
- H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、非晶質薄膜による超格子構造を用い
た電界効果トランジスタに関し、特に超格子構造
内に形成されるポテンシヤル井戸を主にチヤネル
部として使用した高速動作可能な電界効果トラン
ジスタに関するものである。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a field effect transistor using a superlattice structure made of an amorphous thin film. The present invention relates to a field effect transistor that can operate at high speed and is used as a device.
従来の電界効果トランジスタにおいては、キヤ
リアの蓄積されるチヤネル部がゲート絶縁膜と半
導体の界面近傍に集中するため、チヤネル内を走
行するキヤリアは、界面準位あるいはゲート絶縁
膜内のキヤリア捕獲準位によつて捕獲される。キ
ヤリアを捕獲した準位は、チヤネル内を走行する
キヤリアを散乱させて移動度の低下を招いたり、
制御不可能な再放出によるキヤリア生成を行つ
て、ヒステリシス特性や特性変動を生じる原因と
なる。このためキヤリア捕獲準位は、誤動作の原
因となつたり、高速動作の大きな障害となつてい
る。
In conventional field effect transistors, the channel where carriers are accumulated is concentrated near the interface between the gate insulating film and the semiconductor, so the carriers traveling within the channel are trapped at the interface level or the carrier trapping level within the gate insulating film. captured by. The level that captures the carrier scatters the carrier traveling in the channel, causing a decrease in mobility,
Carrier generation occurs due to uncontrollable re-emission, which causes hysteresis characteristics and characteristic fluctuations. For this reason, the carrier capture level causes malfunctions and is a major hindrance to high-speed operation.
本発明は、超格子構造をチヤネル部に使用する
ことにより、安定で且つ高速動作可能な電界効果
トランジスタを提供する。
The present invention provides a field effect transistor that is stable and capable of high-speed operation by using a superlattice structure in a channel portion.
超格子構造は、禁制帯幅の異なる２種類の半導
体の各極めて薄い非晶質の膜、すなわちそれぞれ
数百Ａ以下の非晶質薄膜を交互に積層して形成し
たものである。 The superlattice structure is formed by alternately stacking extremely thin amorphous films of two types of semiconductors having different forbidden band widths, that is, amorphous thin films each having a thickness of several hundred amperes or less.
以下に、本発明の詳細を実施例にしたがつて説
明する。
The details of the present invention will be explained below with reference to Examples.
第１図は、本発明の１実施例である薄膜電界効
果トランジスタの断面図である。図において、１
は半導体のバルク層、２は動作時にチヤネルが形
成されるヘテロ接合超格子構造の活性層、３はソ
ース、４はドレイン、５はゲート電極、６はSiO2
あるいはSi3N4などのゲート絶縁膜を表している。 FIG. 1 is a cross-sectional view of a thin film field effect transistor that is an embodiment of the present invention. In the figure, 1
is a semiconductor bulk layer, 2 is an active layer of a heterojunction superlattice structure in which a channel is formed during operation, 3 is a source, 4 is a drain, 5 is a gate electrode, and 6 is S i O 2
Alternatively, it represents a gate insulating film such as Si3N4 .
本実施例では、ヘテロ接合超格子構造の活性層
２の厚さは約200Åであるが、200乃至200Åの範
囲に製作することができる。キヤリアは、ソース
およびドレイン間で、活性層２の超格子構造内に
形成されるポテンシヤル井戸層に拘束された状態
で、２次元的に高速度で伝播する。図中の実線の
矢線は電子流を表している。 In this embodiment, the thickness of the active layer 2 having a heterojunction superlattice structure is about 200 Å, but it can be manufactured to a thickness in the range of 200 to 200 Å. The carrier propagates two-dimensionally at high speed between the source and the drain while being restrained by the potential well layer formed within the superlattice structure of the active layer 2. The solid arrow in the figure represents the electron flow.
ヘテロ接合超格子構造は、非晶質SiとSi1−xNx
またはSiとSi1−xCxなどの超薄層を交互に積層し
て形成される。第２図はその１例を示したもの
で、７は水素を含有する非晶質のａ−Si1−xNx：
Ｈ層、８は非晶質のａ−Si：Ｈ層であり、層７と
層８は交互に積層されている。各層の厚さＷは、
30〜200Åの範囲が適当である。 The heterojunction superlattice structure consists of amorphous S i and S i1 − x N x
Alternatively, it is formed by alternately stacking ultra-thin layers such as S i and S i1 − x C x . Figure 2 shows one example, where 7 is an amorphous a-S i1 − x N x containing hydrogen:
The H layer 8 is an amorphous a-S i :H layer, and the layers 7 and 8 are laminated alternately. The thickness W of each layer is
A range of 30 to 200 Å is suitable.
第３図は、第２図に示した超格子構造のエネル
ギーバンド図である。図示のように、ａ−Si1−x
Nx：Ｈ（ｘ＝0.24）層の禁制帯幅は1.96eVであ
り、ａ−Si：Ｈ層のそれは1.72eVであつて、後者
の層は前者の層に対してポテンシヤル井戸となつ
ている。 FIG. 3 is an energy band diagram of the superlattice structure shown in FIG. 2. As shown, a−S i1 − x
The forbidden band width of the N x :H (x=0.24) layer is 1.96 eV, and that of the a-S i :H layer is 1.72 eV, and the latter layer acts as a potential well with respect to the former layer. There is.
第４図は、第１図に示した薄膜電界効果トラン
ジスタにおける、フラツトバンド状態（ゲート電
圧無印加時又は小さいゲート電圧で実現される）
でのエネルギーバンド図を示したもので、第５図
は、これに比較的大きい正のゲート電圧VGを印
加し、チヤネルを形成した状態でのエネルギーバ
ンド図を示したものである。また第６図は、比較
のため、超格子構造をもたない従来の薄膜電界効
果トランジスタに比較的大きい正のゲート電圧印
加時におけるエネルギーバンド図を示したもので
ある。 Figure 4 shows the flat band state (achieved when no gate voltage is applied or with a small gate voltage) in the thin film field effect transistor shown in Figure 1.
FIG. 5 shows the energy band diagram when a relatively large positive gate voltage V G is applied to this to form a channel. For comparison, FIG. 6 shows an energy band diagram when a relatively large positive gate voltage is applied to a conventional thin film field effect transistor that does not have a superlattice structure.
電界効果トランジスタのチヤネル部に超格子構
造を導入することにより、安定で且つ高速の動作
が得られるのは次の３つの理由による。 Stable and high-speed operation can be achieved by introducing a superlattice structure into the channel portion of a field effect transistor for the following three reasons.
第１には、超格子構造内に形成されるポテンシ
ヤル井戸層に閉じ込められたキヤリアは、井戸幅
がキヤリアのド・ブロイ波長程度（数＋Å）に狭
い場合には、量子サイズ効果により、キヤリアが
２次元的にのみ分布する２次元キヤリアガス状態
となることである。この２次元キヤリアガス状態
において井戸層内のキヤリア輸送時の散乱は、２
次元等エネルギー面内での散乱のみが支配的とな
つてキヤリア散乱確率が減少するため、キヤリア
移動度が増大する。 First, carriers confined in a potential well layer formed in a superlattice structure are This results in a two-dimensional carrier gas state that is distributed only two-dimensionally. In this two-dimensional carrier gas state, the scattering during carrier transport within the well layer is 2
Since only the scattering within the dimensional equi-energy plane becomes dominant and the carrier scattering probability decreases, the carrier mobility increases.
第２には、第５図中にキヤリアが電子の場合に
ついてで示されているように、キヤリアの電子
は、超格子構造内の各ポテンシヤル井戸層に閉
じ込められ、ゲート絶縁膜から離れて形成された
チヤネルを走行するようになることである。その
ため、第６図に示す従来例の場合のように、ゲー
ト絶縁膜界面に存在する界面準位により電子が
捕獲されたり、界面付近の固定電荷により散乱を
うけて、キヤリア移動度が低下するというような
下具合点が大幅に改善される。 Second, as shown in Figure 5 for the case where the carriers are electrons, the carrier electrons are confined in each potential well layer in the superlattice structure and are formed away from the gate insulating film. This means that the vehicle will be able to travel on the same channel as before. Therefore, as in the case of the conventional example shown in Figure 6, electrons are captured by the interface states existing at the gate insulating film interface, or are scattered by fixed charges near the interface, resulting in a decrease in carrier mobility. Poor health scores such as these will be significantly improved.
第３には、第５図のエネルギーバンド図に示さ
れるように、超格子構造を用いた場合、キヤリア
（電子）の分布が各ポテンシヤル井戸層に空間的
に分離されて分布するため、ゲート電圧VGの印
加によつて生ずるバンドの曲がりが均一化され、
第６図の従来例のものでは、強くバンドの曲がる
領域が表面から100Å乃至200Å程度の深さしかな
かつたのにくらべて、表面層よりさらに深い位置
（たとえば数百Å）にまで及ぶことである。これ
により、平均電界強度を表面層で低下させること
ができ、強電界下での界面準位やゲート絶縁膜内
の捕獲準位へのキヤリア捕獲を抑制することが可
能となる。 Thirdly, as shown in the energy band diagram in Figure 5, when a superlattice structure is used, the distribution of carriers (electrons) is spatially separated in each potential well layer, so the gate voltage The bending of the band caused by the application of V G is made uniform,
In the conventional example shown in Figure 6, the region where the band bends strongly was only at a depth of about 100 Å to 200 Å from the surface; be. As a result, the average electric field strength can be lowered in the surface layer, and carrier trapping in the interface level or the trap level in the gate insulating film under a strong electric field can be suppressed.
なお、本発明は、薄膜電界効果トランジスタを
実施例として説明されたが、一般のMOS型電界
効果トランジスタにも適用できることは容易に理
解できるところである。 Although the present invention has been described using a thin film field effect transistor as an example, it is easy to understand that it can also be applied to a general MOS type field effect transistor.
また、本実施例で使用された非晶質半導体Si，
Si1−xNxは本発明に適用可能な１例にすぎず、広
い範囲の材料の組み合わせが可能である。 In addition, the amorphous semiconductor S i used in this example,
S i1 −x N x is only one example applicable to the present invention, and a wide range of combinations of materials are possible.
以上のように、本発明によれば、超格子構造を
電界効果トランジスタのチヤネル部に使用するこ
とで、キヤリア移動度の増大とともに、捕獲準位
によるキヤリア捕獲の抑制とが図られ、誤動作が
極めて少なくて高速動作が可能な非晶質半導体を
用いた電界効果トランジスタを提供することがで
きる。
As described above, according to the present invention, by using a superlattice structure in the channel portion of a field effect transistor, it is possible to increase carrier mobility and suppress carrier trapping by trapping levels, which greatly reduces malfunction. It is possible to provide a field effect transistor using an amorphous semiconductor that can operate at high speed with a small amount of material.
第１図は本発明の１実施例の薄膜電界効果トラ
ンジスタの断面図、第２図はヘテロ接合超格子構
造の１実施例を示す図、第３図は第２図に示すヘ
テロ接合超格子構造のエネルギーバンド図、第４
図は第１図に示す実施例のフラツトバンド状態の
時のエネルギーバンド図、第５図は同じ実施例の
ゲート電圧印加時のエネルギーバンド図、第６図
は従来の薄膜電界効果トランジスタのゲート電圧
印加時のエネルギーバンド図である。
図中、１はバルク層、２はヘテロ接合超格子構
造の活性層、３はソース、４はドレイン、５はゲ
ート電極、６はゲート絶縁膜を示す。
FIG. 1 is a cross-sectional view of a thin film field effect transistor according to an embodiment of the present invention, FIG. 2 is a diagram showing an embodiment of a heterojunction superlattice structure, and FIG. 3 is a heterojunction superlattice structure shown in FIG. 2. Energy band diagram of 4th
The figure shows an energy band diagram of the embodiment shown in Fig. 1 in a flat band state, Fig. 5 shows an energy band diagram of the same embodiment when a gate voltage is applied, and Fig. 6 shows a conventional thin film field effect transistor when a gate voltage is applied. It is an energy band diagram of time. In the figure, 1 is a bulk layer, 2 is an active layer with a heterojunction superlattice structure, 3 is a source, 4 is a drain, 5 is a gate electrode, and 6 is a gate insulating film.
Claims (1)
い非晶質の薄膜を交互に積層して製作されるヘテ
ロ接合超格子構造のチヤネル部をもつ電界効果ト
ランジスタ。1. A field-effect transistor having a channel portion with a heterojunction superlattice structure manufactured by alternately stacking extremely thin amorphous thin films of two types of semiconductors with different forbidden band widths.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14795784A JPS6127681A (en) | 1984-07-17 | 1984-07-17 | Field effect transistor having channel part of superlattice construction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14795784A JPS6127681A (en) | 1984-07-17 | 1984-07-17 | Field effect transistor having channel part of superlattice construction |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6127681A JPS6127681A (en) | 1986-02-07 |
| JPH0224025B2 true JPH0224025B2 (en) | 1990-05-28 |
Family
ID=15441903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14795784A Granted JPS6127681A (en) | 1984-07-17 | 1984-07-17 | Field effect transistor having channel part of superlattice construction |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6127681A (en) |
Families Citing this family (47)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0719888B2 (en) * | 1985-04-05 | 1995-03-06 | セイコーエプソン株式会社 | Field effect transistor and method of manufacturing the same |
| JPS62279672A (en) * | 1986-05-28 | 1987-12-04 | Kanegafuchi Chem Ind Co Ltd | Semiconductor device |
| FR2600821B1 (en) * | 1986-06-30 | 1988-12-30 | Thomson Csf | HETEROJUNCTION AND DUAL CHANNEL SEMICONDUCTOR DEVICE, ITS APPLICATION TO A FIELD EFFECT TRANSISTOR, AND ITS APPLICATION TO A NEGATIVE TRANSDUCTANCE DEVICE |
| JP2709374B2 (en) * | 1986-10-08 | 1998-02-04 | 株式会社 半導体エネルギー研究所 | Insulated gate field effect semiconductor device |
| US4908678A (en) * | 1986-10-08 | 1990-03-13 | Semiconductor Energy Laboratory Co., Ltd. | FET with a super lattice channel |
| JPS6394681A (en) * | 1986-10-08 | 1988-04-25 | Semiconductor Energy Lab Co Ltd | Manufacture of insulated-gate field-effect semiconductor device |
| JPS6394682A (en) * | 1986-10-08 | 1988-04-25 | Semiconductor Energy Lab Co Ltd | Manufacture of insulated-gate field-effect semiconductor device |
| US4849797A (en) * | 1987-01-23 | 1989-07-18 | Hosiden Electronics Co., Ltd. | Thin film transistor |
| US5051786A (en) * | 1989-10-24 | 1991-09-24 | Mcnc | Passivated polycrystalline semiconductors quantum well/superlattice structures fabricated thereof |
| JP2692599B2 (en) | 1994-07-27 | 1997-12-17 | 株式会社島津製作所 | Laser non-contact extensometer |
| US6993222B2 (en) | 1999-03-05 | 2006-01-31 | Rj Mears, Llc | Optical filter device with aperiodically arranged grating elements |
| GB2385941B (en) | 1999-03-05 | 2003-10-22 | Nanovis Llc | Non-linear optical loop miror with aperiodic grating |
| JP3373831B2 (en) | 2000-01-19 | 2003-02-04 | 岸本産業株式会社 | Test specimen elongation measuring method and apparatus |
| WO2002001641A1 (en) * | 2000-06-27 | 2002-01-03 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
| KR100454199B1 (en) | 2000-11-21 | 2004-10-26 | 마츠시타 덴끼 산교 가부시키가이샤 | Semiconductor device and its manufacturing method |
| US6830964B1 (en) | 2003-06-26 | 2004-12-14 | Rj Mears, Llc | Method for making semiconductor device including band-engineered superlattice |
| US7612366B2 (en) | 2003-06-26 | 2009-11-03 | Mears Technologies, Inc. | Semiconductor device including a strained superlattice layer above a stress layer |
| US7491587B2 (en) | 2003-06-26 | 2009-02-17 | Mears Technologies, Inc. | Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer |
| US6833294B1 (en) * | 2003-06-26 | 2004-12-21 | Rj Mears, Llc | Method for making semiconductor device including band-engineered superlattice |
| US7531850B2 (en) | 2003-06-26 | 2009-05-12 | Mears Technologies, Inc. | Semiconductor device including a memory cell with a negative differential resistance (NDR) device |
| US7229902B2 (en) | 2003-06-26 | 2007-06-12 | Rj Mears, Llc | Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction |
| US7586165B2 (en) | 2003-06-26 | 2009-09-08 | Mears Technologies, Inc. | Microelectromechanical systems (MEMS) device including a superlattice |
| US7446002B2 (en) | 2003-06-26 | 2008-11-04 | Mears Technologies, Inc. | Method for making a semiconductor device comprising a superlattice dielectric interface layer |
| US7514328B2 (en) | 2003-06-26 | 2009-04-07 | Mears Technologies, Inc. | Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween |
| US7659539B2 (en) | 2003-06-26 | 2010-02-09 | Mears Technologies, Inc. | Semiconductor device including a floating gate memory cell with a superlattice channel |
| US7535041B2 (en) | 2003-06-26 | 2009-05-19 | Mears Technologies, Inc. | Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance |
| US7045813B2 (en) | 2003-06-26 | 2006-05-16 | Rj Mears, Llc | Semiconductor device including a superlattice with regions defining a semiconductor junction |
| US7531829B2 (en) | 2003-06-26 | 2009-05-12 | Mears Technologies, Inc. | Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance |
| AU2004300982B2 (en) | 2003-06-26 | 2007-10-25 | Mears Technologies, Inc. | Semiconductor device including MOSFET having band-engineered superlattice |
| US7045377B2 (en) | 2003-06-26 | 2006-05-16 | Rj Mears, Llc | Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction |
| US7586116B2 (en) | 2003-06-26 | 2009-09-08 | Mears Technologies, Inc. | Semiconductor device having a semiconductor-on-insulator configuration and a superlattice |
| US7531828B2 (en) | 2003-06-26 | 2009-05-12 | Mears Technologies, Inc. | Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions |
| US7598515B2 (en) | 2003-06-26 | 2009-10-06 | Mears Technologies, Inc. | Semiconductor device including a strained superlattice and overlying stress layer and related methods |
| US7227174B2 (en) | 2003-06-26 | 2007-06-05 | Rj Mears, Llc | Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction |
| US7517702B2 (en) | 2005-12-22 | 2009-04-14 | Mears Technologies, Inc. | Method for making an electronic device including a poled superlattice having a net electrical dipole moment |
| US7718996B2 (en) | 2006-02-21 | 2010-05-18 | Mears Technologies, Inc. | Semiconductor device comprising a lattice matching layer |
| US7781827B2 (en) | 2007-01-24 | 2010-08-24 | Mears Technologies, Inc. | Semiconductor device with a vertical MOSFET including a superlattice and related methods |
| US7928425B2 (en) | 2007-01-25 | 2011-04-19 | Mears Technologies, Inc. | Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods |
| US7863066B2 (en) | 2007-02-16 | 2011-01-04 | Mears Technologies, Inc. | Method for making a multiple-wavelength opto-electronic device including a superlattice |
| US7880161B2 (en) | 2007-02-16 | 2011-02-01 | Mears Technologies, Inc. | Multiple-wavelength opto-electronic device including a superlattice |
| US7812339B2 (en) | 2007-04-23 | 2010-10-12 | Mears Technologies, Inc. | Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures |
| US9275996B2 (en) | 2013-11-22 | 2016-03-01 | Mears Technologies, Inc. | Vertical semiconductor devices including superlattice punch through stop layer and related methods |
| WO2015191561A1 (en) | 2014-06-09 | 2015-12-17 | Mears Technologies, Inc. | Semiconductor devices with enhanced deterministic doping and related methods |
| US9722046B2 (en) | 2014-11-25 | 2017-08-01 | Atomera Incorporated | Semiconductor device including a superlattice and replacement metal gate structure and related methods |
| US9899479B2 (en) | 2015-05-15 | 2018-02-20 | Atomera Incorporated | Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods |
| WO2016196600A1 (en) | 2015-06-02 | 2016-12-08 | Atomera Incorporated | Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control |
| WO2018213385A1 (en) | 2017-05-16 | 2018-11-22 | Atomera Incorporated | Semiconductor device and method including a superlattice as a gettering layer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53131779A (en) * | 1977-04-20 | 1978-11-16 | Ibm | Semiconductor superlattice structure |
| JPS55117281A (en) * | 1979-03-05 | 1980-09-09 | Nippon Telegr & Teleph Corp <Ntt> | 3[5 group compound semiconductor hetero structure mosfet |
| JPS5984475A (en) * | 1982-11-05 | 1984-05-16 | Hitachi Ltd | Field effect device |
-
1984
- 1984-07-17 JP JP14795784A patent/JPS6127681A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53131779A (en) * | 1977-04-20 | 1978-11-16 | Ibm | Semiconductor superlattice structure |
| JPS55117281A (en) * | 1979-03-05 | 1980-09-09 | Nippon Telegr & Teleph Corp <Ntt> | 3[5 group compound semiconductor hetero structure mosfet |
| JPS5984475A (en) * | 1982-11-05 | 1984-05-16 | Hitachi Ltd | Field effect device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6127681A (en) | 1986-02-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0224025B2 (en) | ||
| JP2786327B2 (en) | Heterojunction field effect transistor | |
| JP2609587B2 (en) | Semiconductor device | |
| JPH0156543B2 (en) | ||
| JPS62256478A (en) | Compound semiconductor device | |
| JP2722885B2 (en) | Field effect transistor | |
| JPH01186683A (en) | Semiconductor device | |
| JPH0312769B2 (en) | ||
| JPH0355980B2 (en) | ||
| JP2855775B2 (en) | Field effect transistor | |
| JPS61276269A (en) | Hetero-junction type field-effect transistor | |
| JP2761211B2 (en) | Semiconductor device | |
| JPS60235476A (en) | Semiconductor device | |
| JPH0311767A (en) | Velocity modulation type field-effect transistor | |
| JPS6281063A (en) | Superlattice electronic element | |
| JPS62245681A (en) | Negative differential resistance field-effect tran-sistor | |
| JPH0582558A (en) | Field effect transistor | |
| JP2541280B2 (en) | Semiconductor device | |
| JPH0368143A (en) | Heterojunction field-effect transistor | |
| JPS63229763A (en) | Semiconductor device | |
| JPH04250635A (en) | Manufacture of two dimensional electron gas field effect transistor | |
| JPH05102198A (en) | Pseudo-one-dimensional field-effect transistor and its manufacture | |
| JPS6312393B2 (en) | ||
| JPH0338843A (en) | Field-effect transistor | |
| JPH04280639A (en) | Two-dimensional field-feect transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |