JPH02246236A - Flip-chip bonding method - Google Patents
Flip-chip bonding methodInfo
- Publication number
- JPH02246236A JPH02246236A JP6605989A JP6605989A JPH02246236A JP H02246236 A JPH02246236 A JP H02246236A JP 6605989 A JP6605989 A JP 6605989A JP 6605989 A JP6605989 A JP 6605989A JP H02246236 A JPH02246236 A JP H02246236A
- Authority
- JP
- Japan
- Prior art keywords
- solder bumps
- solder
- wiring board
- circuit wiring
- solder bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title description 22
- 229910000679 solder Inorganic materials 0.000 claims abstract description 70
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 125000006850 spacer group Chemical group 0.000 claims abstract description 11
- 238000010438 heat treatment Methods 0.000 claims abstract description 7
- 239000007788 liquid Substances 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 230000004907 flux Effects 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 229920002379 silicone rubber Polymers 0.000 abstract description 4
- 239000004945 silicone rubber Substances 0.000 abstract description 4
- 230000003139 buffering effect Effects 0.000 abstract description 2
- 229910052729 chemical element Inorganic materials 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 10
- 238000002844 melting Methods 0.000 description 4
- 230000008018 melting Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1183—Reworking, e.g. shaping
- H01L2224/1184—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要]
フリップチップ接合方法、特に大規模集積回路(LSI
)素子の回路配線基板上へのフリップチップ接合方法に
関し、
はんだ接合部における熱歪みによる応力を緩和すること
のできるフリップチップ接合方法を提供することを目的
とし、
半導体素子に形成した全てのはんだバンプの頂部を平面
に形成する工程と、前記はんだバンプの頂部を回路配線
基板の電極部に当接させ、前記半導体素子と回路配線基
板の隙間に、初期状態では粘稠な液体であり、一定時間
経過後に硬化するスペーサを配置する工程と、接合のた
めに加熱により前記はんだバンプをリフローさせる工程
とを含むことを特徴とするフリップチップ接合方法を含
み構成する。[Detailed Description of the Invention] [Summary] Flip-chip bonding method, especially large-scale integrated circuit (LSI)
) Regarding the flip-chip bonding method of devices onto circuit wiring boards, the purpose of this is to provide a flip-chip bonding method that can alleviate stress caused by thermal distortion in the solder joints, and all solder bumps formed on semiconductor devices. The top of the solder bump is brought into contact with the electrode part of the circuit wiring board, and the liquid, which is initially viscous, is applied to the gap between the semiconductor element and the circuit wiring board for a certain period of time. The present invention includes a flip-chip bonding method characterized by including a step of arranging a spacer that hardens after a period of time, and a step of reflowing the solder bump by heating for bonding.
本発明はフリップチップ接合方法、特に大規模集積回路
(LSI)素子の回路配線基板上へのフリップチップ接
合方法に関する。The present invention relates to a flip-chip bonding method, and more particularly to a flip-chip bonding method for large-scale integrated circuit (LSI) devices onto a circuit wiring board.
〔従来の技術]
近年のコンピュータシステムの高速化の要求に伴い、L
SI素子間の信号伝播の遅延を低減することが要求され
ている。このため、半導体チップ上の表面電極を回路配
線基板の配線電極に直接はんだ接合するフリップチップ
接合法が提案されているが、このフリップチップ接合法
によるはんだ接合部には、回路配線基板とLSI素子と
の線膨張係数の差による歪み(熱歪み)が加わることと
なる。また、はんだ接合部は微小であることから、信韻
性の高いはんだ接合部を得るには、使用するはんだ材料
、形成するはんだ接合部の形状を吟味する必要がある。[Prior art] With the recent demand for faster computer systems, L
There is a need to reduce delay in signal propagation between SI elements. For this reason, a flip-chip bonding method has been proposed in which surface electrodes on a semiconductor chip are directly soldered to wiring electrodes on a circuit wiring board. Strain (thermal strain) will be added due to the difference in linear expansion coefficient. Furthermore, since solder joints are minute, in order to obtain solder joints with high reliability, it is necessary to carefully consider the solder material to be used and the shape of the solder joints to be formed.
第5図(a)〜(d)は従来のフリップチップ接合方法
を示す工程図である。FIGS. 5(a) to 5(d) are process diagrams showing a conventional flip-chip bonding method.
同図(a)に示すように、半導体素子1へのはんだバン
プ2の形成は、例えばメタルマスク3を介して素子電極
上にインジウム(In)などのはんだを蒸着し、次に、
同図(b)に示すように、フラックスを塗布してからは
んだ融点以上の温度に加熱し、半球状に形成していた。As shown in FIG. 2(a), solder bumps 2 are formed on a semiconductor element 1 by, for example, depositing solder such as indium (In) on the element electrode through a metal mask 3, and then
As shown in FIG. 5B, flux was applied and then heated to a temperature above the melting point of the solder to form a hemispherical shape.
次に、同図(C)に示すように、半導体素子1のはんだ
バンプ2の頂部を回路配線基板4の電極部5に当接させ
、同図(d)に示すように、再び加熱してはんだバンプ
2のリフローによ゛り接合させていた。Next, as shown in the figure (C), the tops of the solder bumps 2 of the semiconductor element 1 are brought into contact with the electrode parts 5 of the circuit wiring board 4, and as shown in the figure (d), they are heated again. They were joined by reflowing the solder bumps 2.
このため、半導体素子1上のはんだバンプ2は、回路配
線基板4に当接させる前には半球状になるとともに、各
電極上へのはんだ蒸着量にバラツキを生じた場合(メタ
ルマスク3の穴径のバラツキによって生じる)には、同
図(ハ)に示すようにはんだバンプ2の高さは不均一と
なる。また、接合したときのはんだバンプ2は、同図(
d)に示すように1、半導体素子1の重さで潰され中央
部が膨らんだ形状に形成され、はんだ接合部は球帯状と
なっていたため、はんだバンプ2と半導体素子1、及び
はんだバンプ2と回路配線基板4の界面に熱歪みによる
応力が集中することになる。Therefore, the solder bumps 2 on the semiconductor element 1 become hemispherical before coming into contact with the circuit wiring board 4, and if the amount of solder vapor deposited on each electrode varies (the holes in the metal mask 3 (caused by variations in diameter), the heights of the solder bumps 2 become non-uniform, as shown in FIG. In addition, the solder bump 2 when bonded is shown in the same figure (
As shown in d), the solder bumps 2, the semiconductor elements 1, and the solder bumps 2 were crushed by the weight of the semiconductor element 1 and were formed in a bulging shape at the center, and the solder joints had a spherical shape. Stress due to thermal strain will be concentrated at the interface between the circuit wiring board 4 and the circuit wiring board 4.
従って、従来のフリップチップ接合方法においては、は
んだバンプ2自身の重要な役割である熱歪みの緩衝効果
は不十分となるため、はんだバンプ2と半導体素子1、
もしくは回路配線基板4との界面付近で、クランクが生
じ最終的に破断に至る問題があった。Therefore, in the conventional flip-chip bonding method, the thermal strain buffering effect, which is an important role of the solder bump 2 itself, is insufficient.
Alternatively, there was a problem in that cranking occurred near the interface with the circuit wiring board 4, eventually leading to breakage.
そこで本発明は、はんだ接合部における熱歪みによる応
力を緩和することのできるフリップチップ接合方法を提
供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a flip-chip bonding method that can alleviate stress caused by thermal strain in solder joints.
上記課題は、半導体素子に形成した全てのはんだバンプ
の頂部を平面に形成する工程と、前記はんだバンプの頂
部を回路配線基板の電極部に当接させ、前記半導体素子
と回路配線基板の隙間に、初期状態では粘稠な液体であ
り、一定時間経過後に硬化するスペーサを配置する工程
と、接合のために加熱により前記はんだバンプをリフロ
ーさせる工程とを含むことを特徴とするフリップチップ
接合方法によって達成される。The above problem involves a step of forming the tops of all solder bumps formed on a semiconductor element into a flat surface, and a step of bringing the tops of the solder bumps into contact with electrode parts of a circuit wiring board, and filling the gaps between the semiconductor element and the circuit wiring board. , by a flip-chip bonding method characterized by including a step of arranging a spacer that is a viscous liquid in an initial state and hardens after a certain period of time, and a step of reflowing the solder bump by heating for bonding. achieved.
本発明によれば、半導体素子と回路配線基板の隙間にス
ペーサを入れるため、リフロー時に両者の間隔が変わる
ことがなくなる。一方、はんだバンプの頂部は、回路配
線基板の電極部の面積より広いことから、リフロー時に
はんだバンプが電極部にぬれていく過程で、はんだバン
プの中央部が括れた形状になる。従って、熱歪みによる
応力は接合部の両界面付近に集中することがなくなり、
はんだバンプ全体で緩和される。According to the present invention, since the spacer is inserted into the gap between the semiconductor element and the circuit wiring board, the gap between the two does not change during reflow. On the other hand, since the top of the solder bump is wider than the area of the electrode portion of the circuit wiring board, the center portion of the solder bump becomes constricted during reflow as the solder bump wets the electrode portion. Therefore, stress due to thermal strain is no longer concentrated near both interfaces of the joint,
Relaxed across the solder bump.
以下、本発明を図示の一実施例により具体的に説明する
。Hereinafter, the present invention will be specifically explained with reference to an illustrated embodiment.
第1図(a)〜(f)は本発明実施例のフリップチップ
接合方法を示す工程図である。FIGS. 1(a) to 1(f) are process diagrams showing a flip-chip bonding method according to an embodiment of the present invention.
まず、同図(a)に示すように、半導体素子11の電極
上には、通常の方法によりはんだバンプ12が形成され
る。例えば、半導体素子11として、10mm口で0
、3a+m厚さ程度のシリコン素子の電極上に、図示し
ないメタルマスクを介・してIn(融点が156°C)
などの材料を蒸着した後、フラックス(アルファメタル
ズ、RM−5776)を塗布してからはんだ融点以上の
温度に加熱し、半球状のはんだバンプ12を形成する。First, as shown in FIG. 2A, solder bumps 12 are formed on the electrodes of the semiconductor element 11 by a conventional method. For example, as the semiconductor element 11, a 10 mm opening is used.
, In (melting point: 156°C) is applied onto the electrode of a silicon element with a thickness of about 3a+m through a metal mask (not shown).
After depositing the materials, flux (Alpha Metals, RM-5776) is applied and heated to a temperature higher than the solder melting point to form hemispherical solder bumps 12.
そして、同じサイズのシリコン板13をはんだバンブ1
2上に置く。Then, solder the silicon plate 13 of the same size to the solder bump 1.
Place it on 2.
次に、同図(9)及び(C)に示すように、再び加熱し
て、全てのはんだバンプ12の頂部に一つの平面部を形
成する。Next, as shown in FIGS. 9 and 9C, heating is performed again to form one flat portion on the tops of all the solder bumps 12.
次に、同図(d)に示すように、半導体素子11を裏返
しにし、フラックスを塗布した回路配線基板14上に載
せ、はんだバンプ12の頂部を回路配線基板14の電極
部15に当接させる。この回路配線基板14は、例えば
、35mm口で0 、6mm厚さ程度のアルミナ基板な
どで形成されている。Next, as shown in FIG. 2D, the semiconductor element 11 is turned over and placed on the circuit wiring board 14 coated with flux, and the tops of the solder bumps 12 are brought into contact with the electrode portions 15 of the circuit wiring board 14. . The circuit wiring board 14 is formed of, for example, an alumina substrate with a diameter of 35 mm and a thickness of about 0.6 mm.
次に、同図(e)に示すように、接合のための加熱工程
前に、半導体素子11四隅の回路配線基板14との隙間
に、例えば、−成型室温硬化シリコーンゴム(信越シリ
コーン製、KE347.348 > などからなるス
ペーサ16を図示しないデイスペンサで充填する。Next, as shown in FIG. 6(e), before the heating process for bonding, molded room-temperature curing silicone rubber (manufactured by Shin-Etsu Silicone, KE347 A dispenser (not shown) is used to fill the spacer 16 made of .348> or the like.
次に、同図げ)に示すように、−成型室温硬化シリコー
ンゴムなどのスペーサ16が硬化したのを確認した後(
10時間後)、図示しないコンベア式リフロー炉を用い
て210°C程度に加熱し、はんだバンプ12をリフロ
ーさせた。Next, as shown in Figure 1), after confirming that the spacer 16 made of molded room temperature curing silicone rubber has hardened (
After 10 hours), the solder bumps 12 were reflowed by heating to about 210° C. using a conveyor type reflow oven (not shown).
第2図は第1図(f)の工程における本発明実施例の斜
視図である。なお、第1図に対応する部分は同一の符号
を記す。FIG. 2 is a perspective view of the embodiment of the present invention in the step of FIG. 1(f). Note that parts corresponding to those in FIG. 1 are denoted by the same reference numerals.
上記フリップチップ接合方法では、半導体素子11と回
路配線基板14の隙間にスペーサ16を入れるため、リ
フロー時に両者の間隔が変わることがなくなる。一方、
はんだバンプ12の頂部は、回路配線基板14の電極部
15の面積より広いことから、リフロー時にはんだバン
プ12が電極部15にぬれていく過程で、はんだバンプ
12の中央部が括れた形状になる。従って、熱歪みによ
る応力は接合部の両界面付近に集中することがなくなり
、はんだバンプ12全体で緩和される。なお、本発明で
は、全ての電極部にはんだバンプ12が接触しているこ
とが不可欠となるため、はんだバンプ12頂部の全てを
一つの平面にする必要がある。そのため、例えば、従来
方法で形成したはんだバンプ12上に、フラックスを塗
布し、さらにはんだがぬれない板としてシリコン板13
を置いて、はんだ融点まで加熱している。また、スペー
サ16は初期状態で粘稠な液体であるため、平面出し後
のはんだバンプ12の高さのバラツキを問題にすること
がなくなる。In the flip-chip bonding method described above, since the spacer 16 is inserted into the gap between the semiconductor element 11 and the circuit wiring board 14, the gap between the two does not change during reflow. on the other hand,
Since the top of the solder bump 12 is wider than the area of the electrode part 15 of the circuit wiring board 14, the center part of the solder bump 12 becomes constricted in the process of getting wet with the electrode part 15 during reflow. . Therefore, stress due to thermal strain is no longer concentrated near both interfaces of the joint, and is relaxed throughout the solder bump 12. In the present invention, it is essential that the solder bumps 12 are in contact with all the electrode parts, so it is necessary to make all the tops of the solder bumps 12 into one plane. For this reason, for example, flux is applied on the solder bumps 12 formed by the conventional method, and a silicon plate 13 is used as a plate that does not get wet with solder.
is heated to the melting point of the solder. Furthermore, since the spacer 16 is a viscous liquid in its initial state, variations in the height of the solder bump 12 after flattening do not pose a problem.
第3図は本発明の実施例によるはんだ接合部の写真に基
く模式図であり、半導体素子11と回路配線基板14の
隙間のはんだバンプ12は、その中央部が括れた形状に
形成されている。なお、第1図に対応する部分は同一の
符号を記す。FIG. 3 is a schematic diagram based on a photograph of a solder joint according to an embodiment of the present invention, and the solder bump 12 in the gap between the semiconductor element 11 and the circuit wiring board 14 is formed in a constricted shape at the center. . Note that parts corresponding to those in FIG. 1 are denoted by the same reference numerals.
第4図は従来のはんだ接合部の写真に基く模式図であり
、半導体素子1と回路配線基板4の隙間のはんだバンプ
2は、半導体素子1の重さで潰されており、その中央部
が膨らんだ形状に形成されている。なお、第5図に対応
する部分は同一の符号を記す。FIG. 4 is a schematic diagram based on a photograph of a conventional solder joint, in which the solder bump 2 in the gap between the semiconductor element 1 and the circuit wiring board 4 is crushed by the weight of the semiconductor element 1, and its central part is It is formed in a bulged shape. Note that parts corresponding to those in FIG. 5 are denoted by the same reference numerals.
なお、上記実施例では、スペーサ16として一液型室温
硬化シリコーンゴムなどを使用しているが、本発明の適
用範囲はこれに限らず、初期状態では粘稠な液体であり
、一定時間経過後に硬化する材料であればよい。また、
はんだバンプ12は、Inを蒸着して形成するものに限
定されない。In the above embodiment, one-component room temperature curing silicone rubber is used as the spacer 16, but the scope of the present invention is not limited to this.In the initial state, it is a viscous liquid, and after a certain period of time, Any material that hardens may be used. Also,
The solder bumps 12 are not limited to those formed by vapor depositing In.
以上説明した様に本発明によれば、はんだバンプの中央
部を括れた形状にしたことで、熱歪みによる応力をはん
だバンブ全体で緩衝させることができ、脆い半導体素子
とはんだバンプの接合界面に作用する応力を緩和でき、
フリップフロップ接合体の信鯨性向上に寄与するところ
が大きい。As explained above, according to the present invention, by making the central part of the solder bump constricted, stress caused by thermal strain can be buffered throughout the solder bump, and the bonding interface between the fragile semiconductor element and the solder bump is It can relieve the stress that is applied,
This greatly contributes to improving the reliability of the flip-flop assembly.
第1図(a)〜げ)は本発明実施例のフリップチップ接
合方法を示す工程図、
第2図は本発明実施例の斜視図、
第3図は本発明実施例によるはんだ接合部の写真に基く
模式図、
第4図は従来のはんだ接合部の写真に基く模式図、
第5図(a)〜(ロ)は従来のフリップチップ接合方法
を示す工程図である。
図中、
11は半導体素子、
12ははんだバンプ、
13はシリコン板、
14は回路配線基板、
15は電極部、
16はスペーサ
を示す。
特許出願人 富士通株式会社
代理人弁理士 久木元 彰
同 大菅義之
半尊イ本素了11
本発現] プに方伝ムイク弓
の糾視図
本梵絹文池4?IIt:Jる1;んfc”接合部の写真
l9本く模式図第3図
従来の11んfぞ接合部め写真l:基く膜に図第
図
4・・・回珀配聾仮
従来の7リーノフ゛フロツフ・接合方法杢示T二須■幻
第
図Figures 1 (a) to (a) are process diagrams showing the flip-chip bonding method according to the embodiment of the present invention, Figure 2 is a perspective view of the embodiment of the present invention, and Figure 3 is a photograph of the solder joint according to the embodiment of the present invention. FIG. 4 is a schematic diagram based on a photograph of a conventional solder joint, and FIGS. 5(a) to 5(b) are process diagrams showing a conventional flip-chip bonding method. In the figure, 11 is a semiconductor element, 12 is a solder bump, 13 is a silicon plate, 14 is a circuit wiring board, 15 is an electrode portion, and 16 is a spacer. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney Akimoto Kuki Hajime Osuga Yoshiyuki Hanson Ihon Soryo 11 Book Expression] Punihoden Muikyu's Examination Book Sanskrit Kinubunike 4? IIt:Jru1;nfc'' joint photo l9 schematic diagram Fig. 3 Conventional 11n fc joint photo l: Diagram of the underlying membrane 7 Reno-Frotsuf/Joining Method Diagram
Claims (1)
12)の頂部を平面に形成する工程と、 前記はんだバンプ(12)の頂部を回路配線基板(14
)の電極部(15)に当接させ、前記半導体素子(11
)と回路配線基板(14)の隙間に、初期状態では粘稠
な液体であり、一定時間経過後に硬化するスペーサ(1
6)を配置する工程と、 接合のために加熱により前記はんだバンプ(12)をリ
フローさせる工程とを含むことを特徴とするフリップチ
ップ接合方法。[Claims] All solder bumps (
forming the top of the solder bump (12) into a flat surface;
), and the semiconductor element (11
) and the circuit wiring board (14), there is a spacer (14) that is a viscous liquid in its initial state and hardens after a certain period of time.
6); and a step of reflowing the solder bump (12) by heating for bonding.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6605989A JPH02246236A (en) | 1989-03-20 | 1989-03-20 | Flip-chip bonding method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6605989A JPH02246236A (en) | 1989-03-20 | 1989-03-20 | Flip-chip bonding method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02246236A true JPH02246236A (en) | 1990-10-02 |
Family
ID=13304914
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6605989A Pending JPH02246236A (en) | 1989-03-20 | 1989-03-20 | Flip-chip bonding method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02246236A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5478007A (en) * | 1993-04-14 | 1995-12-26 | Amkor Electronics, Inc. | Method for interconnection of integrated circuit chip and substrate |
US5795818A (en) * | 1996-12-06 | 1998-08-18 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection and method |
US7670873B2 (en) | 2006-02-08 | 2010-03-02 | Fujitsu Limited | Method of flip-chip mounting |
-
1989
- 1989-03-20 JP JP6605989A patent/JPH02246236A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5478007A (en) * | 1993-04-14 | 1995-12-26 | Amkor Electronics, Inc. | Method for interconnection of integrated circuit chip and substrate |
US5795818A (en) * | 1996-12-06 | 1998-08-18 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection and method |
US6163463A (en) * | 1996-12-06 | 2000-12-19 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection |
US7670873B2 (en) | 2006-02-08 | 2010-03-02 | Fujitsu Limited | Method of flip-chip mounting |
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