JPH02208931A - Polishing process for compound semiconductor substrate - Google Patents
Polishing process for compound semiconductor substrateInfo
- Publication number
- JPH02208931A JPH02208931A JP2936289A JP2936289A JPH02208931A JP H02208931 A JPH02208931 A JP H02208931A JP 2936289 A JP2936289 A JP 2936289A JP 2936289 A JP2936289 A JP 2936289A JP H02208931 A JPH02208931 A JP H02208931A
- Authority
- JP
- Japan
- Prior art keywords
- polishing
- wafer
- substrate
- polished
- polishing process
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 24
- 150000001875 compounds Chemical class 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000007517 polishing process Methods 0.000 title abstract 6
- 238000005498 polishing Methods 0.000 claims abstract description 130
- 239000004744 fabric Substances 0.000 claims abstract description 26
- 230000002093 peripheral effect Effects 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000006061 abrasive grain Substances 0.000 claims abstract description 15
- 239000007788 liquid Substances 0.000 claims description 13
- 239000000126 substance Substances 0.000 claims description 5
- 238000003825 pressing Methods 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 abstract description 55
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000005187 foaming Methods 0.000 abstract 1
- 239000006260 foam Substances 0.000 description 5
- 239000004745 nonwoven fabric Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000007665 sagging Methods 0.000 description 3
- 241000257465 Echinoidea Species 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000036772 blood pressure Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は、基板表面の加工ひずみ層を除去し、ひずみの
ない鏡面を得るための、ラッピング後に行われる化合物
半導体基板の研磨方法に係り、特に、2次に亙って行わ
れるポリシングのうちの1次ポリシングを改善したもの
に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for polishing a compound semiconductor substrate after lapping, in order to remove a processed strain layer on the surface of the substrate and obtain a distortion-free mirror surface. In particular, the present invention relates to improved primary polishing of secondary polishing.
[従来の技術]
化合物半導体基板(以下、ウェハという)の研磨には、
■ウェハ表面に研磨ダメージが残っていないこと、■ウ
ェハの厚さむらがなく平坦であり、ひずみのない鏡面を
得ることが要求される。[Conventional technology] For polishing compound semiconductor substrates (hereinafter referred to as wafers),
(2) There is no polishing damage left on the wafer surface; (2) The wafer is required to have an even and flat thickness and a mirror surface without distortion.
この要求を満たすために採用されるウェハ研磨方法とし
ては、先ずラッピングで平坦度と厚さを揃え、次いでポ
リシングでラッピングのダメージを取り除き、ひずみの
ない鏡面を得るようにしている。The wafer polishing method adopted to meet this requirement is to first achieve uniform flatness and thickness by lapping, and then to remove damage caused by lapping by polishing to obtain a mirror surface without distortion.
第2図はウェハをポリシングするための片面ポリシング
装置例を示す。FIG. 2 shows an example of a single-sided polishing apparatus for polishing wafers.
マウント板と呼ばれるトッププレート3に複数枚のウェ
ハ4,4をワックス6で貼り付ける。トッププレート3
は回転する(矢印方向)ようになっている。ウェハ4,
4を研磨布2を張った回転(矢中方向)する研磨定盤l
に押し付ける。研磨定盤lへの押し付けは加圧シリンダ
7によって行っている。研磨定盤lの中央から研磨液5
を供給しながら研磨定盤1及びトッププレート3を回転
させて、ウェハ4,4を研磨するようなっている。A plurality of wafers 4 are attached to a top plate 3 called a mount plate with wax 6. Top plate 3
is designed to rotate (in the direction of the arrow). wafer 4,
4 is a polishing surface plate l that rotates (in the direction of the arrow) with polishing cloth 2 stretched on it.
to press against. Pressing against the polishing surface plate l is performed by a pressure cylinder 7. Polishing liquid 5 from the center of the polishing surface plate L
The wafers 4 are polished by rotating the polishing surface plate 1 and the top plate 3 while supplying the wafers.
このポリシング装置を使うポリシリグ作業は1次、2次
の2回に亙って行われる。1次ポリシングでは平坦度を
維持するために、砥粒入すの研磨液5と不織布で作った
比較的硬質の研磨布2とを用いる。また、2次ポリシン
グでは1次ポリシング面に残っている僅かなダメージを
取り除き、且つ、表面に微小な凹凸のない鏡面に仕上げ
るため、砥粒を含まない化学液からなる研磨液5と発泡
層を持つ比較的軟質の研磨布2とを用いる。The polishing work using this polishing device is performed twice: primary and secondary. In the primary polishing, in order to maintain flatness, a polishing liquid 5 containing abrasive grains and a relatively hard polishing cloth 2 made of non-woven fabric are used. In addition, in the secondary polishing, in order to remove the slight damage remaining on the primary polished surface and to finish the surface to a mirror surface without minute irregularities, a polishing liquid 5 consisting of a chemical liquid that does not contain abrasive grains and a foam layer are used. A relatively soft polishing cloth 2 is used.
ところで、化合物半導体はSiに比して機械的強度が小
さい。例えばGaAsの場合には硬度がSiの半分以下
であり、もろく傷付きやすい。このため研磨液5に砥粒
を入れる1次ポリシングは比較的低い面圧で行われる。By the way, compound semiconductors have lower mechanical strength than Si. For example, in the case of GaAs, the hardness is less than half that of Si, and it is brittle and easily damaged. For this reason, the primary polishing in which abrasive grains are added to the polishing liquid 5 is performed at a relatively low surface pressure.
従って、第3図に示すように1次ポリシングでは、ラッ
ピングにより仕上げた平坦な面が維持できる(第3図(
a))。Therefore, as shown in Figure 3, in the primary polishing, a flat surface finished by lapping can be maintained (Figure 3 (
a)).
しかし、2次ポリシングでは、砥粒なしの化学液と発泡
層のある軟質の研磨布とを用いるため、ウェハ面内で圧
力分布に差が生じやす(、特に、圧力の高くなりやすい
周辺部で研磨が進み、いわゆる「周辺ダレ」8が生じる
(第3図(b))。However, because secondary polishing uses a chemical solution without abrasive grains and a soft polishing cloth with a foam layer, differences in pressure distribution tend to occur within the wafer surface (particularly in the peripheral area where pressure tends to be high). As the polishing progresses, so-called "peripheral sagging" 8 occurs (FIG. 3(b)).
2次ポリシングで周辺部の圧力が高くなりやすい理由は
、研磨布が軟質であるため、研磨布がウェハを包み込ん
だり、ウェハが研磨布に食い込んだりするからであると
いわれている。It is said that the reason why the pressure in the peripheral area tends to increase during secondary polishing is that because the polishing cloth is soft, the polishing cloth may wrap around the wafer or the wafer may dig into the polishing cloth.
このように2次ポリシングで周辺ダレが生じる結果、ウ
ニ表面の平坦度が悪化するという欠点があった。As a result of peripheral sag occurring in the secondary polishing, the flatness of the surface of the sea urchin deteriorates.
平坦度の目安となるTTV(全体の総厚さばらつき)は
、従来のものでは2〜4μmもあった。The TTV (total total thickness variation), which is a measure of flatness, was as high as 2 to 4 μm in conventional products.
[発明が解決しようとする課題]
上述したように、1次ポリシングで比較的低い面圧をか
けて行う従来の研磨方法では、ラッピングで得た平坦度
を1次ポリシングで維持し得ても、2次ポリシングで均
一に研磨されず周辺部にダレが生じるため、平坦度の高
いウェハを得ることができなかった。[Problems to be Solved by the Invention] As described above, in the conventional polishing method in which a relatively low surface pressure is applied in the primary polishing, even if the flatness obtained by lapping can be maintained in the primary polishing, In the secondary polishing, the wafer was not polished uniformly and sag occurred in the peripheral area, making it impossible to obtain a wafer with high flatness.
本発明の目的は、上述した従来技術の欠点を解消して、
2次ポリシングで周辺部に過剰研磨が生じても、ウェハ
面が過剰研磨の影響を受けることなく、高い平坦度が得
られる化合物半導体基板の研磨方法を提供することにあ
る。The purpose of the present invention is to overcome the above-mentioned drawbacks of the prior art,
An object of the present invention is to provide a method for polishing a compound semiconductor substrate in which even if excessive polishing occurs in the peripheral area during secondary polishing, the wafer surface is not affected by the excessive polishing and a high degree of flatness can be obtained.
[課題を解決するための手段]
本発明の化合物半導体基板の研磨方法は、平坦度および
厚さを揃えるためのラッピング後に行われ、ラッピング
によって生じたウェハ表面の加工ひずみ層を除去し、ひ
ずみのない鏡面を得るために2段階で行われるポリシリ
ングであって、1次で硬質の不織布および砥粒を含む研
磨液を用い、2次で軟質の研磨布および化学性の研磨液
を用いて研磨することにより周辺部にダレが生じるポリ
シング方法において、1次ポリシングで基板に100g
/am”以上の面圧を加えることにより、2次ポリシン
グで形成される周辺部のダレを見込んで、ウェハ表面を
凹面状に研磨して、最終的にウェハを平坦化するように
したものである。[Means for Solving the Problems] The compound semiconductor substrate polishing method of the present invention is performed after lapping to make the flatness and thickness uniform, and removes the processing strain layer on the wafer surface caused by lapping, and reduces the strain. Polysilling is performed in two stages to obtain a mirror-like surface.The first step uses a hard non-woven fabric and a polishing solution containing abrasive grains, and the second step uses a soft polishing cloth and a chemical polishing solution. In the polishing method that causes sag in the peripheral area due to polishing, 100g of
By applying a surface pressure of /am'' or more, the wafer surface is polished into a concave shape, taking into account the sag in the peripheral area formed during secondary polishing, and the wafer is finally flattened. be.
[作用コ
本発明は、ポリシングにおいてウェハ面圧を高くすると
ウェハ表面が凹面状になるという事実に着目し、2次ポ
リシングで避けられない周辺部ダレを見越して、1次ポ
リシングで平坦にすることを止め、敢えて凹面状に研磨
するようにしたものである。[Function] The present invention focuses on the fact that when the wafer surface pressure is increased during polishing, the wafer surface becomes concave, and in anticipation of the peripheral sagging that is inevitable in the secondary polishing, the wafer surface is flattened in the primary polishing. This is done by intentionally polishing the surface into a concave shape.
なお、1次ポリシングでウェハ面圧を高くするとウェハ
表面が凹面状になるというメカニズムは、はっきりと分
かっていないが、研磨布が硬質であるため、砥粒がいた
ずらするのではないかと考えられる。The mechanism by which the wafer surface becomes concave when the wafer surface pressure is increased during primary polishing is not clearly understood, but it is thought that the abrasive grains become mischievous because the polishing cloth is hard.
1次ポリシングで、基板にloog/cm2以上の面圧
を加えると、砥粒の作用によりウェハの周辺部の研磨量
が少なく、中央部の研磨量が多くなり、ウェハは表面形
状が凹面状に研磨される。周辺部の研磨量は2次ポリシ
ングでの周辺部のダレを見込んだ量になっている。従っ
て、血圧もそれに合わせて調整される。ウェハ面圧10
0g/an’以上といっても、当然、ウェハが壊れたり
、傷が付くような圧力を越えない範囲である。When a surface pressure of log/cm2 or more is applied to the substrate during primary polishing, the amount of polishing at the periphery of the wafer is small due to the action of abrasive grains, and the amount of polishing at the center is large, resulting in a concave surface shape of the wafer. Polished. The amount of polishing in the peripheral area takes into account the sagging of the peripheral area during secondary polishing. Therefore, blood pressure is also adjusted accordingly. Wafer surface pressure 10
Even if the pressure is 0 g/an' or more, it is within a pressure range that does not cause damage or damage to the wafer.
1次ポリシングでウェハ表面を凹面状に研磨すると、2
次ポリシングで周辺部に過剰研磨が生じても、この研磨
量を見込んで周辺部が肉厚となっているため、ウェハの
周辺部はダレない。When the wafer surface is polished into a concave shape in the primary polishing, 2
Even if excessive polishing occurs in the periphery during the next polishing, the periphery of the wafer will not sag because the periphery is made thicker to account for this amount of polishing.
したがって、ポリシングの最終段階でウェハ表面が平坦
化される。Therefore, the final stage of polishing flattens the wafer surface.
[実施例] 以下、本発明の一実施例を説明する。[Example] An embodiment of the present invention will be described below.
本実施例で用いられる片面ポリシング装置は、第2図に
示した装置と全く同一であるため、その説明を省略する
。The single-sided polishing apparatus used in this embodiment is exactly the same as the apparatus shown in FIG. 2, and therefore its description will be omitted.
ポリシングは、平坦度および厚さを揃えるためのラッピ
ング後に行われ、ウニノー表面の加工ひずみ層を除去し
、ひずみのない鏡面を得るために2段階で行われる。Polishing is performed after lapping to equalize flatness and thickness, and is performed in two stages to remove the processing strain layer on the Uninow surface and obtain a distortion-free mirror surface.
1次ポリシングで、研磨定盤lに接着する研磨布2には
硬質の不織布を用い、研磨液5には砥粒を含ませる。加
圧シリンダ7の加圧力を制御し、ウェハ4に100g/
cm”以上の面圧を加えて、研磨定盤lおよびトッププ
レート3を回転させ、2次ポリシングで形成される周辺
部のダレを見込んで、ウェハ4を凹面状に研磨する。In the primary polishing, a hard nonwoven fabric is used as the polishing cloth 2 that is adhered to the polishing platen l, and the polishing liquid 5 contains abrasive grains. The pressure of the pressure cylinder 7 is controlled and the wafer 4 is coated with 100g/
The polishing surface plate 1 and the top plate 3 are rotated by applying a surface pressure of 1 cm" or more, and the wafer 4 is polished into a concave shape while taking into account the sag in the peripheral area formed by the secondary polishing.
2次ポリシングで、研磨布2には軟質の発泡層を持つ研
磨布を用い、研磨液5には砥粒を含まない化学液を用い
る。そして、研磨定盤lおよびトッププレート3を回転
させて2次ポリシングを行うと、1次ポリシングでウェ
ハ4を凹面状に研磨しであるため、2次ポリシングで周
辺部に過剰研磨が生じても、この研磨量を見込んで周辺
部が肉厚となっているため、ウェハ4の周辺部はダレな
い。In the secondary polishing, a polishing cloth having a soft foam layer is used as the polishing cloth 2, and a chemical liquid containing no abrasive grains is used as the polishing liquid 5. Then, when the polishing surface plate l and the top plate 3 are rotated to perform secondary polishing, the wafer 4 is polished into a concave shape in the primary polishing, so even if excessive polishing occurs in the peripheral area in the secondary polishing. Since the peripheral portion is made thick in consideration of this amount of polishing, the peripheral portion of the wafer 4 does not sag.
従って、最終的にウェハ表面が平坦化される。Therefore, the wafer surface is finally planarized.
以上述べたように本実施例によれば、1次ポリシングで
loog/am’以上の大きな圧力をウェハ4に与えて
周辺部の研磨量少なくするようにしたので、2次ポリシ
ングで過剰研磨が生じても、面内研摩量差がカバーされ
ることになり、したがって、ラッピングで得られたウニ
表面の平坦度がポリシングによって悪化するということ
がない。As described above, according to this embodiment, a large pressure equal to or greater than log/am' is applied to the wafer 4 in the primary polishing to reduce the amount of polishing in the peripheral area, so that overpolishing occurs in the secondary polishing. However, the difference in the amount of in-plane polishing is covered, and therefore, the flatness of the surface of the sea urchin obtained by lapping will not be deteriorated by polishing.
なお、上記した実施例では研磨布として1次で不織布を
、2次で発泡層を持つ布を用いた場合について述べたが
、本発明はこれに限定されるものではなく、例えば1次
に比較的硬質な人工皮革等を、2次に比較的軟質で粘弾
性のあるその他の研磨布等を用いることもできる。In addition, in the above-mentioned example, a case was described in which a nonwoven fabric was used as the primary polishing cloth and a cloth with a foam layer was used as the secondary polishing cloth, but the present invention is not limited to this. It is also possible to use a relatively soft and viscoelastic polishing cloth, etc., as a secondary polishing cloth.
さて、上記のような装置を用いてGaAsウェハをのポ
リシングした場合の具体例についてのべる。Now, a specific example of polishing a GaAs wafer using the above-mentioned apparatus will be described.
ウェハとしてLEC法(′tfi、体封止引上げ法)に
より製造された、直径2インチ、厚さ550μmのGa
Asウェハを用いた。A Ga wafer with a diameter of 2 inches and a thickness of 550 μm was manufactured by the LEC method ('TFI, body-sealing pulling method).
An As wafer was used.
先ず、ラッピングして平坦度と厚さを揃えた後、エツチ
ング処理をしてラッピングにより生じた加工ひずみによ
る反りを取り除き、厚さ430μmまで研磨し、直径3
00xxのセラミック製トッププレート3にウェハ4を
ワックス6で10枚接着した。First, after lapping to make the flatness and thickness uniform, etching is performed to remove the warpage caused by processing strain caused by lapping, and the etching is polished to a thickness of 430 μm.
Ten wafers 4 were adhered to the ceramic top plate 3 of 00xx with wax 6.
1次ポリシングでは上述したように、砥粒入すの研磨液
5と不織布の研磨布2を使用し、ウェハ4に面圧150
g/cm”を加え、20μmポリシングを行い、第1
図(a)に示すような1〜2μm凹状の表面形状を得た
。As mentioned above, in the primary polishing, a polishing liquid 5 containing abrasive grains and a non-woven polishing cloth 2 are used, and a surface pressure of 150 is applied to the wafer 4.
g/cm” and then polished to 20 μm.
A concave surface shape of 1 to 2 μm as shown in Figure (a) was obtained.
次に、2次ポリシングでは、砥粒を含まない研磨液5と
発泡層を持つ研磨布2を使用し、10μmポリシングを
行い、第1図(b)に示すような平坦な平面形状を得た
。Next, in secondary polishing, 10 μm polishing was performed using a polishing liquid 5 that did not contain abrasive grains and a polishing cloth 2 that had a foam layer, and a flat planar shape as shown in FIG. 1(b) was obtained. .
ウェハ4を装置から取り外し、洗浄した後平坦度測定を
行ったところ、TTVは1〜2μmであり、従来の2〜
4μmを大幅に改善することができた。When the wafer 4 was removed from the apparatus, cleaned, and then measured for flatness, the TTV was 1 to 2 μm, which was higher than the conventional 2 to 2 μm.
4 μm could be significantly improved.
また、ウェハを洗浄後、スポットライト下でウェハ表面
を観察したところ、特に傷は発見されなかった。Further, after cleaning the wafer, the wafer surface was observed under a spotlight, and no particular scratches were found.
このように、本実施例によれば高精度な鏡面ウェハを得
ることができるので、特に、ウェハプロセスにおいて益
々要求が厳しくなっているパターン微細化対応にも十分
答えることができる。In this way, according to the present embodiment, a mirror-finished wafer with high precision can be obtained, and therefore, it is possible to sufficiently meet requirements for pattern miniaturization, which is becoming increasingly demanding in wafer processes.
[発明の効果]
本発明によれば、基板に100g7cm”以上の面圧を
加えて、基板表面を凹面状に研磨したので、2次ポリシ
ングで周辺部に過剰研磨が生じても、基板表面が過剰研
磨の影響を受けることなく、平坦度の極めて高い基板を
得ることができる。[Effects of the Invention] According to the present invention, the surface of the substrate is polished into a concave shape by applying a surface pressure of 100g7cm or more to the substrate, so even if excessive polishing occurs at the periphery during secondary polishing, the surface of the substrate remains unchanged. A substrate with extremely high flatness can be obtained without being affected by excessive polishing.
第1図は本発明による化合物半導体基板の研磨方法の一
実施例により得られた1次ポリシング。
2次ポリシングのウェハ表面形状を示す説明図、第2図
は本発明の研磨方法にも用いられる従来の片面ポリシン
グ装置例の正面図、第3図は従来方法により得られた1
次ポリシング、2次ポリシングのウェハ表面形状を示す
説明図である。
■は定盤、2は研磨布、4は化合物半導体基板としての
ウェハ 5は研磨液、7は基板に面圧を加える加圧シリ
ンダ、8はウェハ周辺部に発生したダレである。
(a)1&ネ°リシンク°の表面体
0m
(b)2欠本°リシンク゛の表面亙m
本°リシンタ゛装−にの正「i外り
第2図FIG. 1 shows primary polishing obtained by an embodiment of the compound semiconductor substrate polishing method according to the present invention. An explanatory diagram showing the wafer surface shape in secondary polishing, FIG. 2 is a front view of an example of a conventional single-sided polishing apparatus which is also used in the polishing method of the present invention, and FIG. 3 is a diagram showing the wafer surface shape obtained by the conventional method.
FIG. 4 is an explanatory diagram showing the wafer surface shape of secondary polishing. 2 is a surface plate, 2 is a polishing cloth, 4 is a wafer as a compound semiconductor substrate, 5 is a polishing liquid, 7 is a pressure cylinder that applies surface pressure to the substrate, and 8 is a sag generated around the wafer. (a) Surface area of 1&resink 0m (b) Surface height of 2 missing parts resink
Claims (1)
面圧で押し付けて研磨することにより、ひずみのない鏡
面を基板表面に得るポリシングであって、1次ポリシン
グで硬質の研磨布および砥粒を含む研磨液を用い、2次
ポリシングで軟質の研磨布および化学性の研磨液を用い
て研磨すると基板表面の周辺部が過剰研磨される化合物
半導体基板の研磨方法において、 上記1次ポリシングで、2次ポリシングで生じる周辺部
の過剰研磨量を見込んで、基板を100g/cm^2以
上の面圧で押し付け、基板表面を凹面状に研磨して、最
終的に基板を平坦化するようにしたことを特徴とする化
合物半導体基板の研磨方法。[Claims] A polishing method that obtains a distortion-free mirror surface on the substrate surface by pressing a compound semiconductor substrate against a polishing cloth provided on a rotating surface plate with a predetermined surface pressure. In a method for polishing a compound semiconductor substrate, the peripheral part of the substrate surface is excessively polished when polishing using a soft polishing cloth and a chemical polishing liquid in secondary polishing, using a polishing cloth and a polishing liquid containing abrasive grains. In the first polishing described above, the substrate is pressed with a surface pressure of 100 g/cm^2 or more to allow for excessive polishing of the peripheral area that will occur in the second polishing, and the substrate surface is polished into a concave shape, and finally the substrate is polished. A method for polishing a compound semiconductor substrate, characterized by flattening the substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2936289A JPH02208931A (en) | 1989-02-08 | 1989-02-08 | Polishing process for compound semiconductor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2936289A JPH02208931A (en) | 1989-02-08 | 1989-02-08 | Polishing process for compound semiconductor substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02208931A true JPH02208931A (en) | 1990-08-20 |
Family
ID=12274070
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2936289A Pending JPH02208931A (en) | 1989-02-08 | 1989-02-08 | Polishing process for compound semiconductor substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02208931A (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0658401A1 (en) * | 1993-12-14 | 1995-06-21 | Shin-Etsu Handotai Company Limited | Polishing member and wafer polishing apparatus |
EP0791953A3 (en) * | 1996-01-31 | 1998-07-15 | Shin-Etsu Handotai Company Limited | Method of manufacturing semiconductor wafers |
US5989107A (en) * | 1996-05-16 | 1999-11-23 | Ebara Corporation | Method for polishing workpieces and apparatus therefor |
US6343978B1 (en) | 1997-05-16 | 2002-02-05 | Ebara Corporation | Method and apparatus for polishing workpiece |
US6354922B1 (en) | 1999-08-20 | 2002-03-12 | Ebara Corporation | Polishing apparatus |
US6413156B1 (en) | 1996-05-16 | 2002-07-02 | Ebara Corporation | Method and apparatus for polishing workpiece |
KR100408537B1 (en) * | 1999-11-05 | 2003-12-06 | 엔이씨 일렉트로닉스 코포레이션 | Polishing process for use in method of fabricating semiconductor device |
US6682408B2 (en) | 1999-03-05 | 2004-01-27 | Ebara Corporation | Polishing apparatus |
JP2014122699A (en) * | 2012-11-21 | 2014-07-03 | Nippon Steel Sumikin Materials Co Ltd | Method for manufacturing ceramic coating roller |
-
1989
- 1989-02-08 JP JP2936289A patent/JPH02208931A/en active Pending
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0658401A1 (en) * | 1993-12-14 | 1995-06-21 | Shin-Etsu Handotai Company Limited | Polishing member and wafer polishing apparatus |
EP0791953A3 (en) * | 1996-01-31 | 1998-07-15 | Shin-Etsu Handotai Company Limited | Method of manufacturing semiconductor wafers |
US5989107A (en) * | 1996-05-16 | 1999-11-23 | Ebara Corporation | Method for polishing workpieces and apparatus therefor |
US6413156B1 (en) | 1996-05-16 | 2002-07-02 | Ebara Corporation | Method and apparatus for polishing workpiece |
US6343978B1 (en) | 1997-05-16 | 2002-02-05 | Ebara Corporation | Method and apparatus for polishing workpiece |
US6682408B2 (en) | 1999-03-05 | 2004-01-27 | Ebara Corporation | Polishing apparatus |
US6878044B2 (en) | 1999-03-05 | 2005-04-12 | Ebara Corporation | Polishing apparatus |
US7632378B2 (en) | 1999-03-05 | 2009-12-15 | Ebara Corporation | Polishing apparatus |
US6354922B1 (en) | 1999-08-20 | 2002-03-12 | Ebara Corporation | Polishing apparatus |
KR100408537B1 (en) * | 1999-11-05 | 2003-12-06 | 엔이씨 일렉트로닉스 코포레이션 | Polishing process for use in method of fabricating semiconductor device |
JP2014122699A (en) * | 2012-11-21 | 2014-07-03 | Nippon Steel Sumikin Materials Co Ltd | Method for manufacturing ceramic coating roller |
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