JPH02188024A - Level shifting circuit - Google Patents

Abstract

PURPOSE:To facilitate inverting operation even when an input signal is at low level and to improve fastness and design performance by accelerating switching operation in input signal switching by 1st and 2nd current supply circuits. CONSTITUTION:When the input signal Si varies to a high level V2, a transistor (TR) 1 turns off and a TR 2 turns on. Therefore, both TRs 2 and 4 turn on. At such a time, the input signal Si is at the high level V2, so a TR 42 turns on. The output signal So at an output terminal 13, on the other hand, is still at the high level, so a TR 41 also turns on and a current flows to a TR 43. Therefore, the gate potential of the TR 4 rises and its ON resistance increases. Consequently, the potential at the output terminal 13 falls and the ON resistance of a TR 3 decreases, positive feedback is provided, so the switching operation of a level shifting circuit is accelerated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a level shift circuit, and particularly to a level shift circuit that is effective for low voltage operation and suitable for high speed operation.

[Prior Art] A circuit shown in FIG. 4 has been known as this type of level shift circuit. This level shift circuit includes a CMOS inverter 12 that inverts an input signal Si input through an input terminal 11, an inverted input signal St of this inverter 12, and the input signal St inputted to respective gates and whose sources are connected to a common ground. Enhancement N channel MOS transistors 1.2 and 1.2 are respectively connected to the drain sides of these MOS transistors 1.2 as loads, their gates and drains are cross-connected, and their sources are commonly connected to a power supply V. Channel M
The output terminal 13 is composed of an MOS transistor 3.4, and the drain of the MOS transistor 2 is used as an output terminal 13.

Next, the operation of this circuit will be explained.

The input signal Si input from the input terminal 11 is a CMOS
It is inverted by the inverter 12 and becomes Si.

Signals Si and SL are input to the gates of N-channel type MOS transistors 1.2, respectively. Here, if the power supply voltage of the CMOS inverter 12 is 2, the signals Si and Clove will have voltage values between the power supply voltage 2 and GND (OV), so the signals St and S will be 5i=V2. Si°=0. Or, S i =O, Hyakugo = ■2. Therefore, the operations of transistors 1 to 4 in the steady state are as shown in Table 1 below.

In Table 1, the output signal So whose level is shifted from 0 to 2 with respect to the level 0 to 2 of the input signal Si is output to the output terminal 13.
It will be obtained from However, the threshold voltage VTN of N-channel MO3) transistors 1 and 2 is V2>VTN>
Set to 0.

Now, consider a transient state when transistor 1 changes from OFF to ON and transistor 2 changes from ON to OFF. Transistor 1 is off, transistor 2
When is ON, transistor 3 is ON and transistor 4 is OFF. Here, transistor 1 changes from OFF to ON, and transistor 2 changes from ON to OFF.
When it changes to
It becomes F state. Therefore, the output terminal 13 remains at a low level and does not change immediately. On the other hand, since transistors 1 and 3 are both in the ON state, if the on-resistance of the transistor is smaller than the on-resistance of transistor 3, a sufficient voltage drop will occur between the drain and source of transistor 3. The potential at the connection point P decreases. As a result, a positive feedback occurs as transistor 4 turns on → the potential of output terminal 13 rises → the on-resistance of transistor 3 increases → the potential of point P further decreases → the on-resistance of transistor 4 decreases, and finally the transistor 3
is turned off, and transistor 4 is turned on. Therefore, the output terminal 13 changes from low level to high level. Even when the state changes of transistors 1 and 2 are reversed, the inversion operation is performed through exactly the same process.

In this way, in the conventional level shift circuit shown in FIG. 4, when N-channel MO3 transistor 1 (or 2) is turned on, the on-resistance of transistor 1 (or 2) is (or 4) needs to be sufficiently smaller than the on-resistance. If this condition is not met, the operating speed will be extremely slow or malfunction will occur.

[Problems to be Solved by the Invention] In the conventional level shift circuit described above, in a transient state where transistor 1 is turned on from OFF, transistor 3 also remains on, so that the connection point P between the two remains on.
In order to lower the potential of N-channel MOS transistor l, the on-resistance of N-channel MOS transistor
It must be sufficiently smaller than the on-resistance of transistor 3. In other words, in this level shift circuit, the drain current (Iol) flowing through transistor 1 must be larger than the drain current (ID3) flowing through transistor 3. In general, the steady current Io flowing through a transistor
is expressed as in equation (1).

I o = K (Vo Vt) ”・
(1) where K is the conductivity coefficient of the transistor, VG is the gate voltage, and V↑ is the threshold voltage. Therefore, drain current ID1. ID3 is determined by formulas (2) and (3), respectively. If V tp l = 0.5 V, then at least Kl/
must be set to 3 > 14.06, with a margin of 2
If it is viewed twice, K 1/K 3 > 28.12. is generally expressed as =eεμW/(2dL). Here, e is the electron charge, ε is the dielectric constant of the semiconductor, μ is the carrier mobility of the semiconductor, d is the thickness of the oxide film, W is the gate width, and L is the gate length. Here, in general, ε and d are the same for N-channel MO3 and P-channel MO8, and μ is about twice larger in N-channel MO3 than in P-channel MO3, so K 1 / K 3 > 28.12
The condition (subscript is transistor number) is (W/L) 1/(W/ L ) 3 > 14.06 using W/L.
(The subscript is the transistor number).

However, since there is a minimum required area for a transistor, trying to satisfy the above condition results in an increase in the area of the first and second transistors (1, 2), which leads to an increase in the layout area. There was a point.

Furthermore, as the first and second transistors become larger, the gate capacitance of these transistors also becomes larger, so in order to ensure switching speed, there is a problem in that the inverter and transistor in the preceding stage must be made larger.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a level shift circuit that is capable of high-speed switching and has a small layout area.

[Means for Solving the Problems] A level shift circuit according to the present invention includes first and second level shift circuits of a first conductivity type whose sources are commonly connected to a first power supply and whose gates input mutually inverted input signals. a second field effect transistor having a drain connected to the drain of the first field effect transistor, a source connected to a second power supply, and a gate connected to the drain of the second field effect transistor; a third field effect transistor of conductivity type, a drain connected to the drain of the second field effect transistor, a source connected to the second power supply, and a gate connected to the drain of the first field effect transistor; Gate potentials of the connected fourth field effect transistor of the second conductivity type and the first and fourth transistors are input, and these gate potentials turn on the first and fourth field effect transistors, respectively. and a first current supply circuit that supplies a drain current to the second field effect transistor when the potential is such that the second field effect transistor is turned off, and a gate potential of the second and third transistors. and a second current supply circuit that supplies a drain current to the first field effect transistor when the potential is such that the second and third field effect transistors are turned on and off, respectively. Features.

[Operation] According to the present invention, the gate potentials of the first and fourth transistors are monitored by the first current supply circuit, and these gate potentials turn the first and fourth transistors on and off, respectively. When the voltage is at the potential, that is, when the first transistor is in a transient state where it is switched from off to on, a head drain current of the second transistor is supplied from the first current supply circuit. This increases the drain-source voltage of the second transistor, which acts to turn off the third transistor. Therefore, the potential at the connection point between the first and third transistors decreases, the fourth transistor is turned on, and the output is switched at high speed.

Also when the second transistor switches from off to on,
The second current supply circuit achieves the same effect as described above and provides high-speed switching operation.

According to the present invention, there is no need to consider the size ratio between the first transistor and the third transistor and the size ratio between the second transistor and the fourth transistor, and the layout area can be reduced.

[Examples] Examples of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing the configuration of a level shift circuit according to an embodiment of the present invention. Note that in FIG. 1, the same parts as in FIG. 4 are given the same numbers, and explanations of overlapping parts will be omitted.

The level shift circuit shown in FIG. 1 differs from the conventional circuit shown in FIG. 4 in that current supply circuits 21 and 22 are newly provided. The current supply circuit 21 inputs the gate potential of the N-channel MOS transistor 1 and the gate potential of the P-channel MOS transistor 4, and when both gate potentials are at a high level, the current supply circuit 21 supplies the N-channel MOS transistor 2 with A current I is supplied to increase the drain current ID2. Current supply circuit 22
Similarly, the gate potential of the N-channel MOS transistor 2 and the gate potential of the P-channel transistor 3 are input, and when both of these gate potentials are at a high level, the N-channel MOS transistor 1 is
A current I' is supplied to increase the drain current ID. Note that these current supply circuits 21.
The power supply V of 22 may be the same as the power supply ■1 or ■2,
It may also be a different value.

FIG. 2 is a circuit diagram showing a more detailed configuration example of the current supply circuits 21 and 22 in FIG. 1. The current supply circuit 21 includes an enhancement N-channel type MOS transistor 31 which is controlled on and off by the drain potential of the transistor 1, and an enhancement N-channel MOS transistor 31 connected in series with the transistor 31 on the drain side of the transistor 31 and turned on and off by the gate potential of the transistor 1. Off-controlled enhancement N
A channel type MOS transistor 32, an enhancement P channel type MO3) transistor 33 whose gate and source are connected between the transistor 32 and the power supply ■l, and a gate connected to the transistor 33 to form a current mirror circuit. and the source are transistor 3
Enhancement P-channel type MO whose drain is connected in common with transistor 3 and whose drain is connected to the drain of transistor 2.
It is composed of an S transistor 34. The current supply circuit 22 is also configured in substantially the same manner.

That is, the current supply circuit 22 has an enhancement N that is controlled on and off by the drain potential of the transistor 2.
A channel type MoS transistor 41, an enhancement N-channel type MOS transistor 42 connected in series with the transistor 41 on the drain side of this transistor 41 and controlled on/off by the gate potential of the transistor 2, this transistor 42 and a power supply V, An enhancement P-channel type MOS transistor 43 is connected between the transistors 43 and 43, and the gate and source are commonly connected to the transistor 43 in order to configure a current mirror circuit together with this transistor 43, and the drain is connected to the transistor 1. The transistor 44 is an enhancement P-channel type MO3) transistor connected to the drain of the transistor 44.

Next, the operation of the level shift circuit according to this embodiment configured as described above will be explained.

First, in a steady state, the states of each transistor 1 to 4 are as shown in Table 2 below.

Table 2 Also, in this steady state, the states of each of the transistors 31 to 34 and 41 to 44 constituting the current supply circuits 21 and 22 are as shown in Table 3 below.

Table 3 Therefore, no current flows steadily.

Next, the operation of this circuit in a transient state when the input signal Si changes from OV to V2V will be described. First, when the signal Si changes to V2, the transistor 1 changes from ON to OFF.
FF, transistor 2 changes from OFF to ON. Therefore, transistors 2 and 4 are both turned on. At this time, the input signal Si is at a high level (v2), so the transistor 42 is turned on. On the other hand, since the output signal So at the output terminal 13 is still at a high level,
Transistor 41 is also turned on, and the current shown in the figure flows through transistor 43. As a result, current n11 flows through transistor 44.

However, n is (W/L) 44 (W/L) 4
3 (the subscript is the transistor number). Therefore, the drain potential of transistor 1, that is, the gate potential of transistor 4 increases, and the on-resistance of transistor 4 increases. As a result, the potential of the output terminal 13 is lowered and the on-resistance of the transistor 3 is reduced, resulting in positive feedback, which facilitates the switching operation of the level shift circuit described above. Also, the input signal Si is ■2
Even when changing from OV to OV, the current supply circuit 21 facilitates a similar switching operation.

In this way, according to the present level shift circuit, the level of the input complementary signal (■2) is low, that is, the level of the input complementary signal (■2) is low, that is, the level of the
Even if the on-resistance of transistor 1.
2 can be reduced in size. Moreover, the current supply circuits 21 and 22 operate only when the input signal Si and the output signal So are in a transient state of high level or low level, and do not function in a steady state, which adversely affects the normal level shift operation. It will not affect you.

FIG. 3 is a circuit diagram of a level shift circuit according to another embodiment of the present invention. This circuit is a circuit in which the transistors 33 and 43 in the circuit shown in FIG. 2 described above are replaced with resistive elements 51 and 52.

In this circuit as well, when the input signal St is switched, the transistors 31, 32 or 41, 42 are simultaneously turned on, and the voltage drop generated across the resistor element 51 or 52 turns on the transistor 34 or 44, causing the transistor 1 or 2 to turn on. Since the potential can be supplied to the level shift circuit, the switching operation of the level shift circuit can be facilitated and high-speed operation can be realized, similarly to the above-described embodiment.

In each of the embodiments described above, the N-channel MOS transistor is replaced with a P-channel MO8) transistor, and the P-channel MO3) transistor is replaced with an N-channel MO3) transistor.
O3) It goes without saying that the same effect can be achieved even if it is replaced with a transistor.

[Effects of the Invention] As explained above, the present invention facilitates the switching operation when the input signal is switched in the first and second current supply circuits, so that the inversion operation can be performed even when the input signal is at a low level. Therefore, it is possible to provide a level shift circuit which is easy to operate and has improved speed and design.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a level shift circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a more specific example of the circuit in FIG. 1, and FIG. 3 is another embodiment of the present invention. FIG. 4 is a circuit diagram showing the structure of a conventional level shift circuit. 1.2, 31, 32. 41, 42; N-channel MOS transistor, 3, 4.33, 34, 43° 44; P-channel MO31-transistor, 11; Input terminal, 12; Inverter, 13: Output terminal, 21 .22; Power supply circuit, 51, 52; Resistance element 51.52. Figure 13; Output 1V. Funeral map

Claims (1)

[Claims] (1) A first transistor of a first conductivity type whose sources are commonly connected to a first power supply and whose gates receive mutually inverted input signals.
and a second field effect transistor, a drain connected to the drain of the first field effect transistor, a source connected to a second power supply, and a gate connected to the drain of the second field effect transistor. a third field effect transistor of a second conductivity type;
a fourth field effect transistor of a second conductivity type, which is connected to the drain of the field effect transistor, has a source connected to the second power supply, and has a gate connected to the drain of the first field effect transistor; When the gate potentials of the first and fourth transistors are input and these gate potentials are potentials that turn the first and fourth field-effect transistors on and off, respectively, the second field-effect transistor The first one supplies drain current to the transistor.
and the gate potentials of the second and third transistors, and when these potentials are potentials that turn the second and third field effect transistors on and off, respectively, 1. A level shift circuit comprising: a second current supply circuit that supplies a drain current to the first field effect transistor.