JPH02186850A - Frame synchronization circuit - Google Patents

Abstract

PURPOSE:To easily execute frame synchronization in fast transmission by performing a one-bit shift processing related to the frame synchronization by using a clock of respective line rate after multiplex separation. CONSTITUTION:An AND gate 6 on the other side to input the output of a decoder circuit 4 after the multiplex separation and a synchronous line selection pulse, a synchronous pattern generator 7 provided with clock width after the multiplex separation, and a noncoincidence circuit 8 which performs the one-bit shift of a line separation circuit 10 by resetting a D flip-flop at a stage preceding by one from the final stage of a counter in the line separation circuit 10 when noncoincidence is detected by comparing the output of the synchronous pattern generator 7 with that of the AND gate 6 on the other side are provided. Therefore, all the one-bit shift processings are performed by a separation line clock at low speed after the multiplex separation. In such a way, the execution of the frame synchronization can easily be performed even when transmission speed is accelerated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame synchronization circuit, and particularly to a frame synchronization circuit for high-speed digital transmission.

[Prior art] Fig. 4 shows a frame called a 1-bit shift digital synchronization method, which is shown in "Synchronization method in time division multiplex code transmission" described in, for example, Journal of the Institute of Electrical Communication, Vol. 43, No. 12 (December 1960). This is a conventional example of a synchronous circuit. In FIG. 4, a bit synchronization circuit (1) that reproduces a timing signal from an input multiplexed code sequence, a logic gate (2) that inhibits the output clock of this bit synchronization circuit (1),
A line separation circuit (3) that counts the output clock pulses of this logic gate (2) and generates the pulses necessary for line separation.
and a decoder circuit (4) that separates the input multiplex code sequence into each line based on the output pulses of the line separation circuit (3).
The frame synchronization line selection pulse, which is one output of the line separation circuit (3), is ANDed with the input clock of the line separation circuit (3), and one AND gate (5) generates a synchronization pattern generation clock. The other AND gate (6) that ANDs the line selection pulse and the input multiplexed code sequence, and the synchronization pattern generator (7) that generates a frame synchronization pattern from the output of the AND gate (5).
), a mismatch circuit (8) that compares the synchronization pattern with the multiplexed code sequence input at the frame synchronization position and detects a mismatch, and a delay circuit (9) that appropriately delays the output of the mismatch circuit (8). is shown, and one bit of the clock is inhibited by the logic gate (2) at the output of this delay circuit (9).

Next, the operation will be explained. The transmitted multiple code series is bit synchronized by a bit synchronization circuit (1) and a clock pulse is generated.

This clock pulse advances a line separating circuit consisting of a counting circuit to generate a separating pulse for each line or each digit.

In addition, the synchronous line selection pulse hO, which is the output of the line separation circuit (3), is generated by selecting the code at the time of synchronization on the receiving side from among the multiple code sequences in the other AND gate (6), and in the other AND gate (5). Then, the timing is determined by the clock and the synchronization pattern generator (7) is operated. The output of the synchronization pattern generator (7) is compared with the output of the other AND gate (6) in the mismatch circuit (8), and since they always match during normal synchronization, normal operation continues. When out-of-synchronization occurs due to noise or the like, the other AND gate (6) erroneously selects the code of the other line, and the mismatch circuit (8) generates a pulse every time there is mismatch. This pulse passes through a 1-bit delay circuit (9), inhibits the clock by 1 bit at the logic gate (2), and shifts the line isolation circuit (3) by 1 bit. This shift process is repeated several times to return to the synchronized state.

[Problem to be solved by the invention] Since the conventional frame synchronization circuit had the above configuration, the transmission speed became high, and it was difficult to adjust a 1-bit delay circuit for transmission of several gigabits/second. Therefore, when disabling one bit of the clock, it is necessary to use a high-speed element, resulting in a problem of increased cost.

This invention was made with the aim of solving this problem, and it performs 1-bit shift processing related to frame synchronization using the clock of each line rate after demultiplexing, thereby facilitating frame synchronization in high-speed transmission. It is an object of the present invention to obtain a frame synchronization circuit that can be realized and constructed at a low cost as a whole.

[Means for Solving the Problems] The frame synchronization circuit according to the second invention includes the other AND gate that inputs the decoder circuit output after demultiplexing and the synchronization line selection pulse, and the synchronization pattern having the clock width after demultiplexing. The output of the synchronization pattern generator is compared with the output of the other ant gate, and when a mismatch is detected, the D-flip-flop in the stage before the final stage of the counter in the line separation circuit is reset. and a mismatch circuit that shifts the line separation circuit by 1 bit.

[Function] According to the present invention, all 1-bit shift processing is performed using a low-speed separated line clock after demultiplexing, so there is no need for a delay circuit, and even if the transmission speed becomes high, the frame synchronization circuit is not required. It is possible to easily realize the circuit, and to configure the circuit using inexpensive elements.

[Example] Next, the present invention will be described in more detail based on an example shown in FIGS. 1 to 3.

In FIG. 1, a bit synchronization circuit (1) that reproduces a clock from a multiplexed code sequence, a line separation circuit (10) that generates a separation pulse, a low-speed line clock, and a synchronous line selection pulse based on this clock; A decoder circuit (4) separates multiple code sequences into respective lines based on separation pulses from the line separation circuit (10), and a line separation circuit (10).
) has a retiming function by synchronizing the synchronous line selection pulse generated by the low-speed line clock, and the logic of the data of a specific channel and the synchronous line selection pulse after separating the multiplexed code sequence. The other AND gate (6) that calculates the sum, and the synchronous pattern generator (7) that generates a synchronous pattern by the output of the AND gate (5), and the output of the AND gate (6) and the synchronous pattern generator (7)
) and a mismatch circuit (8) which generates a pulse when there is a mismatch. Further, FIG. 2 shows the line separation circuit (10) in detail, and in FIG. 2, (11a), (llb), (11C), (11d)
is a D-flip-flop, which is continuously connected for the number of lines to be multiplexed. Out of each output of this D-flip-flop, all outputs except the final stage (11d) are used as inputs, and a NOR is taken and the first stage D- flip flop (lla)
A separate line clock generation circuit (13) that generates a line clock after demultiplexing from the output of a counter circuit consisting of a NOR gate (12), D-flip-flops (11a) to (11d), and a NOR gate (12). and,
A counting circuit (14) is shown which divides the frequency of the separated line clock generation circuit (13) by an appropriate counting circuit and outputs a synchronization line selection pulse indicating the position of the frame synchronization pulse.

First, in FIG. 1, the transmitted multiple code series is bit synchronized as in the conventional example, and a clock pulse is generated. Using this clock pulse as input, the line separation circuit (10) generates pulses and associated clocks for separating the multiple code series into each line, and the decoder circuit (4) converts the multiple code series into serial and parallel signals. Separate into two lines. Up to this point, the configuration is exactly the same as the conventional method. When the speed of multiple code sequences increases to several gigabits/second or more, this bit synchronization circuit (1
) It is difficult to perform processes such as synchronization verification and hunting using the output clock, but here these processes are performed using the demultiplexed data and clock.

The line separation circuit (10) generates a synchronization line selection pulse (separation line clock 1 bit width) at the position of the frame synchronization pulse by counting the counting circuit therein, as in the conventional case, and in one AND gate (5), This pulse is synchronized with the separate line clock and a synchronization pattern generator (7)
Enter.

In the synchronous pattern generator, one of these AND gates (5)
A predetermined synchronization pattern is generated based on the output of the synchronization pattern. On the other hand, the other AND gate (6) calculates the logical sum of the above-mentioned synchronization line selection pulse and the data of a specific channel from which a frame synchronization pulse should be output when the multiplexed code sequence is normally separated, and calculates the discordance circuit ( 8), enter
The output of the synchronous pattern generator (7) and the mismatch circuit (8)
), and if they do not match, a shift pulse with a width of one bit of the separated line clock is generated. When this shift pulse is input to the line separation circuit (10), the counter in the line separation circuit (10) is shifted by one bit, and the phase of the separation pulse input to the decoder circuit (4) is shifted. The output separation line is shifted to (4). In this way, the channel position where normal frame synchronization has been inserted is shifted until it becomes the correct position, and synchronization is restored.

As for a 1-bit shift, the configuration of the line separation circuit (10) shown in FIG. 2 makes it possible even when the shift pulse has a width of 1 bit for the separation line. Below is the line separation circuit (10
) operation is shown.

FIG. 3 shows a simple time chart when the number of multiplexed lines is four. Since the number of multiplexed lines is 4, the D-flip-flop (hereinafter referred to as D-FF) (1
The number of cascaded stages in 1) is 4, and the output signal of the NOR gate (12) whose inputs are the D-FF outputs of the first, second and third stages is input to the input of the first stage D-FF (lla). The operation of this counter is a conventionally known operation, and is normally 4
Only one of the three D-FFs becomes "1" and is shifted to the right in order. This pulse is used to separate the lines in the decoder circuit (4). Here, the separated line clock rises at the rising edge of the first-stage flip-flop output, falls at the rising edge of the third-stage flip-flop output, and the separated data is triggered by the rising edge of the first-stage flip-flop output. In this case, the synchronization line selection pulse indicating the position where the frame synchronization signal should be input is also output at the expected frame synchronization position, triggered by the rising edge of the first-stage D-FF (lla) output. This is a case where it is assumed that

In FIG. 3, a synchronous line selection pulse is now generated at position A, and both AND gates (5), (6) in FIG.
When a mismatch is detected in the mismatch circuit (8) via the synchronous pattern generator (7), the shift pulse indicates "1". When the shift pulse becomes 1", the third stage D- in Fig. 2
After resetting the FF (11c), the pulse in the * section shown in the time chart in Figure 3 disappears, and all D-FF
becomes “0”, and the first stage D-FF (l
Only signal la) becomes "1" and the phase of the pulse for the decoder is increased by 1 bit, making it possible to realize the desired 1-bit shift function.

The above operation is the delay time α until the shift pulse is generated.
This is possible as long as it is within the delay time of 3 bits of the transmission line clock, and the 1-bit shift processing for mismatch detection and hunting does not require the use of the high-speed transmission line clock, and can only be processed using the separate line clock. It is possible to realize high-speed operation, and to use inexpensive elements such as gates.

Note that although the above embodiment shows a case where the frame synchronization pattern exists in only one line separation channel, it may exist in a plurality of line separation channels.

At this time, the other game 4 (6) performs multiple logical sums in parallel with the synchronization line selection pulse indicating the position where each frame synchronization pattern should exist for all the channels for which the frame synchronization pattern is expected. The synchronous pattern generator (7) outputs a plurality of parallel outputs, and a mismatch circuit compares the plurality of bits.

Furthermore, in the above embodiment, the position at which the counter is reset by the shift pulse is realized by resetting the D-FF one stage before the final stage of the cascade-connected D-FFs. If the method is to eliminate the shifting pulse by the output of the DFF one stage before the final stage, then this shift pulse and the D-F one stage before the final stage
Other methods such as performing F output and logic tLn may also be used. Furthermore, if the system configuration allows a shift other than 1 bit (for example, 2 bits, 3 bits), the position of the D-FF to be reset can be reset not only in the stage before the final stage but also in other D-FFs. I don't mind.

In the embodiment, for convenience of explanation, the separated line clock rises at the rising edge of the first-stage D-FF (lla) output, and falls at the rising edge of the third-stage D-FF (llc) output, or is set at another location. It doesn't matter if it is.

[Effects of the Invention] As explained above, the present invention detects discrepancies in frame synchronization using demultiplexed channel data, processes using a clock after line separation, and uses D as a basic counter of a line separation circuit. - Flip-flops are connected in series for the number of multiplex lines, and all D-flip-flop outputs except for the final stage are configured with a NOR gate (a conventionally used counter that is input to the D-flip-flop in the labor-saving stage), and has a 1-bit shift function. is configured by resetting the D-flip-flop one stage before the final stage with a 1-bit width shift pulse of the clock after line separation due to mismatch detection, so mismatch detection and 1-bit shift processing are slow after demultiplexing. Since it operates using a clock, synchronization can be realized even when the multiplex transmission speed becomes high, and it has the advantage that inexpensive elements with slow processing speeds can be used.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a frame synchronization circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing a detailed example of the line separation circuit in FIG. 1, and FIG. 3 is a block diagram of a frame synchronization circuit according to an embodiment of the present invention. FIG. 4 is a timing diagram showing an example of operation. FIG. 4 is a block diagram showing a conventional frame synchronization circuit. In the figure, (1) is a bit synchronization circuit, (2) is a logic gate, (3) is a line separation circuit, (4) is a decoder circuit,
(5) is one AND gate, (6) is the other AND gate, (7) is a synchronous bang generator, (8) is a mismatch circuit, (9) is a delay circuit, (10) is a line separation circuit, ( 11
) is a D-flip-flop, (12) is a Noah gate, (
13) is a separation circuit clock generation circuit, and (14) is a counting circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Patent Attorney Masu Oiwa Yudou 180 S I β Har 1 Lua Output T Mangoku I 2 G E 2 plots and 2 Djg Go Sun Moon 5th
2 Diagram 1-2 Flock diagram of 9Nf' no Takashi Ikuri Figure 1

Claims (1)

[Claims] From the output of a counter, the clock from the transmission line is input, D-flip-flops are continuously connected for the number of multiplexing lines, and the outputs of D-flip-flops other than the last stage are input to the first-stage D-flip-flops using a NOR gate. A line separation circuit that outputs a clock of the separation line and a synchronous line selection pulse, a decoder circuit that inputs the counter output of the line separation circuit, converts the input multiplexed code series into serial-to-parallel, and demultiplexes it, and the line separation circuit. One AND gate inputs the synchronous line selection pulse and the separated line clock, and the output of this one AND gate is input to generate a frame synchronization pattern in synchronization with the separated line clock at the synchronous line selection pulse position. A sync pattern generator, another AND gate into which the sync line selection pulse output from the line separation circuit and the decoder circuit output are input, and the output of this other AND gate is compared with the output of the sync pattern generator. The bits at the positions where the synchronization line selection pulses of the channels to which frame synchronization signals are to be inserted are compared among the separated channels, and if they do not match, a shift pulse is output with a width of 1 bit of the separated line clock. D at one stage before the final stage of the counter of the line separation circuit
- a frame synchronization circuit comprising: a mismatch circuit for resetting the flip-flop;