JPH02172097A - Memory - Google Patents

Abstract

PURPOSE:To reduce the access time by starting asynchronously memory readout and applying plural processings simultaneously. CONSTITUTION:An output of a row selection register 7 and a column selection register 8 require a setup time of a pipeline register of a delay time D2-stage to apply memory access and a readout signal from a memory cell array 13 is sensed by a sense amplifier 14. An output of the amplifier 14 is fetched by an output data register 150 or 151 after a time D3. The registers 150, 151 are controlled by a delay circuit 18, a FF 19 and a switching circuit 20 to sore the output of the amplifier 14 alternately. The selector 22 is controlled by an output fetch end signal OUTDONE and the FF 21 and the result of readout stored in the registers 150, 151 is selected alternately and outputted to output terminals DOUTO - DOUTK via an output buffer 23. Thus, the circuit is operated in a shorter cycle than the access time.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to memory, and in particular, the memory cycle time is shortened by providing multiple registers or latches in the memory depth, and multiple memory reads/writes can be processed simultaneously. Regarding memory.

[Conventional technology]

A pipeline register (or latch) is provided in the memory chip to hold the addresses, write data, read data, etc. of read/write requests issued in succession, separately from the read/write requests being processed within the chip. A semiconductor memory has been developed and is called a registered SRAM or a pipeline SRAM.

Pipeline operation in semiconductor memory refers to dividing the processing process (read/write processing) into multiple small processes (hereinafter referred to as stages) that can operate independently, and processing multiple memory requests in a workflow manner. It means to continue.

On the other hand, non-pipelined semiconductor memory is
It is a semiconductor memory that basically becomes ready to accept the next request every time one read/write request is completed. In other words, in non-pipelined semiconductor memory, the time from when a read/write request is submitted to the memory until the processing is completed (hereinafter referred to as memory access time) and the time from when a read/write request is submitted to the memory are The possible time intervals (hereinafter referred to as memory cycle times) are approximately equal.

Pipeline memory has a memory cycle time shorter than memory access time and a higher throughput than non-pipelined memory. For example, AMD's AM9151 uses a latch in the output stage of read data from memory. and simultaneously processes subsequent read/write requests while outputting data as a processing result of a certain memory read request to the outside of the chip. Also, GigaBit.

Logic's 12GO14 has an input register and an output register, and is capable of pipeline operation.

Further, as a further development of this idea, an address decoder and
It also has temporary memory between the driver and the memory cell array.
The processing in the address decoder/driver and the memory cell array is shown as stages that can each operate independently.

However, such a pipeline memory is characterized in that each pipelined stage is operated in synchronization, and synchronization causes the problem of increased access time. Further, this synchronization signal must be supplied from outside the semiconductor memory (usually a clock is used), and supplying the synchronization signal to all memory chips incorporated in the system increases the cost and power consumption of the entire device. Additionally, compatibility issues with conventional non-pipelined memories that can initiate memory access cycles asynchronously remain. Hereinafter, the set point during the access time increase will be specifically explained.

The problem of increased access time caused by pipelining and synchronization is that the processing time of each stage that makes up the pipeline
This is because it is difficult to make the times exactly equal to each other. For example, if a pipeline consists of a first stage that requires a processing time of 20 ns and a second stage that requires a processing time of Ions, the minimum cycle time is 20 ns (the processing time of the first stage that requires a maximum processing time ), a synchronization signal is also given every 20 ns. Here, the access time is 40 ns (20 ns x 2) because the pipeline has two stages, and the access time, which would have been 30 ns if not pipelined, is reduced to 1 by pipelined and providing a synchronization signal.
This will result in a Qnsec delay.

As a solution to this problem, there is a patent application publication No. 62-295484 by the same inventor as the present invention. The outline will be explained with reference to the drawings. FIG. 5 is a block diagram showing the configuration of an embodiment of the above-mentioned patent application publication No. 62-295484, and FIG. 6 is a part of its timing chart. In this example, the address decoder stage takes time, and the memory cell array read stage takes D2 time, and although D1 is D2, access is limited to the slower memory cell array read stage. The time will not be twice as long as D2, and it will be just D,+D2.

[Problem to be solved by the invention] However, the above-mentioned Patent Application Publication No. 1982-295
When attempting to access the pipeline memory according to the invention of No. 484 using a synchronous circuit, the following problems arise.

A synchronous circuit is controlled by a clock. When debugging a synchronous circuit, the tarok frequency is generally lowered. In extreme cases, debugging may be performed while manually advancing the clock one by one.

FIG. 7 shows timing charts when operating at the designed clock frequency and when operating at a lower clock frequency.

FIG. 7(a) is a timing chart when operating at the designed tarlock frequency.

Although not shown in the figure, a synchronous circuit outputs an address in synchronization with a clock. Read data is captured in synchronization with the second rising edge of the clock after the rising edge of the clock that outputs the address. The time from the access start edge to the data capture edge is 2T, where T is the clock repetition period.

The clock frequency is designed so that the pipeline memory access time D1+D2 is included within this 2T time and data can be taken in after 2T.

It is also designed to issue the next memory access while the previous memory access is being executed. That is,
The next memory access is issued in synchronization with the rising edge of the clock next to the rising edge of the clock that started the previous memory access, and the memory address is output. The operation will be explained below.

At time 11, the synchronous circuit synchronizes with the rising edge of the clock and selects address A! When the start signal 5TART is outputted, a control circuit (not shown) generates a start signal 5TART, which is applied to the corresponding terminal of the pipeline memory.

This signal causes the pipeline memory to start a memory cycle and operate as shown in FIG.
Output A/read data via i +D2 Output pins of data register 115 D OUT O ~ D OUT
Output to k. This A/read data is at time t3.
It is taken into the synchronous circuit in synchronization with the rising edge of the clock.

Further, at time t2, the synchronous circuit outputs addresses A and n in synchronization with the rising edge of the clock to start the second memory access. This memory access also operates as shown in FIG. 6, and Affi read data is output to output pins DOUTo to DOUTk after access time D1+D2. This read data is taken into the synchronous circuit in synchronization with the rising edge of the tarok at time t4.

The pipeline memory operates in this way and the synchronous circuit has Ai! The read data and the A1 read data are sequentially captured as shown in the captured data in FIG. 7(a). However, d is the delay time of the captured data from the rising edge of the clock.

On the other hand, FIG. 7(b) is a timing chart when the clock frequency is reduced to 1/2.

Since the clock frequency has become 172, reading of address A is completed at time t2, but A! The read data capture timing is time t3 synchronized with the rising edge of the clock. However, at time t2, a read access to address A is started in synchronization with the rise of the clock, and the access time D1+D2
After that, the A and R read data is output to the output data register 1.
15 output pins DOUTo to DOUTk.

Now that the clock frequency is 172, A/
Time t, which is the timing of importing KW data
AI that was in the output data register 15 before reaching 3! This will destroy the read data. Therefore, the A0 read data is included at time t3 when the A/read data should be taken in.

In other words, Patent Application Publication No. 62-295484
When a synchronous circuit accesses the pipeline memory according to the invention, there is a lower limit to the clock frequency, and access cannot be made at a frequency lower than the lower limit frequency.

An object of the present invention is to realize a high-speed pipeline memory in which there is no lower limit frequency for access by a synchronous circuit, and in which the access time is less than twice that of the pipeline stage with the longest processing time. It is in.

[Means to solve the problem]

A memory according to the present invention includes an input circuit for inputting an address signal, an address decoder/driver, a memory cell array, a sense amplifier, an output circuit for outputting a memory read result, and a read/write control circuit. a first temporary memory that stores the output of the input circuit and inputs it to the address decoder/driver; and a second temporary memory that stores the decoded address that is the output of the address decoder/driver and inputs it to the memory cell array. , and two third temporary memories that store the memory read results output from the sense amplifier that captures and amplifies the output of the memory cell array and input them to the output circuit, and are input asynchronously with the preceding memory access cycle. When a processing start signal is input, the output of the address input circuit is first latched into the first temporary memory, and then after a delay time equal to the processing in the address decoder/driver has elapsed. The decoded address is latched into the temporary memory of memory 2, and then the read processing from the memory cell array is finalized, and after a delay time equal to the processing at the sense amplifier is finalized, the two third
The output of the sense amplifier is latched in the non-temporary memory of the temporary memory that latches the data read by the preceding memory access that precedes the current memory access, and each time the retrieval control signal is input, the output of the sense amplifier is 3rd above
The present invention is characterized in that by alternately switching and selecting the output of the temporary storage and outputting the memory read result through the output circuit, memory read is started asynchronously and multiple processes can be performed simultaneously.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor memory showing one embodiment of the present invention.

In the figure, 1 to 4.7 to 10.150.151 are registers introduced with the adoption of the pipeline system, and may be replaced by latches.

1 to 4 constitute an input register group, which receives input from outside the chip. The row address input register 1 receives the row address input terminal signals CA, ~CA1, the column address input register 2 receives the column address input terminal signal RA O'' RA +, and the write data input register 3 receives the write data input terminal signals DINo ~ DINk. The control signal input register 4 receives the ``writable'' input terminal signal Tπ) and the start signal 5TART, respectively.

Row address decoder 5 is connected to row address input register 1 . The column address decoder is also connected to the column address input register 2.

7 to 10 are a group of pipeline registers installed in the middle of processing within the memory chip. In this embodiment, the row address decoder 5 and the column address decoder 6 are installed between the memory cell array 13, but the row address decoder 5 and the column address decoder 6 may be divided into two stages and installed between them. do not have. Further, each of these pipeline registers 7 to 10 may have a multi-stage configuration. Each pipeline register from 7 to 10 has a
After the start signal 5TART is input, a data capture signal is applied after a delay time D.

The memory cell array 13 is an array of a large number of static memory cells.

The write circuit 11 writes to the memory cell array 13.

The read/write control circuit 12 generates a read enable signal RE and sends it to the sense amplifier 14 in accordance with the write enable signal WE received via the control signal input register 4 and the control signal register 10. is created and sent to the write circuit 11.

The sense amplifier 14 detects a weak signal read from the memory cell array 13 and determines the memory read result.

Output data register 150 and output data register 1
51 receives the memory read result from the sense amplifier 14 and stores it in accordance with the data acquisition signal. After inputting the start signal 5TART, this data acquisition signal is
It is applied via the switching circuit 20 after a delay time of 1+D2.

The delay circuit 16 has a delay time required for address decoding +
This is a delay circuit with a delay time D1 equal to the setup time of the pipeline register, and a start signal 5TA.
When RT is input, a capture signal is supplied to each pipeline register 7.8.9 and 10 after a delay time Dl, and is also supplied as an input signal to the delay circuit 17.

The delay circuit 17 is a delay circuit having a delay time D2 equal to the delay time required for memory cell access and sensing + the setup time of the pipeline register, and when the output signal of the delay circuit 16 is input, the output signal is output after the delay time D2. , provides its output signal to the switching circuit 20 and the delay circuit 18.

The delay circuit 18 is a delay circuit having a delay time D3 that is sufficiently shorter than the longer delay time of the delay time D1 and the delay time D2 minus the operating time of one flip-flop, and the output of the delay circuit 17 When a signal is input, the output signal is given to one flip-flop after a delay time D3.

The flip-flop 19 is a T-type flip-flop, and inverts the output selection signal 5ELI in synchronization with the rising edge of the input signal provided by the delay circuit 18. This selection signal SEL.

is applied to the switching circuit 20 as a control signal.

The switching circuit 20 is controlled by the selection signal 5ELL, which is the output of one flip-flop, and applies a data acquisition signal to either the output data register 150 or the output data register 151.

The flip-flop 21 is a T-type flip-flop 1. At step B, the selection signal 5EL2, which is the output, is inverted in synchronization with the rise of the output capture completion signal 0UTDONE. This selection signal 5EL2 is applied to the selector 22 as a control signal.

The selector 22 is controlled by the selection signal 5EL2 which is the output of the flip-flop 21, and the output data register 1
50 or output data register 151 is selected and output.

The output buffer 23 buffers the output of the selector 22 and sends it to output terminals DOUTO to DOUTk.

The data read operation will be described below with reference to FIG. 1 and FIG. 2, which is a timing chart of this embodiment.

In the data read operation, first, the row address input terminal signals CAo to CAI are connected to the start signal 5TART.
At the rising edge of , it is taken into the row address input register 1 and becomes its output. On the other hand, in parallel with this, the column address input terminal signals RAO to RAI are also stored in the column address input register 6 at the rising edge of the start signal 5TART and become its output.

Next, the outputs of the row address input, register 1, and column address input register 2 are address decoded using a delay time DI minus the set-up time of the next stage pipeline register, and after the delay time DI, the outputs of the row address input register 1 and the column address input register 2 are decoded. It is taken into register 8 and becomes an output. Row address input terminal signals CA and -CAI are decoded in row address decoder 5, and column address input terminal signals RAo to RA are decoded in column address decoder 6, respectively.

Furthermore, the outputs of the row selection register 7 and the column selection register 8 require a delay time D2 minus the set-up time of the next stage pipeline register to perform memory cell access, and the memory read signal is sensed by the sense amplifier 14. The output of the sense amplifier 14 is taken into the output data register 150 or the output data register 151 after a delay time D2 and becomes its output.

Output data register 150 and output data register 1
51 is a delay circuit 18. Controlled by a flip-flop 19 and a switching circuit 20, the sense amplifier 1
Store the output of 4. One of the stored read results is selected by the selector 22. The selector 22 is controlled by the output capture completion signal 0UTDONE and the flip-flop 21, and according to the output capture completion signal, alternately selects the read results stored in the output data register 150 and the output data register 151 and outputs them via the output buffer 23. output terminals DOUTO~DOU
Output to Tk.

Here, an asynchronous pipeline operation in a data read operation will be explained using FIG.

Application of row address input terminal signal CAo-CA and column address input terminal signal RAo-RA and start signal 5
The minimum value of the activation interval (memory cycle time) of memory access by TART is determined by the maximum value of processing delay time at each pipeline stage within the chip. In this embodiment, the processing delay due to memory cell access and sensing is longer than the address decoding processing delay at the pipeline stage. Therefore, the delay time D2, which is the sum of the pipeline register set-up time and the delay time due to memory cell access and sensing, guarantees the minimum value of the memory cycle time.

In FIG. 2, address A is applied in the next cycle after inputting address A/. Row address input register 1 and column address input register 2 prevent the input of address A7 from colliding with the decoding of the preceding input of address A/. Similarly, when the output of these address input registers becomes address A1, address A! The decoding result for line) 1! It is held by selection register 7 and column selection register 8, and memory cell access is started.

Now, the sense amplifier 14 outputs data at address A/, data at address A, and data at address An in this order. By the operation of the delay circuit 18 and the flip-flop 19, the switching circuit 20 outputs the start signal 5TART (input of the switching circuit 20 in FIG. 2) delayed by the delay circuits 16 and 17 to the data register 150.
and are added alternately to the output data register 151, so
The output data register 150 outputs the data at address AI and the data at address A7, and the output data register 151 outputs the data at address A1 and the data at address A0 at the timings shown in FIG. 2, respectively.

On the other hand, the flip-flop 21 is controlled by the output capture completion signal outdone, and the selection signal 5EL2 is
Changes as shown in the figure. This selection signal 5EL2 causes the selector 22 to alternately select the outputs of the output data register 150 and the output data register 151 and add them to the output buffer 23, so that the output terminals DOUTo to DOU
Address A is sent to Tk at the timing shown in Figure 2.
! data at address A, data at address A.

data, address A. The data is output in the following order.

As can be seen from this timing diagram, at the rising edge of the output capture completion signal, the output terminal D OUT
Since the read data at the desired address has been determined in DOUTk, the circuit that accesses the semiconductor memory of this embodiment can capture the read data in synchronization with the rise of the output capture completion signal.

As shown in FIG. 2, the semiconductor memory of this embodiment has a first stage (outside the chip → address input registers 1 and 2) and a second stage (address input registers 1 and 2 → address decoder) with the pipeline register as the boundary. 5, 6 → row/column selection register 7.8), third stage (row/column selection register 7.8 → memory cell array 13 → sense amplifier 14)
→ output registers 150, 151) and the fourth stage (output registers 150, 151 → output buffer 23 → outside the chip) can independently service different memory read requests.

As described above, it has been shown that it is possible to perform memory reads one after another in a memory cycle time that is shorter than the memory access time, and that it is possible to start a memory access cycle asynchronously with a preceding request.

Next, the case where the semiconductor memory of this embodiment is read by the synchronous circuit will be explained with reference to FIG.

As shown in FIG. 3, the synchronous circuit receives the clock signal CLOC.
Operates in synchronization with the K signal. That is, the tarokk signal C
It outputs an address in synchronization with the rising edge of LOCK, and also takes in data in synchronization with the rising edge of clock CLOCK. Therefore, as shown in FIG.
When the start 5TART and output capture completion signal 0UTDONE are applied to the semiconductor memory of this embodiment along with the address in synchronization with the rise of OCK, it operates in the same manner as described above. Since the synchronous circuit takes in data in synchronization with the rising edge of the CLOCK signal, the address A/ is shown in the double input data in FIG.

Read data can be captured in the order of A, , A, , Ao.

Next, the frequency of the clock CLOCK of the synchronous circuit is 1/2
The operation in this case will be explained with reference to FIG.

Since the synchronous circuit operates in synchronization with the clock CLOCK, the address, output capture completion signal ○UTDONE, and start signal 5TART are all clocked by the clock CLOCK.
delayed in sync with.

As shown in FIG. 4, the output data register 150 stores the data at address A and the data at address A, and the output data register 151 stores the data at address Affi and the data at Oyobi address A0 in this order. Since the selection signal SEL, which is the output of the flip-flop 21 controlled by the output capture completion signal 0UTDONE, changes as shown in the figure, the data stored in the output data register 150 and the output data register 151 are alternately selected by the selector 22. The data at addresses A/, Am, and AfiAo are sequentially output to the output terminals DOUTo to DOUTk as shown in the figure. The synchronous circuit uses the clock CLO
Data is fetched in synchronization with the rising edge of CK, so the addresses A/, Am, A are read as shown in the captured data in the figure.
The data of n and Ao are taken into the condyle.

The operation at the time of writing is the same as the invention described in the patent application publication No. 62-295484 described above, so the explanation will be omitted.

In this embodiment, the output data is switched to the next data at the timing when the output capture is completed, but the data to be captured may be output at the timing when the output capture is started.

〔Effect of the invention〕

As described above, the memory according to the present invention operates in a shorter cycle than the access time by performing pipeline operation, and even when the processing times of the pipe stages are different, compared to the case without pipeline operation. Patent Application Publication No. 62-295484 states that the increase in access time is only due to the operation time of the pipeline register.
In addition to exhibiting the same effect as the invention of 2.0, when accessed by a synchronous circuit, the synchronous circuit can take in correct data even if the frequency of the clock signal becomes 1/2 or less.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a timing chart of asynchronous access during data read operation, Fig. 3 is a timing chart of synchronous access during data read operation, and Fig. 4 is a clock chart. A timing chart of synchronous access during data read operation when the signal frequency is reduced to 1/2. Figure 5 is a block diagram of a conventional asynchronous pipeline memory. Figure 6 is a diagram of a conventional asynchronous pipeline memory. Timing charts 1 to 7 during read operation are timing charts during read operation when a conventional asynchronous pipeline memory is accessed by a synchronous circuit. In FIG. 1, 1 is a row address input register, 2 is a column address input register, 3 is a write data register,
4 is a control signal input register, 5 is a row address decoder,
6 is a column address decoder, 7 is a row selection register, 8 is a column selection register, 9 is a write data register, 10 is a control signal register, 11 is a write circuit, 12 is a read/write control circuit, 13 is a memory cell array, 14 is a Sense amplifier, 150.151 is output data register,
16, 17, 18 are delay circuits, 1 is a flip-flop, 20 is a switching circuit, 21 is a flip-flop, 22
is a selector, and 23 is an output buffer.

Claims (4)

[Claims] (1) In a memory comprising an input circuit for inputting an address signal, an address decoder/driver, a memory cell array, a sense amplifier, an output circuit for outputting a memory read result, and a read/write control circuit, the input circuit and stores the output of the address decoder.
A first temporary memory that inputs to the driver, a second temporary memory that stores the decoded address that is the output of the address decoder/driver and inputs it to the memory cell array, and captures and amplifies the output of the memory cell array. Two third temporary memories are provided to store the memory read results output from the sense amplifier and input them to the output circuit, and when a processing start signal is input asynchronously with the preceding memory access cycle, First, the output of the input circuit is latched in the first temporary memory, and then the decoded address is stored in the second temporary memory after a delay time equal to the time when the processing in the address decoder/driver is finalized. Then, after a delay time equal to the time when the read processing from the memory cell array is finalized and the processing at the sense amplifier is finalized, the current memory of the two third temporary memories is latched. The output of the sense amplifier is latched in the non-temporary memory of the one that latched the read data by the preceding memory access that precedes the access, and the output of the two third temporary memories is output every time the retrieval control signal is input. 1. A memory characterized in that a memory read is started asynchronously and a plurality of processes are performed simultaneously by alternately switching and selecting and outputting a memory read result through the output circuit. (2) Each of the first to third temporary storage circuits can be used by switching between a function of temporarily storing and outputting an input signal and a function of passing the input signal as is without storing it. The memory according to claim 1, characterized in that: (3) The input circuit that inputs the address signal, the address decoder/driver, the memory cell array, the sense amplifier, the output circuit that outputs the memory read result, the read/write control circuit, and the input circuit. In a memory comprising a circuit for detecting a change in an address signal, a first temporary memory stores an output of the input circuit and inputs it to the address decoder/driver, and a decoded address that is an output of the address decoder/driver. a second temporary memory that stores and inputs the memory cell array to the memory cell array; and two third temporary memories that store the memory read result output from the sense amplifier that takes in and amplifies the output of the memory cell array and input it to the output circuit. A memory is provided, and when a change in the address signal applied to the input circuit is used as a processing start signal, and a memory read access cycle is started asynchronously with the preceding memory cycle, first the data is stored in the first temporary memory. latching the output of the input circuit;
Next, the decoded address is latched into the second temporary memory after a delay time equal to the time when the processing in the address decoder/driver is finalized, and then the read processing from the memory cell array is finalized. , after a delay time equal to the time when the processing in the sense amplifier is finalized, one of the two third temporary memories latches the read data from the previous memory access that precedes the current memory access. The output of the sense amplifier is latched in the non-temporary memory, and each time the retrieval control signal is input, the outputs of the two third temporary memories are alternately switched and selected, and the memory read result is sent through the output circuit. A memory characterized by starting memory reading asynchronously and performing multiple processes simultaneously by outputting. (4) Each of the first to third temporary storage circuits can be used by switching between a function of temporarily storing and outputting an input signal and a function of passing the input signal as is without storing it. The memory according to claim 3, characterized in that: