JPH02163848A - Assignment method for shared memory address and information process system - Google Patents

Abstract

PURPOSE:To effectively use a memory address space of an information processing system by deciding optionally the address of a shared memory of each adaptor via a host processor and setting the address of the shared memory to a shared memory address register of each adaptor. CONSTITUTION:The address area assigned to a shared memory 19 of each adaptor 12 is kept in a variable state. Then a host processor 1 assigns a proper address area to each memory 19 when a system is formed or changed. In other words, the processor 1 assigns variably an address area to the memory 19 of each adaptor 12 and sets the head address to a shared memory address register. Thus the occupied area of a memory address space is reduced despite of the presence of many adaptor types and at the same time the duplication of address areas of the memory 19 can be eliminated.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention provides an information processing system in which a plurality of adapters each having a built-in shared memory can be installed, in which addresses can be efficiently assigned to the shared memory of each adapter. This article relates to a possible shared memory address allocation method.

[Prior Art] Conventionally, in information processing systems, various adapters that support general-purpose interfaces have been prepared in order to meet various requests from users. There are a wide variety of such adapters, such as line connection adapters, LANFjIl adapters, and external device control adapters. Information processing devices such as workstations in which these adapters are to be installed are generally provided with a plurality of slots (connectors), and any combination of various adapters can be installed in any slot.

An example of a method for exchanging information between a processor of an information processing device and an adapter installed in the information processing device is the one disclosed in Japanese Patent Application Laid-Open No. 57-89128. In this method, a memory area for information exchange is provided on the main memory, and the adapter section accesses this memory area using DMA (direct memory access).
On the other hand, the processor sections exchange information with each other by accessing them with memory read/write commands.

However, with this method, ■ an increase in the amount of information (for example, an increase from 256 bytes of transferred data to 4 kilobytes), an increase in the number of buffers due to the increase in the speed of M (parallel processing), ■ an increase in the number of buffers due to high-performance control, Due to various factors such as an increase in the number of programs, a large amount of main memory capacity is required, resulting in a problem of insufficient main memory capacity.

Therefore, in recent years, each adapter has a shared memory that can be accessed by both the host processor and the local processor on each adapter. By fixedly allocating address areas agreed upon between the host processor and various adapters, information can be transferred between them.

[Problems to be Solved by the Invention] However, in this way, fixedly allocating the shared memory address of each adapter for each adapter type has the following problem.

i) Since shared memory addresses are fixedly allocated to various types of adapters, there is a risk that the allocated address space will be insufficient.

n) on the memory address space of the upper processor.

If an adapter is installed in a system that has a different area allocated to shared memory, there is a possibility that the shared memory address of the adapter will overlap with the system area.

The present invention has been made in order to solve such conventional problems, and eliminates the fear of insufficient shared memory area in the memory address space of a host processor, and also eliminates the fear that the shared memory address area in the memory address space is insufficient. An object of the present invention is to provide a shared memory address allocation method that allows an adapter to be installed even in different systems, and an information processing system and adapter implementing this method.

[Means for Solving the Problems] In order to achieve the above object 1), the shared memory address allocation method according to the present invention is capable of mounting a plurality of adapters each having a shared memory that can be accessed from both upper and lower processors. A method for allocating shared memory addresses in an information processing system, in which the address area to be allocated to the shared memory of each adapter is made variable,
At the time of system construction or modification, the host processor recognizes the type of installed adapter and allocates a unique address area to each shared memory of the installed adapter.

Further, an information processing system according to the present invention includes a plurality of types of adapters each having a shared memory and an information processing device having a slot in which the plurality of types of adapters can be installed,
In an information processing system in which information is exchanged between the adapter and an information processing device via a shared memory installed in the adapter, the information processing device has a Wr.
The adapter having the shared memory has processor means for checking the type of adapter installed therein, determining an address area to be allocated to the adapter, and providing address information corresponding to the address area to the adapter, and the adapter having the shared memory The processor is characterized by comprising: address information holding means for holding address information given by the means; and means for controlling access to the shared memory by the processor means in accordance with the address information held by the means. be.

In this system, preferably, an access control is further provided for inhibiting access to the shared memory of the adapter until the address information holding means of the adapter holds the address information.

Furthermore, in the adapter according to the present invention, in the adapter having a local processor and a shared memory that is accessible from both the local processor and a higher-level processor, an address area in a self-memory address space allocated to the shared memory by the higher-level processor is provided. address information holding means for holding address information corresponding to the upper processor; address information setting means for setting address information from the upper processor into the holding means; access detection means for detecting access to said shared memory from said access detection means; and memory control means for reading and writing addresses within said allocated address area in accordance with the detection output of said access detection means. It is characterized by:

Preferably, this adapter further includes an access feature that inhibits access to the shared memory until address information is set in the address information holding means.

[Operations] In the configuration of the present invention described above, when a system is constructed by mounting an adapter having a shared memory.

Or, when an adapter is added or changed, the higher-level processor checks which adapter type is installed, and if it recognizes that an adapter with shared memory is installed, it uses the known shared memory of that adapter. 8
Based on this, the address area to be allocated to the shared memory is determined from the free area in its own memory address space. Next, the address information corresponding to this determined address area is held in the holding means within the adapter.

Thereafter, this adapter recognizes that an address in the address area assigned to its own shared memory is an access from an upper processor to its own shared memory.

In addition, due to the effect of the above possibility, even if the adapter is installed in the slot, the above is possible until the address area is allocated to its shared memory (e.g. until the address information is held in its holding means). prevents erroneous memory access by suppressing access to shared memory.

According to the present invention, the address area of the shared memory is not determined fixedly for each adapter type, but by allocating a new address area only for the installed adapter, the memory of the upper processor is Address space can be used efficiently. Furthermore, since the address allocated to the shared memory is determined for each system, there is no risk of duplication of the address 91 area as in the past, and the same adapter group can be shared by different systems.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 2 shows a block diagram of an information processing system to which the present invention is applied.

This system consists of a host processor 1, a main memory 2, and a slot 3 (
It consists of slots #0) to 6 (slot #3) and a group of adapters installed in these slots. The four slots from slot #O to slot #3 have adapters 8 (adapter A) to adapter 13 shown in FIG.
(Adapter F) is installed.

FIG. 5 illustrates the presence or absence of shared memory and the capacity of shared memory for these adapters. The host processor 1 accesses the shared memory of the adapter F from adapter 8 to exchange information.

Fig. 2 is a diagram showing the configuration of adapters installed in slot #0 to slot #3. is not equipped with an adapter, and adapter C without shared memory is installed in slot #2.
Furthermore, a configuration is shown in which an adapter E having a 1 Mbyte shared memory is installed in slot #3. Hereinafter, in order to simplify the explanation, a description will be given according to this configuration example.

As shown in FIG. 3, each slot #1 to #3 has a terminal a for connection with an adapter mounted in that slot.
, b. Each of these terminals is connected to either a high potential level or a low potential level (here either to a 5 volt potential through a resistor, or to ground), thereby giving each slot a unique numbering. There is.

FIG. 4 shows the address structure of the memory address space of the upper processor 1 of FIG. 2.

When confirming whether an adapter is installed in any slot or not, the host processor 1 accesses adapters A to F in order (to all adapters). On the other hand, if each accessed adapter is mounted in slot #0 to slot #3, the host processor 1 is informed of the number of the slot in which it is mounted. In addition, if each adapter is not installed in slot #0 to slot #3, the upper processor 1 monitors the response with a timer,
If there is no response for a certain period of time, it is assumed that the time has expired, and the adapter is recognized as not being installed in any slot.

In this configuration example, the host processor 1 first accesses the adapter A. On the other hand, adapter A is installed in slot #3.
Next, access adapter B. On the other hand, since adapter B is not installed in any of slots #0 to slot #3 and does not respond, the upper processor 1 times out and recognizes that adapter B is not installed. Hereinafter, the above-mentioned access is also performed from adapter C to adapter F to understand the configuration of the adapter. The system configuration recognized in this way is
It is stored in a hard disk device or the like. The system configuration confirmation process for this adapter needs to be performed when building or changing the system.

When the upper processor 1 is powered on or initialized,
Information about adapters A to F (presence or absence of shared memory and capacity of shared memory) is checked from the main memory or hard disk device, etc. to confirm information about the currently installed adapters.

According to this adapter information, adapter E with 2 Mbytes of shared memory is installed in slot #O, no adapter is installed in slot #1, and adapter C without shared memory is installed in slot #2.

Furthermore, it can be confirmed that adapter A having IM bytes of shared memory is installed in slot #3. Based on this recognition, as shown in FIG.

Regarding adapter E installed in slot #O on the shared memory area of the memory address space of host processor 1, its shared memory 2M bytes is allocated to a 2M byte area (
For example, it is assigned to addresses AOOOOOO to BFFFFF), and nothing is done about slot #1 and slot #2 because there is no shared memory.

For adapter A installed in slot #3, its shared memory 91M bytes is transferred to a 1M byte area (for example,
Assigned to addresses C00OOO~CFFFFF).

FIG. 1 shows a system configuration together with a specific example of the configuration of the adapter (E) 12 shown in FIG. 6. The configurations of other adapters having shared memory are basically the same.

In FIG. 1, the system bus 7 of FIG.

It is composed of a control bus 22, an address bus 23, and a data bus 24. Adapter E also includes a shared memory address register 15, a suppression flag register 1G, and an address control unit 14 that controls both registers.
, a shared memory 19 that can be accessed from both the host processor 1 and the local processor 20 , an access control section 17 and a memory control section 18 that control access to this shared memory 19 , the local processor 20 , and the local bus 21 . configured.

The address control section 14 includes an address section 27 that fixedly holds the address "60000" of the address register of the adapter E, an address comparison section 25 that compares this address with the address of the address bus 23, and this comparison section. 2
and a register control section 26 that sets address information in the address register 15 and resets the inhibition flag register 16 based on the match output of No. 5. The access control unit 17 also includes an address comparison unit 28 that compares the address information set in the address register 15 and the address on the address bus 23, and a match output from the comparison unit 28 when the inhibition flag register 16 is not set. and an inhibition flag confirmation unit 29 that notifies the memory control unit 18 that there has been a memory access in response to the request.

The shared memory address setting operation will be explained in detail below with reference to FIG.

The upper processor 1 stores the start address "Aooooo" of the shared memory area of the adapter E allocated as shown in FIG.
The address comparator 25 in the address control unit 14 issues a write command to write to the address "0000").
600000'' is the address of the self-shared memory address register, and if the addresses match (in this case, they match), the register control unit 26 uses the write command sent from the control bus 22 to write the address to the data bus 24. The register control unit 26 loads the data sent from the shared memory area (starting address "AOOOOOO" of the shared memory area) into the shared memory address register 15. At the same time, the register control unit 26 resets the inhibition flag register 16.

This inhibition flag register 16 is ? ta is turned off when a large amount of power is invested, inhibiting access to the shared memory 19 from the higher-level processor 1, but is reset at this point, making it possible for the higher-level processor 1 to access the shared memory 19. Become.

Next, information exchange between the host processor 1 and the adapter E will be explained with reference to FIG. For example, “A1
00OO"). Therefore, the address comparison section 28 in the access control section 17 determines that the output address "A100OO" corresponds to the shared memory 19.
It is determined whether or not the address exists within the address area (AOOOOOO to BFFFFF). In the case of this adapter E, the capacity of the shared memory 19 is 2M bytes, so the method for this determination is to determine whether or not the upper three pins of the 24-bit address match. If the adapter A has a capacity of 1 Mbyte, the comparator 28 may be configured to compare the upper 4 bits.

After this determination, if it is determined that this memory access is an access to the shared memory 19 of this adapter, the inhibition flag register confirmation unit 29 determines that the inhibition flag register 16 has been reset (the shared memory address register 15
(address is set). If the inhibition flag register 16 is reset, the memory control unit 1
8 is a control bus 22, an address bus 23. Take in information (read address "A100OO") from the data bus 24. After taking in this information, the memory control unit 1
8 checks whether there is an access from the local processor 20. If there is no access from the local processor 20, the above address "A10" is sent to the shared memory 19.
The relative address of "0OO" is confirmed and the information of the relative address is read. In this case, the lower 21 bits of the address are used as is as the access address of the shared memory 19.

The information thus read out is sent to the upper processor l via the data bus 24. Furthermore, if there is an access from the local processor 20 or if access is made at the same time, the memory control unit 18 performs the above control on the shared memory 19 after the access by the local processor 20 is completed, and sends the information to the upper processor 1. send. Here, priority is given to shared memory access by the local processor 20, but either may be given priority depending on the purpose.

According to this embodiment, the upper processor variably allocates an address area to the shared memory possessed by each adapter and sets the start address to the shared memory address register. ,
occupies less memory address space, and
This has the effect that the shared memory address areas do not overlap.

Although the preferred embodiment of the present invention has been described above, various changes can be made without departing from the gist of the present invention.1 For example, in the above embodiment, the address of the adapter may be fixed for each adapter type. However, it may be determined uniquely depending on the slot in which the adapter is installed.
Such a technique has been proposed by the present applicant in Japanese Patent Application No. Sho-2. As a result, the number of shared memory address register ports allocated to the adapter shown in Figure 4 is:
The number of adapter addresses required is determined by the number of slots rather than the number of adapter types, and the ratio of adapter addresses to the memory address space of the upper processor is reduced. Furthermore, when detecting installed adapters, instead of sequentially checking addresses for all adapter types, it is sufficient to check addresses for all slots, simplifying and speeding up the process. Renmyo: The adapter installed in the slot of.

A unique address is assigned to that slot, and when this address is received, the adapter rD assigned to each adapter is returned to the upper processor. According to this configuration, it is also possible to mount a plurality of adapters of the same type on the same device.

Furthermore, it is also possible to mount a mixture of adapters with a conventional configuration in which shared memory addresses are fixedly determined.

[Effects of the Invention] Since the present invention is configured as described above, it produces the effects described below.

The upper processor arbitrarily determines the address of the shared memory of each adapter, and sets this address in the shared memory address register of each adapter. This allows the system to be configured easily even when various types of adapters with shared memory are used in the same system. Memory address space can be used efficiently. Furthermore, it can also be installed in devices whose upper processors have different memory address spaces.

[Brief explanation of the drawing]

Figure 1 shows an adapter according to the present invention! FIG. 2 is a block diagram of an information processing system to which the present invention is applied; FIG. 3 is an explanatory diagram of a specific example of each slot in FIG. 2 and an example of mounting an adapter; FIG. 5 is an explanatory diagram of the memory address space of the host processor, FIG. 5 is an explanatory diagram of the system configuration of the adapter shown in FIG. 3, and FIG. 6 is an explanatory diagram of various adapters. 1... Upper processor, 2... Main memory, 3...
6...Slot #0 to 3.7...System bus, 8
~13...Adapter A-F, 14...Address control unit, 15...Shared memory address register, 16...
- Inhibition flag register, 17... access control unit, 1
8... Memory control unit, 19... Shared memory, 20.
... Local processor, 21 ... Local bus, 2
2...Control bus, 23...Address bus,
24...Data bus. Applicant: Hitachi, Ltd.

Claims (1)

[Scope of Claims] 1. A shared memory address allocation method in an information processing system capable of mounting a plurality of adapters each having a shared memory that can be accessed by both upper and lower processors, wherein the shared memory address is allocated to each adapter's shared memory. The shared memory is characterized in that the address area to be used is made variable, and at the time of system construction or modification, the host processor recognizes the type of the installed adapter and allocates a unique address area to each shared memory of the installed adapter. Memory address allocation method. 2. Equipped with multiple types of adapters each having a shared memory and an information processing device having a slot into which the multiple types of adapters can be installed, and between the adapter and the information processing device via the shared memory built into the adapter. In an information processing system that exchanges information, the information processing device checks the type of adapter installed in the slot, determines an address area to be allocated to the adapter, and transfers address information corresponding to the address area to the adapter. The adapter having the shared memory includes address information holding means for holding address information given by the processor means, and address information holding means for holding the address information held by the processor means, and the adapter having the shared memory. An information processing system comprising: means for controlling access to the shared memory. 3. The information processing system according to claim 2, further comprising access inhibiting means for inhibiting the adapter from accessing the shared memory until the address information retaining means of the adapter retains the address information. 4. In an adapter having a local processor and a shared memory that is accessible from both the local processor and a higher-level processor, address information corresponding to an address area in its own memory address space that the higher-level processor allocates to the shared memory. address information holding means for holding address information; address information setting means for setting address information from the upper processor into the holding means; and address information setting means for setting address information from the upper processor to the shared memory in accordance with the address information held in the holding means. An adapter comprising: access detection means for detecting access; and memory control means for writing/reading addresses within the allocated address area in accordance with the detection output of the access detection means. 5. The adapter according to claim 4, further comprising access inhibiting means for inhibiting access to said shared memory until address information is set in said address information holding means.