JPH02166832A - Clock phase control circuit for clock generator - Google Patents

Abstract

PURPOSE:To minimize the skip quantity of a clock phase, and to prevent the drop-out of data, etc., by detecting phase difference between a current using clock and a spare clock, and performing adjustment so that the phase difference of both clocks becomes smaller. CONSTITUTION:The phase difference of the output clocks by a current using system clock generating part 51 and a spare system clock generating part 52 respectively is detected by a phase difference detecting part 53. A phase adjusting part 54 adjusts the phase of the spare system clock or the current system clock, and the phase difference of both the clocks becomes minimum. Accordingly, even when the clock is switched, the skip quantity of the clock phase becomes minimum, and the data drop-out, etc., can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a clock phase control circuit for a clock generator that generates clocks for active and standby systems in devices such as time division multiplexing (TDM) devices.

The purpose of this is to minimize the amount of clock phase jump when switching between working and backup clocks to prevent data loss, etc.

The phase difference detection unit detects the phase difference between the active system output clock and the protection system output clock, and the phase difference detection unit detects the phase difference between the active system output clock and the protection system output clock based on the phase difference detected by the single output clock. and a phase adjustment section that adjusts the phase difference between the two.

[Industrial application field]

The present invention relates to a clock phase control circuit for a clock generator that generates active and backup clocks in various devices such as time division multiplexing (TDM) devices.

In recent years, there has been a demand for improved reliability in various communication devices, and it is necessary to redundant circuits in important parts within the device to reduce the failure rate of the device. Similarly, duplication of circuits is being attempted for clock generators, and in this case, it is necessary to ensure that data loss does not occur due to transient clock phase slips when switching between the active system and the backup system. .

[Conventional technology]

The conventional duplex clock generation value W is as follows.

The active system and backup system clock generators are provided separately and independently, and when a failure occurs such as a disconnection of the output clock of the active system clock generator, the active system clock generator is simply switched to the backup system clock generator. . As a result, there is no correlation between the clocks generated in the active system and the protection system, and when duplex switching is performed, a phase jump occurs between the active and protection output clocks.

[Problem to be solved by the invention]

If a clock phase jump occurs during switching between working and standby as described above, during the switching transition period.

There is a problem in that when a relatively long momentary interruption occurs in a line or the like, the processing of transmitted and received data is not performed normally, and the data during that period is lost.

Therefore, an object of the present invention is to minimize the clock phase jump f&I when switching between the active system and the standby system to prevent data loss and the like.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention.

A clock phase control circuit for a clock generation device according to the present invention is a clock generation device with a duplex configuration including an active clock generation section 51 and a standby clock generation section 52.
A phase difference detection section 53 detects the phase difference between the working system output clock and the standby system output clock, and the phase of the working system output clock or the standby system output clock is set to one phase based on the phase difference detected by the two phase difference detecting sections 53. It also includes a phase adjustment section 54 that adjusts to reduce the phase difference between output clocks.

[Effect]

The phase difference detection section 53 detects the phase difference between the output clocks between the working clock generation section 51 and the protection clock generation section 52, and the phase adjustment section 54 adjusts the output clock to the working system or the protection system so that this phase difference becomes small. Adjust the clock phase. This also applies when the output clocks of the active system and standby system are switched.

Since the jump in clock phase is small, it is possible to reduce data loss due to instantaneous interruptions and the like.

〔Example〕

The present invention will be described in detail below with reference to two drawings.

FIG. 2 is a block diagram showing a clock phase control circuit of a clock generator as an embodiment of the present invention. In this embodiment, the present invention is applied to a lock source having a duplex structure in a time division multiplexing device.

In FIG. 2, reference numeral 1 denotes a PLL control crank generation unit that extracts the signal clock CIJ from the transmission signal of the telephone line, and the extracted clock CLK is the active system clock generation unit 2.
and is input to the standby system clock generation section 3.

The active system clock generator 2 has a phase synchronization circuit 21 that generates a clock CLK o that is phase-synchronized with the extracted clock CLK from the PLL control clock generator l.This clock CLK is frequency-divided to generate the active system at various speeds. It is configured to include a clock generation section 22 that generates a system clock CLK2.

In addition to the phase synchronization circuit 31 and clock generation section 32 similar to those described above, the standby clock generation section 3 includes a clock generation section 32.
The clock control section 33 adjusts the phase of each speed output clock CLKa to generate a standby system clock CLK3. The clock control unit 33 controls the output lock CLK of each speed from the clock generation unit 32.
4 and the output clock CLK2 of each speed from the active system clock generator 2, and select each output clock CLK of the clock generator 32 so that the phase difference is small.
4 is a circuit for controlling the phase.

An example of the configuration of this clock control section 33 is shown in FIG.

In order to simplify the explanation, this configuration example shows the configuration of the clock control unit only for the system clock of one clock speed.In reality, a circuit similar to that shown in Fig. 3 is used for the system clock of each speed. It is provided for each.

In FIG. 3, 331 is a differentiation circuit that differentiates the output clock CL from the clock generation unit 32 by 4 and detects the rising edge of the clock, and 332 is the output of the phase synchronization circuit 31 while being reset by the rising edge detection output of the differentiation circuit 331. A counter 333 counts the number of clocks CLK, and the count value of the counter 332 is counted by the active system clock generator 2.
334 is a phase difference detection unit 33 that latches at the rising timing of the active system clock CLK 2 from CLK 2.
This is a phase control unit that shifts the phase 4 of the output clock CL from the clock generation unit 32 by a phase amount corresponding to the magnitude of the phase difference detection output 3. This phase control section 334 can be configured with a variable shift register.

The operation of this embodiment device will be explained below.

Normally, the clock CLK extracted by the PLL 1 clock generation section 1 is input to the active system clock generation section 2, and a phase-synchronized clock CL whose phase is synchronized with this clock CLK is input to the active system clock generation section 2.
0 is generated in the phase locked circuit 21. This clock C
LK o is further divided into several frequencies by a clock generating section 22 to generate active system clocks CLK 2 of various signal speeds, which are supplied to each section of the time division multiplexing device.

Similarly, in the standby system clock generation section 3, the clock generation section 32 generates output clocks CLK 4 at various speeds, and the clock control section 33 converts 4 into the active system clock CL into 2. The phases are compared and the phase difference is detected. In this phase difference detection, the counter 332 starts counting at the rising edge of the output clock CLK 4 of the standby system clock generating section 32, and the count value is latched by the phase difference detecting section 333 at the rising timing of the active system clock CLK 2. As a result, the phase difference detection unit 333 successively latches a count value corresponding to the phase difference between the active system clock CLK 2 and the protection output clock C 4.

The phase control unit 334 outputs the output clock CLK from the standby clock generation unit 32 according to the count value latched by the phase difference detection unit 333, that is, the phase difference between the two clocks.
4, thereby matching the phase of clock 3 with the system clocks CLK 2 and CL of the active and standby systems.

This allows both system clocks CLK 2 and CLK 3 to
It is always controlled so that there is no phase difference between the two. As a result, even if clock switching occurs between the active system and the protection system (A system), the jump in the clock phase can be made extremely small, and the data loss that occurs during the switching between the active system and the protection system can be minimized.

Various modifications are possible in carrying out the present invention. For example, in the above-described embodiment, the present invention was applied to two clock generators, a working clock generator and a standby clock generator, but it is of course possible to apply the present invention to three or more clock generators. It is also combustible that it is common. Also in the above embodiment.

Although the configuration has been described so as to control the phase of the output clock of the protection system clock generation section, the present invention is not limited to this, and it is also possible to control the phase of the output clock of the working system clock generation section, and also to control the phase of the output clock of the working system clock generation section. The clock phases may be mutually controlled.

〔Effect of the invention〕

According to the present invention, the amount of clock phase jump when switching between the active system and the standby system is minimized, and as a result, data loss and the like can be prevented when switching the clocks.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a block diagram showing a configuration when the clock phase control circuit of a clock generator according to an embodiment of the present invention is applied to a time division multiplexing device, and FIG. It is a block diagram showing an example of composition of a door part. In fig. 1-PLL control clock generation section 2-working system clock generation section 3-standby system clock generation section 21.31-one phase synchronization circuit 22.32--clock generation section 33-clock control section 33L-m- Differentiation circuit 332 - counter 333 - phase difference detection section 334 - phase control section CLK2 - active system clock CLK3 - standby system clock γ

Claims (1)

[Scope of Claims] In a clock generation device with a duplex configuration including a working system clock generation section (51) and a protection system clock generation section (52), a phase difference between the working system output clock and the protection system output clock is detected. a phase difference detection section (53);
53) A clock generator comprising: a phase adjustment section (54) that adjusts the phase of the working system output clock or the standby system output clock based on the phase difference detected by 53) so as to reduce the phase difference between the two output clocks; Device clock phase control circuit.