JPH02165660A - Electronic parts - Google Patents
Electronic partsInfo
- Publication number
- JPH02165660A JPH02165660A JP32096588A JP32096588A JPH02165660A JP H02165660 A JPH02165660 A JP H02165660A JP 32096588 A JP32096588 A JP 32096588A JP 32096588 A JP32096588 A JP 32096588A JP H02165660 A JPH02165660 A JP H02165660A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- electronic circuit
- semiconductor chip
- circuit chip
- circuit pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 19
- 238000007789 sealing Methods 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 abstract description 39
- 230000007261 regionalization Effects 0.000 abstract 3
- 230000005855 radiation Effects 0.000 abstract 1
- 230000017525 heat dissipation Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 239000000919 ceramic Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 239000012611 container material Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- LTPBRCUWZOMYOC-UHFFFAOYSA-N Beryllium oxide Chemical compound O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
Abstract
Description
【発明の詳細な説明】
[発明の目的コ
(産業上の利用分野)
本発明は、電子部品に関し、特に電子回路チップの固定
構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention (Field of Industrial Application)] The present invention relates to electronic components, and particularly to a fixing structure for electronic circuit chips.
(従来の技術)
近年、機器の軽薄短小化の要求はとどまるところを知ら
ないほどに強まっている。さらに、その機能、性能の向
上が要求されており、当然の結果として、実装における
改善、新しい実装技術の要望が強くなっている。(Prior Art) In recent years, the demand for devices to be lighter, thinner, shorter, and smaller has become unstoppable. Furthermore, improvements in their functionality and performance are required, and as a natural result, there is a strong demand for improvements in implementation and new implementation techniques.
しかし、小型化を進める上では、作る側、使う側の両方
で問題が出てくる。However, in advancing miniaturization, problems arise for both manufacturers and users.
たとえば、小型化には優れた材料、工法の開発、導入が
必要であり、また、経済的な観点からしても、設備のコ
ストが上がり、使用の効率も下がり、設備の償却の負担
が上がるなどの聞届がある。For example, miniaturization requires the development and introduction of superior materials and construction methods, and from an economic perspective, the cost of equipment increases, the efficiency of its use decreases, and the burden of depreciation of equipment increases. There are reports such as.
一方、小型化されたチップ部品を使う側は、小さすぎる
ために部品の取り扱いが煩わしく1、紛失したり取り違
えたりすることも少なくなかった。On the other hand, those who use miniaturized chip components find it difficult to handle the components because they are too small1, and they are often lost or mixed up.
そこで、これらの解決方法の一つとして、小型化された
チップを、最終の取り扱い者が使用しやすいような寸法
のパッケージに入れるということが行なわれている。One solution to these problems is to package miniaturized chips in packages with dimensions that are convenient for use by the final handler.
このような半導体パッケージは、チップを収容する容器
材料として、セラミックス、ガラス、メタル、プラスチ
ックなどを用いて、これらの容器に半導体チップを接合
し、続いて、チップ電極部と容器に形成されている導体
部とをワイヤーボンディングによって電気的に接続して
いる。Such a semiconductor package uses ceramics, glass, metal, plastic, etc. as a container material to house the chip, and the semiconductor chip is bonded to these containers, and then chip electrodes and the container are formed. The conductor portion is electrically connected by wire bonding.
i5図はこのような従来の電子部品の構造を示す断面図
で、同図において、電子回路チップの支持部材となる容
器1には電子回路チップとしてたとえば半導体チップ2
が全面で固定されている。Figure i5 is a cross-sectional view showing the structure of such a conventional electronic component. In the figure, a container 1 serving as a support member for an electronic circuit chip contains, for example, a semiconductor chip 2 as an electronic circuit chip.
is fixed throughout.
また、容器1は半導体チップ2を接続するための導体部
3を有しており、半導体チップ2と導体部3はボンディ
ングワイヤー4によって電気的に接続されている。Further, the container 1 has a conductor part 3 for connecting the semiconductor chip 2, and the semiconductor chip 2 and the conductor part 3 are electrically connected by a bonding wire 4.
こうして容器1内に収容された半導体チップ2および導
体部3は、封止メタル5によって封止され、さらに、こ
の電子部品を他の装置に接続するためのリードビン6が
容器1に接続されている。The semiconductor chip 2 and conductor portion 3 thus housed in the container 1 are sealed with a sealing metal 5, and a lead bin 6 for connecting the electronic component to other devices is further connected to the container 1. .
すなわち、この半導体チップ2は完全に容器1内に密封
され、外気から遮断された状態となっている。That is, this semiconductor chip 2 is completely sealed within the container 1 and is in a state of being cut off from the outside air.
なお、容器の封止には、周囲がメタライズされたアルミ
ナ製の蓋をAu−8nブリホームを用いてはんだ付けし
たり、ウェルドリングにメタル製の蓋を電気抵抗溶接す
る方法がとられている。The containers are sealed by soldering an alumina lid with a metalized periphery using Au-8n preform, or by electric resistance welding a metal lid to a weld ring. .
また、チップを樹脂で直接封じ込む樹脂封止も行なわれ
ている。Resin sealing, in which the chip is directly sealed with resin, is also used.
(発明が解決しようとする課8)
ところで、ICの高集積化に伴い、半導体素子の動作時
の発熱量が増大し、この半導体パッケージの放熱性が問
題となってきた。(Problem 8 to be Solved by the Invention) Incidentally, as ICs become more highly integrated, the amount of heat generated during operation of semiconductor elements increases, and the heat dissipation performance of semiconductor packages has become a problem.
このため、高熱伝導性を有する窒化アルミニウムセラミ
ックスやベリリアセラミックスが容器材料として多用さ
れ始めている。For this reason, aluminum nitride ceramics and beryllia ceramics, which have high thermal conductivity, have begun to be frequently used as container materials.
しかしながら、これらのセラミックスにも熱伝導率には
限界があり、放熱性の聞届は、実装の高密度化を図る妨
げとなっている。However, these ceramics also have a limit in thermal conductivity, and the lack of heat dissipation performance is an impediment to achieving higher packaging density.
また、電子部品の動作時の温度が高くなるにつれ、電子
回路チップの絶縁基板として使用されるシリコンなどの
半導体材料と容器などの支持部材との熱膨張率の差が問
題になってきた。Furthermore, as the operating temperature of electronic components increases, the difference in thermal expansion coefficient between a semiconductor material such as silicon used as an insulating substrate of an electronic circuit chip and a support member such as a container has become a problem.
つまり、容器材料と半導体チップとの熱膨張率の差によ
って応力が働き、半導体チップにクラックが発生するケ
ースがみられ、したがって、熱膨張率を考慮して容器材
料を選択しなければならなくなっている。In other words, the difference in thermal expansion coefficient between the container material and the semiconductor chip causes stress, which can cause cracks in the semiconductor chip. Therefore, the container material must be selected with the thermal expansion coefficient taken into consideration. There is.
本発明は、このような問題に対処してなされたもので、
放熱性に優れ、材料の選択が容易な電子部品を提供する
ことを目的とする。The present invention was made in response to such problems.
The purpose is to provide electronic components with excellent heat dissipation properties and easy selection of materials.
〔発明の構成]
(課題を解決するための手段)
本発明の電子部品は、絶縁チップ上に所定の回路パター
ンが形成された電子回路チップと、この電子回路チップ
を支持する支持開口部が形成され前記電子回路チップの
回路パターンを接続する導体部を有するチップ支持部材
とを備え、前記電子回路チップを回路パターン形成面が
前記導体部と同一側に向くように前記チップ支持部材に
固定し、前記電子回路チップの回路パターン形成面およ
びこの回路パターンを接続した前記導体部を封止部材で
封止したことを特徴としている。[Structure of the Invention] (Means for Solving the Problems) The electronic component of the present invention includes an electronic circuit chip in which a predetermined circuit pattern is formed on an insulating chip, and a support opening that supports the electronic circuit chip. and a chip support member having a conductor portion connecting the circuit pattern of the electronic circuit chip, and fixing the electronic circuit chip to the chip support member such that the circuit pattern forming surface faces the same side as the conductor portion, The circuit pattern forming surface of the electronic circuit chip and the conductor portion to which the circuit pattern is connected are sealed with a sealing member.
(作 用)
本発明の電子部品によれば、電子回路チップを支持する
支持部材にチップを支持する支持開口部が形成され、上
記電子回路チップの回路パターン形成面が、上記支持部
材に設けられている導体部と共に封止されるように電子
回路チップを支持部材に固定している。(Function) According to the electronic component of the present invention, a support opening that supports the chip is formed in the support member that supports the electronic circuit chip, and the circuit pattern forming surface of the electronic circuit chip is provided in the support member. The electronic circuit chip is fixed to the support member so as to be sealed together with the conductor portion.
したがって、電子回路チップの絶縁チップ面が封止され
た電子部品外部の空気と直接接触しており、チップ−空
気間で熱放散が行われるため、放熱性を向上させること
ができる。Therefore, the insulating chip surface of the electronic circuit chip is in direct contact with the air outside the sealed electronic component, and heat is dissipated between the chip and the air, so that heat dissipation can be improved.
そして一方、電子回路チップの回路パターン形成面は封
止されているため、回路パターンは保護される。On the other hand, since the circuit pattern forming surface of the electronic circuit chip is sealed, the circuit pattern is protected.
また、このように電子回路チップが外部に露出している
ため、送風することなどによってチップの冷却時間を短
縮することができる。Further, since the electronic circuit chip is exposed to the outside in this way, the cooling time of the chip can be shortened by blowing air or the like.
また、電子回路チップと支持部材との接合面積が少ない
ため、チップと支持部材との熱膨張率の差によって生じ
る応力の影響が小さく、支持部材材料の選択が容易とな
る。Further, since the bonding area between the electronic circuit chip and the support member is small, the influence of stress caused by the difference in coefficient of thermal expansion between the chip and the support member is small, and the selection of the support member material is facilitated.
(実施例)
次に、本発明の実施例について図面を用いて具体的に説
明する。なお、第5図と同一部分には同一符号を付して
重複する部分の説明を省略する。(Example) Next, an example of the present invention will be specifically described using the drawings. Note that the same parts as in FIG. 5 are given the same reference numerals, and the explanation of the overlapping parts will be omitted.
実施例1
第1図は本発明の一実施例における半導体パッケージの
構造を示した図であり、第2図は第1図で示した半導体
パッケージの断面図である。Embodiment 1 FIG. 1 is a diagram showing the structure of a semiconductor package in an embodiment of the present invention, and FIG. 2 is a sectional view of the semiconductor package shown in FIG. 1.
支持部材となる容器1には電子回路チップとしての半導
体チップ2を支持する支持開口部10が形成されている
。A support opening 10 for supporting a semiconductor chip 2 as an electronic circuit chip is formed in a container 1 serving as a support member.
そして、半導体チップ2は、回路パターン形成面が導体
部3と同一側に向いた状態で容器1に固定されている。The semiconductor chip 2 is fixed to the container 1 with the circuit pattern forming surface facing the same side as the conductor portion 3.
この実施例における固定は、半導体チップ2の回路パタ
ーン形成面が容2ri1と接する状態で行ったものであ
る。The fixing in this example was carried out with the circuit pattern formed surface of the semiconductor chip 2 in contact with the capacitor 2ri1.
このような電子部品は、たとえば以下のようにして作製
される。Such an electronic component is manufactured, for example, as follows.
はじめに、窒化アルミニウムを主成分とするセラミック
スグリーンシートにパンチングによってスルーホールを
形成すると同時に、半導体チップを固定する部分にこれ
を支持する支持開口部を形成する。First, through-holes are formed by punching in a ceramic green sheet whose main component is aluminum nitride, and at the same time, support openings for supporting the semiconductor chip are formed in the portion where the semiconductor chip is to be fixed.
次いで、タングステンなどの導体ペーストをスクリーン
印刷によってスルーホールに充填し、さらにグリーンシ
ート上に所望の回路パターンを印刷する。Next, the through holes are filled with a conductive paste such as tungsten by screen printing, and a desired circuit pattern is printed on the green sheet.
そして、これらのグリーンシートを熱圧着によって積層
一体化し、脱脂、焼成を行い、セラミックス多層基板の
容器を作製する。Then, these green sheets are laminated and integrated by thermocompression bonding, degreased, and fired to produce a ceramic multilayer substrate container.
その後、半導体チップをフェイスダウンで、容器に形成
した支持開口部を塞ぐように容器に固定し、さらに、こ
の半導体チップと容器に形成されている導体部とをワイ
ヤーボンディングで電気的に接続する。Thereafter, the semiconductor chip is fixed face down to the container so as to close the support opening formed in the container, and the semiconductor chip and the conductor portion formed in the container are electrically connected by wire bonding.
最後に、封止部材としてメタルを用い、容器下部を封止
してパッケージとする。Finally, the lower part of the container is sealed using metal as a sealing member to form a package.
このような方法を用いて作製された電子部品は、半導体
チップの回路パターンが封正によって保護されると同時
に、この半導体チップの絶縁基板面は空気と接している
ため、放熱性が良好であった。Electronic components manufactured using this method have good heat dissipation properties because the circuit pattern of the semiconductor chip is protected by sealing, and the insulating substrate surface of the semiconductor chip is in contact with air. Ta.
さらに、チップの接合面積が削減されたため接合剤の使
用量を節約することができ、コストダウンを図ることが
できた。Furthermore, since the bonding area of the chip was reduced, the amount of bonding agent used could be reduced, leading to cost reductions.
また、容器の材料の選択が容品で、半導体チップと容器
材料の熱膨張率に差がある場合でも、クラックなどの発
生率は従来構造の電子部品と比較すると大幅に減少した
。Furthermore, even when the material for the container was selected as a container and there was a difference in the coefficient of thermal expansion between the semiconductor chip and the container material, the incidence of cracks was significantly reduced compared to electronic components with conventional structures.
実施例2
第3図は、本発明の他の実施例を示した図である。なお
、符号は第1図と同一である。Embodiment 2 FIG. 3 is a diagram showing another embodiment of the present invention. Note that the symbols are the same as in FIG. 1.
この実施例は、半導体チップ2を容器1の支持開口部1
0に固定する際、半導体チップ2の絶縁基板面が容器1
と接するように固定したものである。すなわち容器1の
内側で固定した状態となっている。In this embodiment, the semiconductor chip 2 is placed in the support opening 1 of the container 1.
0, the insulating substrate surface of the semiconductor chip 2 is fixed to the container 1.
It is fixed so that it is in contact with the That is, it is in a fixed state inside the container 1.
このような構造でも実施例1と同様の効果を得ることが
できた。Even with such a structure, the same effects as in Example 1 could be obtained.
実施例3
第4図は、本発明のさらに別の実施例を示した断面図で
ある。Embodiment 3 FIG. 4 is a sectional view showing still another embodiment of the present invention.
同図において、チップ支持部材であるプリント基板11
には導体部3が印刷されており、半導体チップ2が実施
例1と同一の状態でプリント基板11に固定されている
。In the figure, a printed circuit board 11 which is a chip support member is shown.
A conductor portion 3 is printed on the substrate, and a semiconductor chip 2 is fixed to a printed circuit board 11 in the same state as in the first embodiment.
また、半導体チップ2の回路パターンは導体部3とボン
ディングワイヤー4によって電気的に接続されている。Further, the circuit pattern of the semiconductor chip 2 is electrically connected to the conductor portion 3 by a bonding wire 4.
そして、上記半導体チップ2の回路パターンおよび導体
部3は、封止部材として樹脂15を用い、ボッティング
によって封止されている。The circuit pattern and conductor portion 3 of the semiconductor chip 2 are sealed by botting using a resin 15 as a sealing member.
このような構造を取入れることによって、半導体チップ
の取付けが容易になり、さらに、支持開口部の部分がキ
ャビティ部の役目を果たすため封止性が向上した。By adopting such a structure, it becomes easy to attach the semiconductor chip, and further, the sealing performance is improved because the support opening part serves as a cavity part.
これらの結果から明らかなように、容器の半導体チップ
を固定する部分に支持開口部を形成し、半導体チップを
容器外部の空気と接触させることにより、放熱性を向上
させることができた。As is clear from these results, by forming a support opening in the portion of the container where the semiconductor chip is fixed and bringing the semiconductor chip into contact with the air outside the container, heat dissipation could be improved.
また、支持開口部の面積骨、半導体チップと容器とを接
合する接合材の使用量が少なくてすむため、コストダウ
ンを図ることができた。Further, since the area of the support opening and the amount of bonding material used to bond the semiconductor chip and the container can be reduced, costs can be reduced.
[発明の効果]
以上説明したように、本発明の電子部品によれば、電子
回路チップの回路パターン形成面が封正によって保護さ
れると同時に、この電子回路チップの絶縁基板面は電子
部品外部の空気と接する状態となり、熱放散が半導体チ
ップ−空気間で行われ、放熱性が向上する。[Effects of the Invention] As explained above, according to the electronic component of the present invention, the circuit pattern forming surface of the electronic circuit chip is protected by sealing, and at the same time, the insulating substrate surface of the electronic circuit chip is protected from the outside of the electronic component. The semiconductor chip is in contact with the air, and heat dissipation occurs between the semiconductor chip and the air, improving heat dissipation.
したがって、より高密度化を図ることが可能となる。Therefore, it becomes possible to achieve higher density.
また、電子回路チップと支持部材との接合面積が少ない
ため、熱膨張率の差による接合不良が減少し、支持部材
の材料の選択が容易となる。Furthermore, since the bonding area between the electronic circuit chip and the support member is small, bonding defects due to differences in thermal expansion coefficients are reduced, and the material for the support member can be easily selected.
第1図は本発明の一実施例の電子部品の構造を示す図、
第2図は第1図の断面図、第3図および第4図は本発明
の他の実施例の断面図、第5図は従来の電子部品の断面
図である。
1・・・・・・・・・容器
2・・・・・・・・・半導体チップ
3・・・・・・・・・導体部
4・・・・・・・・・ボンディングワイヤー5・・・・
・・・・・封止メタル
6・・・・・・・・・リードピン
10・・・・・・支持開口部
出願人 株式会社 東芝FIG. 1 is a diagram showing the structure of an electronic component according to an embodiment of the present invention;
FIG. 2 is a sectional view of FIG. 1, FIGS. 3 and 4 are sectional views of other embodiments of the present invention, and FIG. 5 is a sectional view of a conventional electronic component. 1... Container 2... Semiconductor chip 3... Conductor portion 4... Bonding wire 5...・・・
... Sealing metal 6 ... Lead pin 10 ... Support opening Applicant: Toshiba Corporation
Claims (1)
電子回路チップと、この電子回路チップを支持する支持
開口部が形成され前記電子回路チップの回路パターンを
接続する導体部を有するチップ支持部材とを備え、前記
電子回路チップを回路パターン形成面が前記導体部と同
一側に向くように前記チップ支持部材に固定し、前記電
子回路チップの回路パターン形成面およびこの回路パタ
ーンを接続した前記導体部を封止部材で封止したことを
特徴とする電子部品。(1) A chip support member having an electronic circuit chip with a predetermined circuit pattern formed on an insulating chip, and a support opening that supports the electronic circuit chip and a conductor portion that connects the circuit pattern of the electronic circuit chip. The electronic circuit chip is fixed to the chip support member so that the circuit pattern forming surface faces the same side as the conductor part, and the circuit pattern forming surface of the electronic circuit chip and the conductor to which the circuit pattern is connected are provided. An electronic component characterized in that a portion of the electronic component is sealed with a sealing member.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32096588A JPH02165660A (en) | 1988-12-20 | 1988-12-20 | Electronic parts |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32096588A JPH02165660A (en) | 1988-12-20 | 1988-12-20 | Electronic parts |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02165660A true JPH02165660A (en) | 1990-06-26 |
Family
ID=18127275
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32096588A Pending JPH02165660A (en) | 1988-12-20 | 1988-12-20 | Electronic parts |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02165660A (en) |
-
1988
- 1988-12-20 JP JP32096588A patent/JPH02165660A/en active Pending
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