JPH0215487A - Memory card - Google Patents

Abstract

PURPOSE:To simplify a circuit and to enlarge memory capacity by arranging memory elements in plural columns and rows, selecting a column by a chip selecting line common to every column, and specifying one memory element by the output state of a writing/reading signal line common to every row. CONSTITUTION:Chip selecting signal lines CS1-CS16 are respectively connected to the memory ICs of the same column in rows G1 and G2 in common. Consequently, for the signal lines CS1-CS16, two ICs such as an IC01 and an IC17 in the rows G1 and G2 are simultaneously selected by a host address. Further, for each IC, a reding/writing control line is connected for every row in common. In this type of structure, a row is discriminated according to the H and L states of signals the inverse of OE1, OE2, WE1, and WE2, and one IC can be specified. Thus, the number of parts and the number of conductive patterns can be decreased, and the memory capacity can be enlarged.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a large number of semiconductor memory devices (hereinafter abbreviated as memory IC) called, for example, IC memory cards.
The present invention relates to a memory card containing a memory card, and particularly to a memory IC selection mechanism thereof.

[Conventional technology]

Memory cards have traditionally been used in, for example, word processors, hand belt computers, information gathering devices, or data file electronics. Memory cards have been commercialized in a wide variety of external shapes depending on their usage, but in recent years there has been a trend toward smaller and thinner memory cards as semiconductor I wave generation technology progresses.

[Problem to be solved by the invention]

This is not a big problem if the storage capacity is small, in other words, if the number of memory ICs installed is small, but if you try to manufacture a large capacity memory card, the number of memory ICs installed will inevitably increase, and both sides of the printed circuit board will need to be installed. It is necessary to install a memory IC in the For example, when manufacturing a memory card with a large capacity of about 1 megabyte (IMB), a large number of memory ICs, about 32, are required.

On the other hand, in the conventional memory IC chip selection method, the memory IC was selected at the time of access by decoding the upper address and connecting the decoded signal to C8 of each memory IC.

However, if this conventional chip selection method is applied to a large-capacity memory card as is, the number of O8 output terminals of the group array will be equal to the number of memory ICs mounted, that is, 3.
Two pieces are required.

This increase in the number of output terminals means that the shape of the conductive pattern on the printed circuit board becomes more and more complex.
The patterning work becomes complicated, leading to decreased productivity and increased costs.

In addition, there is a limit to the number of terminals for one gate array, and in addition to chip selection, a predetermined number of terminals for control signals, input/output terminals for address No. 48, etc. are required for the gate array. . Therefore, there is a limit to the number of terminals that can be used for chip selection, which poses a design difficulty.

An object of the present invention is to solve these problems and provide a memory card with a small number of parts and conductive patterns, and a large storage capacity. [Means for solving 1M] The above-mentioned To achieve the object, the present invention combines a large number of semiconductor memory devices and a single semiconductor memory device to be operated.
a gate array for selecting the chip select signal, the plurality of semiconductor memory elements are arranged in a plurality of columns and rows, and a chip select signal line and a signal line are commonly provided for each column, and the chip select signal line is provided in common for each column. The semiconductor memory element column is selected by the line, and one semiconductor memory is specified from the selected semiconductor memory element column by the output status of the write signal line and the read signal line. This is a characteristic feature.

[Embodiments of the invention]

Next, a memory card according to an embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 is an exploded perspective view of a block body in a memory card, FIG. 2 is a perspective view showing a state in which an upper liquid is attached to the block body, and FIG. 3 is a block diagram of the memory card.
FIG. 4 is a circuit diagram of the memory card.

First, the structure of the memory card will be explained using FIG. 1 and FIG. 2. The memory card according to this embodiment is roughly composed of a block body 1, an upper liquid 2, a lower nameplate, and a battery cover.

The block 1 is arranged in the upper frame 3 as shown in FIG.
, a printed circuit board 4 , a connector 5 , and a lower frame 6 . For convenience of illustration, FIG. 1 depicts the upper toolium 3 at the bottom and the lower frame 6 at the top.

The upper frame 3 has a rectangular frame 7;
Four parts are formed inside the recess to accommodate the printed circuit board 4 and the lower tool 6, and reinforcing ribs 8 are provided at predetermined intervals at parts corresponding to the tops of the recesses.

A connector positioning recess 9 is formed at the front end of the frame 7, and a groove 10 for preventing erroneous insertion is formed on both sides of the frame 7 at the front end so that the memory card can be inserted into the reader/writer without fail. is provided.

n) There are 32 memories I on both sides of the printed circuit board 4.
Circuit elements such as CI 1 and gate array 12 are mounted. As shown in FIG. 2, the memory chips C1l mounted on the top surface of the printed circuit board 4 are all aligned. The replenishment rib 8 of the upper frame 3 is inserted into the upper frame 3.

A connector 5 is integrally connected to the front end of the printed circuit board 4, and a battery terminal 13 is attached to the rear of the printed circuit board 4. A battery 14 such as a lithium battery (see Fig. 4) connected to this terminal 13 is a backup power source, and two batteries 14 are connected to the terminal 13 to provide long-term backup even in the event of a power outage. arranged in parallel.

A battery holding part 15 is integrally formed at the rear of the lower frame 6. As shown in FIG. The block body l is constructed by integrally connecting the upper frame 3 and the lower frame 6 with screws 16 via the screws 16.

After that, as shown in FIG. 2, the upper nameplate 2 is fixed to the surface of the block body 1 using hot melt adhesive.

A lower inscription Fi (not shown) is similarly fixed to the lower surface of the block body 1 using a hot melt adhesive. Furthermore, by storing a battery in the battery holding part 15 of the lower frame 6 and rotatably attaching a battery cover (not shown) above it,
Complete the memory card assembly.

Next, the circuit configuration of the memory card according to this embodiment will be explained using FIGS. 3 and 4.

As shown in FIG. 3, on the printed circuit board 4.

32 memory ICIs as mentioned above 1. In addition to the gate array 12, there are also a pull-up resistor 17 and a write protect switch 18 for preventing writing. Electrical DLT pressure monitoring circuit 19
Also provided are a pull-up control circuit 20 and the like.

The gate array No. 611 has 80 bin terminals, and the internal length of the signal line connected to each bin terminal is as shown in Table 1 below.

table Therefore, memory IC1 What is used to select 1?

There are 20 wires in total: 16 nap select signal lines, 2 read (OE) control lines, and 2 write (WE) front roll lines.

As shown in FIG. 4, the 32 memories IcI 1 are divided into a first group G1 and a second group G2 of 16 each, forming 16 columns and 2 rows. Then, 16 chip select signal lines (C8ffi line) decoded from the upper address (CS x to CS z
s ) are each commonly connected to one memory IG of the first group G1 and one memory IC of the second group G2, that is, commonly connected for each column. Also, the first
Each memory IC of group Gl has a first retcon 1-
roll line (δ1] line) and the first light control IA (
WEz line) are connected in common.

Further, in the second group G2, the second read control line (OE2 line) and the second write control line (WE
- wires) are connected in common.

A write signal line and a read signal line are commonly provided for each row.

Therefore, two memories ICI l are selected at the same time by one C8 signal line, but in order to distinguish between them, I'H of OEx, WE yu, OE z, WE z
The determination is made based on the states of J and rLJ.

To explain this more specifically, in FIG. 4, for example, when a selection signal is output to the CS x signal line,
Two memory ICs, rI'CIJ and rIc17J, are selected at the same time. Looking at the output states of OEx, WE Yu, OF2, and WEx at that time, for example, if OE 1 is “L”
'', if all the ponds are rHJ, it can be recognized that the memory IC of rlclJ has been identified and that reading into that memory IC is about to start.

The operation modes of this memory IC are summarized in Table 2 below.

The power source of the gate array 12 is backed up by a battery 14 so that the C8 signal is reliably output even if the commercial power source Vcc is not applied.

In addition, the voltage detection signal of the battery 14 can be output to a predetermined pin of the connector 5, but in order to prevent the battery from being charged by accidentally applying a voltage higher than the battery voltage from the outside, a charging prevention Connect diode 21 to connector 5 and battery 1
Further, a backflow prevention diode 22 is connected to each battery 14 in order to prevent backflow from other batteries 14 due to differences in discharge states.

The aforementioned power supply voltage monitoring circuit 19 constantly monitors the memory operating potential (usually 4.5 to 5.5 V), and for some reason (such as a power outage), the operating voltage may change to a preset threshold voltage ( For example, when it becomes lower than 4, OV), it is detected and a voltage drop (stop signal) is output to the voltage monitoring signal terminal of the gate array 12. Based on this signal, the gate array 12 The system retains the current memory contents and disables write/read operations.

In the above embodiment, the memory IC is divided into two groups, but the present invention is not limited to this.If the memory IC is divided into three or more groups, the number of terminals used in the gate array and the number of lines 48 can be further reduced. can do.

FIG. 5 is a diagram for explaining another embodiment of the present invention. Similarly, in this embodiment, 32 memory ICs are used, and these are divided into four groups of eight ICs each, namely, a first group Gl, a second group G2, and so on. The third group G3 and the fourth group G4 are divided into eight columns and four rows.

The C stone signal line is commonly connected to each column.

Furthermore, the method for selecting and specifying two memory ICs in which the 11 signal line and the W1 signal line are connected in common for each row is the same as in the embodiment described above, and therefore will not be described here.

In this example, as shown in the figure, there are 8 Kid lines, 4 τT1m lines, and 4 WE signal lines.
A total of 16 signal lines, one from 32 memory ICs.
memory ICs can be selected.

[Improving Effect] Since the present invention has the above-described configuration, even if the storage capacity of the memory card increases, or in other words, even if the number of memory ICs installed increases, the number of gate arrays does not increase. Without,
The number of signal lines (conductive patterns) can be reduced as much as possible, space can be saved accordingly, and storage capacity can further be increased.

[Brief explanation of the drawing]

All figures are for detailed explanation of the present invention.
The figure is an exploded perspective view of a block body in a memory card, Figure 2 is a perspective view showing a state in which the upper nameplate can be removed from the block body, Figure 3 is a block diagram of the memory card, and Figure 4
Figures a and 4b are circuit diagrams of the memory card, and Figure 5 is a block diagram of a memory card according to another embodiment. 4...Printed circuit board, 11...Memory I
C212...Gate array. rabbit drawing

Claims (1)

[Claims] (1) A gate array comprising a large number of semiconductor memory devices and a gate array for selecting one semiconductor memory device to be operated, and arranging the large number of semiconductor memory devices in a plurality of columns and rows, each column A common chip select signal line is provided for each
A write signal line and a read signal line are provided in common for each row, and the column of the semiconductor memory element is selected by the chip select signal line, and the column of the semiconductor memory element is selected by the output state of the write signal line and the read signal line. A memory card characterized in that it is configured to identify one semiconductor memory element from a selected semiconductor memory element column.